Common-mode Voltage Control Research Articles

A 0.6V 119 dB High-CMRR Low-NEF PGA with common-mode voltage control for ECG recording

This paper proposes a programmable gain amplifier (PGA) with common-mode voltage control for ECG recording. In order to ensure that input common-mode interference (CMI) does not deteriorate amplifier performance, a novel common-mode voltage control module is proposed, which soaks up CMI and maintains the common-mode input within the expected range. Utilizing a standard 65 nm CMOS process, our PGA runs on a 0.6 V supply. This amplifier has a frequency response range of 10 Hz–57.0 kHz, a gain range of 0 dB–24 dB, and a noise efficiency factor (NEF) of 4.17. Its common-mode rejection ratio (CMRR) is over 119.2 dB, and input reference noise within the amplifier bandwidth is 6.6 μVrms.

A Reduced Common-Mode Voltage Control Scheme for Three-Level H10 Converter Considering Dead-Time Effect

A Reduced Common-Mode Voltage Control Scheme for Three-Level H10 Converter Considering Dead-Time Effect

Novel SVPWM for Open Winding PMSM Drives With Simultaneous Common Mode Voltage Control and Full Frequency Zero Sequence Current Suppression

Zero sequence voltage (ZSV) can cause zero sequence current (ZSC), while variation of common mode voltage (CMV) can cause bearing current in an open winding (OW) permanent magnet synchronous machine (PMSM) fed by common dc -bus dual two-level inverters. This article proposes a novel space vector pulsewidth modulation (SVPWM) strategy for simultaneously eliminating CMV variation and suppressing full frequency ZSC harmonics in either linear or over modulation region by optimal selection of switching combinations. The proposed SVPWM can reduce large ZSV ripples and number of switching actions in the conventional CMV control method for the common dc -bus OW drive. Thus, high-frequency ZSC harmonics and switching frequency can be significantly reduced in both linear and over modulation regions. Moreover, the proposed SVPWM can suppress large low-frequency ZSC harmonics induced by the conventional method in over modulation region. The superior performances of CMV variation elimination and full frequency ZSC suppression in the proposed SVPWM are verified by experiments.

Stability Analysis of Bipolar LVDC Grid

The study and regulation of bipolar DC structures covered by asymmetrical action, the DC symmetric part approach is implemented. This approach is an expansion of the standard principle of symmetrical components in three phase AC-controlled networks. In typical and differential modes, the asymmetrical voltage and current in the positive and negative poles are separated into symmetric segments. For each mode, an analogous circuit is imitative, which produces decoupled case circuits. As a consequence, it provides autonomous recommendations of each situation and offers an informative mode of a bipolar DC power system's static and dynamic behavior. A common methodology which is relevant to numerous cases of device scheme is the DC symmetrical portion process. An improved common-mode voltage control scheme is defined as an example. By incorporating active damping regulation, it suppresses common mode LC resonance and decreases common-mode impedance to enhance power efficiency and stability of voltage. Matlab/Simulink effects validate the main theoretical assumptions.

Control Design of a 99% Efficiency Transformerless EV Charger Providing Standardized Grid Services

A nonisolated DC charger is proposed for electric vehicle (EV) battery system. The leakage current can be reduced by the novel charging system without bulky transformer. A zero sequence voltage control method is developed to stabilize the common-mode voltage, thus, reduce the leakage current. The proposed fast charger includes two energy conversion stages: DC–DC converter for battery side control; DC–AC converter for grid interface and common-mode voltage control. The parameters of the system with the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LCL</i> filter are analyzed and optimized for a better performance of grid interface. Grid service functions are designed for the EV charger to provide grid-voltage/frequency compensations. High power (22 kW) and high efficiency ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$&gt;$</tex-math></inline-formula> 99%) are achieved with low-leakage current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$&lt;$</tex-math></inline-formula> 20 mA). The experiments are implemented to verify the proposed EV charger system.

Efficiency‐enhanced and high‐precision of input common‐mode feedback control using OSA–CLS technique

Efficiency-enhanced and high-precision input common-mode feedback control (ICMFB) is proposed for a fully differential readout circuit of the MEMS capacitive sensor. This ICMFB improves the efficiency and performance of input common-mode voltage control using a smaller feedback capacitor. The noise performance of the readout circuit is improved as a decrease of a feedback capacitor. The correlated level shift (CLS) technique is used to improve the output swing of the amplifier therefore reduce the value of a feedback capacitor. Also, the oversampling successive approximation (OSA) technique is used to improve the accuracy of input common-mode voltage control using a low-gain op-amp. Simulation results show that the input common-mode voltage error decreases to 0.01% when the value of the feedback capacitor is the same as the MEMS sensor. Also, the noise power spectral density of the readout circuit increases by 10 dB.

Novel Predictive Control for the IPMSM Fed by the 3L-SNPC Inverter for EVAs: Modified Lyapunov Function, Computational Efficiency, and Delay Compensation

This paper proposes a novel predictive strategy based on a model predictive control (MPC) for the interior permanent magnet synchronous motors (IPMSMs) driven by a three-level simplified neutral-point clamped inverter (3L-SNPC) for electric vehicle applications (EVAs). Based on the prediction of the future behavior of the controlled variables, a predefined multiobjective cost function incorporates the control objectives which are evaluated for every sampling period to generate the optimal switching state applied directly to the inverter without the modulation stage. The control objectives in this paper are tracking current capacity, neutral-point voltage balancing, common-mode voltage control, and switching frequency reduction. The principal concepts of the novel scheme are summarized as follows: first, the delay compensation based on the long horizon of prediction is adopted by a multilevel power converter structure. Second, based on the modified Lyapunov candidate function, both stability and recursive feasibility are ensured of the proposed predictive scheme. Third, the practicability of the real-time implementation is improved by the proposed “static voltage vector” (SVV) and “single state variation” (SSV) principles. Finally, the proposed concepts are implemented in the novel predictive control formulation as additional constraints without compromising the complexity and the good performances of the predictive controller. Therefore, only the switching states that guarantee the stability and the reduction of calculation burden criteria are considered in the evaluation of cost function. The proposed predictive scheme based on the “SVV” principle has demonstrated superior performance in simulation compared with the proposed scheme with the “SSV” principle. The computational burden and switching frequency rates are reduced by 35% and 56.22%, respectively.

Zero-Sequence Current Suppression Strategy With Common-Mode Voltage Control for Open-End Winding PMSM Drives With Common DC Bus

The zero-sequence loop inherently exists in the structure of the three-phase open-end winding permanent-magnet synchronous machine (OW-PMSM) system with common dc bus, which provides the circulating path for zero-sequence current (ZSC) and consequently causes the torque ripple and extra system loss. Besides, the common-mode voltage (CMV), which can cause many negative effects, such as the bearing current and the failure of motor bearing, is another concern in the driving system. However, the simultaneous suppression of ZSC and the CMV control of the devices is investigated mainly in the application of the induction machine system and the multiphase OW-PMSM system, whereas it is ignored in the application of the three-phase OW-PMSM system, in which the suppression of ZSC is more complex considering the effect of flux linkage harmonic components. On this basis, this article proposes a strategy that can not only suppress the ZSC, but also eliminate the ripple of CMV in the three-phase OW-PMSM system. In the proposed method, the suppression of ZSC is achieved by synchronously adjusting the duration time of each phase within every control cycle based on the reference voltage of zero-sequence control loop, which can simplify the conventional rearrangement-based scheme. Furthermore, the duration time of each phase is distributed into each switch device of the two inverters, with the principle of eliminating the ripple of CMV. Consequently, both the suppression of ZSC and the CMV control can be achieved easily. Furthermore, the influence of dead time on the CMV control is analyzed, indicating that the CMV control is irrelevant with the dead time. Moreover, the effective modulation range of the proposed technique is analyzed. Finally, the experimental validation is conducted on a three-phase OW-PMSM system with common dc bus.

A triangular 3D coordinate system for multilevel SVPWM generation

This article presents a triangular coordinate system, a three-dimensional (3-D) coordinate system in which the three axes are oriented at 60° to each other. The 3-D representation of multilevel inverter voltage space vectors and generation of 3-D space vector pulsewidth modulation (3DSVPWM) using this coordinate system is proposed. The proposed 3DSVPWM method offers advantage of simplicity, amenable for implementation in field programmable gate arrays (FPGA) and application specific integrated circuits (ASICs), and flexibility for common-mode voltage control. The existing methods for 3DSVPWM generation operate on a 3-D space, with the axes oriented at 90°. The conventional 3DSVPWM methods require switching among four vectors, located at vertices of a tetrahedron, in a PWM cycle. In addition, the triangular coordinate system offers flexibility to directly extend any two-dimensional SVPWM (2DSVPWM) algorithm to 3-D, since it also involves switching of three vectors located at vertices of a triangle. The proposed method of 3DSVPWM generation is generalized and can be extended to any n-level inverter. The three vectors switched to approximate the reference vector and their corresponding durations are directly determined utilizing arithmetic operations. The coordinate system and the generation of SVPWM utilizing the triangular coordinate system is explained and experimentally validated on a dSPACE DS1104 platform for a five-level open-end winding inverter configuration and results are presented.

Simultaneous DC Current Balance and Common-Mode Voltage Control With Multilevel Current Source Inverters

The current source converter (CSC) has been popular in high-power medium-voltage applications. To increase the system power capacity and reduce the output harmonics, parallel connection of CSCs with multilevel current output is a practical approach. There are mainly two types of parallel based configurations. The structure with an independent dc link for each paralleled CSC can be regarded as the first configuration, where the dc current flowing into each CSC can be controlled from the rectifier side independently. The second type is constructed with only one current source rectifier (CSR) on the grid side and paralleled current source inverters (CSIs) on the load side, which could potentially reduce the cost and size of the system. However, with a common dc source, the dc current for each CSC should be carefully controlled with proper modulation design. At the same time, the common-mode voltage (CMV), which increases the motor line-to-ground voltage and causes additional stress to the insulation system, should also be suppressed. In this paper, with a focus on the shared dc-link structure, we thoroughly analyze the dc-link current flow and common-mode loop circuit. We propose a multilevel modulation strategy of the parallel CSI system considering the requirement of dc current balancing and CMV reduction to improve the overall system performance. The effectiveness of the proposed method is verified by both simulation and experiment in a transformerless parallel CSC system.

Finite State Predictive Current and Common Mode Voltage Control of a Seven-phase Voltage Source Inverter

&lt;p class="abstract"&gt;The paper elaborate finite set model based predictive current control of a seven-phase voltage source inverter. The current control is carried out considering a finite set of control actions. The space vector model of a seven-phase voltage source inverter (VSI) yields 2&lt;sup&gt;7&lt;/sup&gt; = 128 space voltage vectors, with 126 active and two zero vectors. The control method described in this paper discard some switching states from the whole set and employs reduced number of switching states to track the commanded current. Three sets of space vectors are used for switching actuation, in one case only 15 vectors are used (14 active and one zero), in second case 29 vectors are used (28 active and one zero) and finally 43 vectors (42 active and one zero) are employed. Optimal algorithm is employed to find the vector which minimizes the chosen cost function. The effect of selecting the cost function, the number of space vectors and the sampling time is investigated and reported. The developed technique is tested for RL load using simulation and experimental approaches.&lt;/p&gt;&lt;br /&gt;&lt;p class="Papertitle"&gt; &lt;/p&gt;

A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings

This paper presents a low power fast ON/OFF switchable voltage mode implementation of a driver/receiver pair intended to be used in high speed bit-serial Low Voltage Differential Signaling (LVDS) Address Event Representation (AER) chip grids, where short (like 32-bit) sparse data packages are transmitted. Voltage-Mode drivers require intrinsically half the power of their Current-Mode counterparts and do not require Common-Mode Voltage Control. However, for fast ON/OFF switching a special high-speed voltage regulator is required which needs to be kept ON during data pauses, and hence its power consumption must be minimized, resulting in tight design constraints. A proof-of-concept chip test prototype has been designed and fabricated in low-cost standard 0.35 μ m CMOS. At ± 500 mV voltage swing with 500 Mbps serial bit rate and 32 bit events, current consumption scales from 15.9 mA (7.7 mA for the driver and 8.2 mA for the receiver) at 10 Mevent/s rate to 406 μ A ( 343 μ A for the driver and 62.5 μA for the receiver) for an event rate below 10 Kevent/s, therefore achieving a rate dependent power saving of up to 40 times, while keeping switching times at 1.5 ns. Maximum achievable event rate was 13.7 Meps at 638 Mbps serial bit rate. Additionally, differential voltage swing is tunable, thus allowing further power reductions.

Front End ASIC design for SiPM readout

A Front End ASIC for the readout of Silicon Photo-Multipliers is presented with the following features: wide dynamic range, high speed, multi channel, low input impedance current preamplifier, low power (7mW per channel), DC coupled input with common mode voltage control and separated timing and charge signal output.A detailed description of the SiPM modeling and parameter extractionis also included allowing the emulation of the signal generated bydifferent commercial devices in the design simulation stage. Currentprototype is the first step for a more complex mixed signal designincluding more channels, analog processing and digital outputs, thusreducing power consumption and increasing integration. This prototypeincludes basic blocks for 3 channels with: preamplifier with twoseparate signal paths and fast current discriminator with digitaloutput.

A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique

A time-shifted correlated double sampling (CDS) technique is proposed in the design of a 10-bit 100-MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. An efficient common-mode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18-/spl mu/m CMOS process, the prototype 10-bit pipelined ADC occupies 2.5 mm/sup 2/ of active die area. With 1-MHz input signal, it achieves 65-dB SFDR and 54-dB SNDR at 100MS/s. For 99-MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8-V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline.