Combinational VLSI Circuits Research Articles

Application of PODEM Algorithm for Fault Detection and Location in FinFet based Combinational VLSI Circuits

FinFet transistors are used in major semiconductor organizations and a significant role is played by it in developing the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, different algorithms such as PODEM (Path Oriented Decision Making algorithms) are used to find the fault detection and location. The Furthermore, more complicated circuits are analyzed for fault detection with different approach. In this research work Combinational Circuits are designed using 20nm/32nm technology nodes in LT Spice environment and PODEM Algorithm is implemented which is developed in MATLAB, to detect and identify fault location and sensitive test vector to detect fault in the circuit and results are presented..

Generating Test Patterns for Multiple Fault Detection in VLSI Circuits using Genetic Algorithm

In this paper we propose a method for the automatic test pattern generation for detecting multiple stuck-at-faults in combinational VLSI circuits using genetic algorithm (GA). Derivation of minimal test sets helps to reduce the post-production cost of testing combinational circuits. The GA proves to be an effective algorithm in finding optimum number of test patterns from the highly complex problem space. The paper describes the GA and results obtained for the ISCAS 1989 benchmark circuits.

Structural synthesis of cell-based VLSI circuitsusing a multi-objectivegenetic algorithm

The authors present the development of a technique which uses a ‘multi objective’ genetic algorithm for the structural synthesis of combinational VLSI circuits by employing one or more cell-based design libraries. Throughout, the genetic evaluation circuits which are optimal with regard to different criteria at various levels within the design hierarchy are sought. The genetic algorithm succeeds in manipulating a highly complex solution space of circuit structures and provides solutions in a relatively small number of generations. The structural cell based GA implemented, the circuit synthesised, and the results obtained, have not been reported in the literature so far.

A new analytical/iterative approach to statistical delay characterization of cmos digital combinational circuits

AbstractThis paper is believed to be one of the first attempts to statistically characterize signal delays of basic CMOS digital building blocks. Analytic expressions in terms of the transistor geometries and technological process variations are provided for fast delay computations, to be used for manufacturing yield optimization, delay variability reduction and general VLSI circuit design for quality. the proposed approach is novel in several ways: (1) It is a combination of an accurate, semi‐empirical MOS transistor model with the use of an efficient interpolation technique to link the non‐physical model parameters to the ‘designable’ and ‘noise’ factors. (2) It uses several newly developed analytical delay formulae where possible and simple iterative solutions where direct analytical solutions do not exist. (3) the resulting hybrid analytical/iterative models are tuned, if necessary, to enhance the overall statistical accuracy. (4) Local delays are combined together for the analysis of complex combinational VLSI circuits. (5) C‐code is generated for specific delay paths to further increase efficiency (improvement in analysis times by two to four orders of magnitude with respect to SPICE, with about 5%‐10% accuracy). Examples of statistical delay characterization are used to illustrate the high accuracy of the proposed approach in modelling the influence of the ‘noise’ parameters on circuit delay relative to direct SPICE‐based Monte Carlo analysis. the important impact of the proposed approach is that statistical evaluation and optimization of delays in much larger VLSI circuits will become possible.

Generating test patterns for VLSI circuits usinga geneticalgorithm

The authors present the development of a technique that uses genetic algorithms, for the generation of test patterns that detect single stuck-at faults in combinational VLSI circuits. As the genetic algorithm evolves, an efficient set of test patterns are produced, by searching the solution space for patterns that detect the highest number of remaining faults in the fault list.

Transitional Delay Fault Test Generation Using AGenetic Algorithm

With the continuous technological advancements in digital electronic circuit technology devices are becoming even more complex, it is essential that a high level of operational reliability is maintained which is why there is always a requirement for new and improved test methodologies. A fault condition in a digital circuit may be the result of a manufacturing problem causing physical imperfection in the device, this imperfection may be open circuit or short circuit connections, or a flaw that changes other characteristics of the device. The propagation of a gate may be affected introducing a delay defect into the circuit, often creating timing problems, which have always proved difficult to detect. This paper presents a new approach to the generation of test patterns that detect gross delay defects in combinational VLSI circuits. In O'Dare and Arslan [1] the authors presented a technique that implemented a genetic algorithm (GA) for the generation of test patterns to detect single stuck-at-faults in combinational VLSI circuits. In order to generate a test for delay faults it is necessary to create a transition in logical state at the fault site within the circuit, the only way to achieve this is by generating pairs of test patterns . The first test pattern initialises the state of all nodes within the circuit, the second test pattern is then used to force the required transition at the designated test node. The problem of test generation for delay faults is considerably more complex than that of test pattern generation for single stuck-at-faults presented in O'Dare and Arslan [1], with an increase in search space size from 2 n to 2 2n for an n input circuit. The problem is further augmented by the necessity of applying the two test patterns in a strict ordered sequence to create the required transition. The authors have therefore developed a new genetic test technique to overcome the problem, using chromosomes-pairs to represent the test patterns. The GAs primary component is a dynamically evolving Global Record Table (GRT), which is used to guide the search towards optimal test pairs in an otherwise complex solution space, producing a compact and efficient set of test pattern-pairs as the GA evolves. The experimental results presented in this paper are compared with other research results for well known combinational benchmark circuits.