Collector-up Heterojunction Bipolar Transistors Research Articles

Alleviation of Thermal Instability via Novel Collector-Up HBTs for Reliable Wireless Applications

We analyzed thermal characteristics of power transistors based on the complementary InGaP/InGaAs/GaAs collector-up heterojunction bipolar transistors (HBTs), and especially for stable wireless applications under extreme operations. A newly developed structure, incorporating the graded InGaAs base and the nonuniform collector, without employing additional thermal-removal design is presented. Significantly, the multi-finger devices achieved compelling high speed and heat dissipation. Results show that the fairly matched high-frequency performance has been exhibited and over 30% improvement in the surface-temperature-rise ratio is achieved. As a consequence of the effective alleviation of unstable feedback phenomena by this novel arrangement, exploiting the advantageous characteristics of complementary collector-up HBTs for thermally reliable high-speed wireless applications is feasible.

Graphene Packaging for Thermal Management of Innovative Complementary Collector-Up Heterojunction Bipolar Transistors

This exploration emphasizes the juxtaposition of thermal stability in InGaP/GaAs p-n-p and n-p-n collector-up (C-up) heterojunction bipolar transistors (HBTs), and specially for the performance-matched complementary wireless applications under extreme operations. High-quality graphene packaging, beneath the graded InGaAs base and the nonuniform collector of C-up HBTs, is proposed. Significantly, the multifinger devices achieved compeling high speed and heat dissipation. The results show that the reasonably matched performance has been exhibited, and a remarkable improvement in the surface temperature rise is attained. Due to the effective alleviation of adverse feedback phenomena by using this innovation, a better thermal stability in the p-n-p device than in the n-p-n device has been evidently observed.

Graphene Heat Spreaders for Thermal Management of InGaP/GaAs Collector-Up HBTs

We present a novel thermal management design for InGaP/GaAs power amplifiers (PAs) by placing the graphene heat spreader (GHS) at the backside of GaAs/InGaAs/InGaP collector-up (C-up) heterojunction bipolar transistors (HBTs), including n-p-n and p-n-p types. The GHS was used to create extra escape channel for thermal spread, and a physics-based analysis was performed to justify heat-dissipation improvements. Temperature distribution in the GHS and the application of these spreaders to ameliorate thermal coupling effects on multifinger transistors were discussed. Compared to the n-p-n device, the p-n-p device exhibits greater thermal stability enhancement results, which are extraordinary and reproducible. Both numerical simulation and experimental measurement were achieved to scrutinize thermal performance of the GHS. This brief demonstrates the potential of the suggested structure in replacing the conventional thermal-removal configuration of GaAs-based HBTs used in high-efficiency cellular handset PAs.

A Comparative Study of InGaP/GaAs Collector-Up HBTs for High-Reliability Small-Scale PA Applications

In this paper, the characteristics of InGaP/GaAs collector-up (C-up) pnp and npn heterojunction bipolar transistors (HBTs) with the graded InGaAs base and the nonuniform doped collector are demonstrated, and the performances as well as the reliability of the novel HBTs have been compared with the conventional InGaP/GaAs HBTs with various collector structures and thermal schemes. Compared to conventional HBTs, the studied C-up HBTs exhibited better current-driving capability, higher RF efficiency, and improved long-term reliability. Note that the pnp device displayed greater thermal stability enhancements, which are distinct and reproducible, than the npn device. The favorable data of the pnp C-up HBT could be attributed to higher electron mobility, resulting in low base resistance and higher emitter resistance improving the thermal stability. The comparison results, based on pragmatic observations from the C-up HBTs without relatively large heat-dissipation configurations, should be very useful for the reliable and the cost-effective design as small-scale power amplifiers in the wideband CDMA system.

Enhanced Thermal Performance of InGaP/GaAs Collector-Up HBTs With a Miniaturized Backside Heat-Dissipation Structure

A miniaturized heat-dissipation structure is developed to reduce the operating temperature of power bipolar transistors to favorable levels, while maintaining a configuration size that is compact enough for high-efficiency operation. By placing the thermal-removal packaging at the backside of the collector-up heterojunction bipolar transistor and through the appropriate finger-pitch arrangement of the packaging design, which displays noticeable enhancement in terms of thermal management, significant reduction in the surface temperature rise is demonstrated on devices composed of the InGaP/GaAs material system. A factor of over 20 shrinkages of the consumed chip area and a 10-fold reduction in mutual heating is observed. At levels of power density up to 1.2 mW/μm2, a power-added efficiency greater than 50% is attained for the wireless cellular power amplifier application.

An efficient heat-spreader design: First demonstration on InGaP/graded InGaAs base/GaAs collector-up HBTs

An efficient heat-spreader design, demonstrated on n-p-n InGaP/graded InGaAs base/GaAs collector-up heterojunction bipolar transistors (HBTs) for the first time, is proposed to achieve high speed and thermal dissipation performances. The collector-up HBT, with a graded InGaAs base, has been successfully fabricated using a three-stage selective-area-regrowth technique. A unity-gain cutoff frequency fT=55GHz and a maximum frequency of oscillation fmax=74GHz were obtained from prototype devices with a large collector area of 3.5×40μm2. Moreover, through proper thinning process, the maximum junction temperature and thermal coupling within the transistors were effectively decreased. It is shown that the thermal management for power amplifiers, based on the developed HBT, used in next-generation cellular phones can be enhanced.

Ameliorated Thermal Performance of n-p-n and p-n-p GaAs/InGaAs/InGaP Collector-Up HBTs

To alleviate mutual heating, both n-p-n and p-n-p GaAs/InGaAs/InGaP collector-up heterojunction bipolar transistors with an effective heat-dissipation configuration (HDC), which can be used in power-amplifier circuits for next-generation wireless communication, have been successfully fabricated for the first time. Significantly different from recently proposed thermal-property-improving collector-up structures and thermal-via-hole designs, the HDC-implemented multifinger devices, with a graded InGaAs base but without the InGaP tunneling collector, are demonstrated to achieve compelling high-speed and heat-removing thermal performance. Preliminary results show that the thermal coupling has been substantially decreased, and nearly 20% amelioration, compared to previous work, in the temperature-rise ratio is obtained. Unprecedentedly, the HDC has a stronger influence on the p-n-p device than on the n-p-n device based on the empirical observations.

Thermal Analysis and Packaging Optimization of Collector-Up HBTs Using an Enhanced Genetic-Algorithm Methodology

In this paper, state-of-the-art collector-up (C-up) heterojunction bipolar transistors (HBTs) with different thermal-via structures (TVS) have been systematically investigated by an enhanced genetic-algorithm (GA) approach. According to recent literature, C-up HBTs are compelling candidates as active components integrated in modern power amplifiers (PAs). To meet the immense demand for miniature PAs in advanced mobile phones, the temperature profiles of multi-finger C-up HBTs with TVS has been described. The thermal coupling between collector fingers as well as various finger pitches and the size effect on the maximum operation temperature within the transistor have been scrutinized. In addition, the thermal management and packaging design of the device has been optimized using a highly efficient GA combined with fuzzy-logic technique. The proposed analysis methodology is demonstrated on the potential InGaP/GaAs C-up HBT. An elucidation of actually-measured, finite-element-calculated, and globally-optimized results has been presented. Evaluated from this effective simulation tool and in comparison with prior works, the remarkable improvements show that the thickness of the TVS can be further reduced by more than 35%, and the thermal resistance of the transistors can be greatly improved over 45%. As a result, it is revealed that the significant thermal performance can be achieved with a highly-compact packaging design, and the thermally stable InGaP/GaAs C-up HBT should be viable for the implementation in the next-generation handset PAs.

Thermal-Stability Enhancement of InGaP/GaAs Collector-Up HBTs

A number of intricate configurations have been proposed to enhance the thermal stability of state-of-the-art power heterojunction bipolar transistors (HBTs). Existing structures for alleviating temperature-interference effects within HBTs are nevertheless not efficient enough to realize miniaturized power amplifiers in next-generation cellular phones. Key thermal parameters, including the temperature-distribution profile, the thermal resistance, the out power, and the power-added efficiency (PAE), of a cost-effective heat-spreading structure have been optimized by the device-physics-based genetic algorithm, and a demonstration on multifinger InGaP/GaAs collector-up HBTs, which exhibit noticeable RF performance, is presented. Comparatively, the significant results, which guarantee the reliability, indicate that the thermal resistance can be substantially decreased by 50%, and a PAE of more than 55% is attained from this novel design.

Improved Packaging Design for Maximizing the Thermal Performance of Multifinger Collector-Up HBTs

Advanced collector-up (C-up) heterojunction bipolar transistors (HBTs) with the thermal-via configuration (TVC) have been analyzed using a genetic algorithm (GA). Novel packaging structures are presented and evaluated in detail. With careful optimization, the thermal performance can be maximized by improving the thermal resistance over 40%, and the conventional TVC can be further reduced by 35%. The proposed approach is demonstrated on the multifinger InGaP/GaAs C-up HBT, which is attractive as the active component in power amplifiers. A comparison of measured, finite-element-calculated, and GA-extracted results has been made. Consequently, it is shown that the remarkable thermal management can be achieved with a miniature heat-dissipation design, and the thermally stable InGaP/GaAs C-up HBT should be feasible for implementation in intelligent wireless communication systems.

Temperature-Dependent Characteristics of a GaN/InGaN/ZnO Heterojunction Bipolar Transistor

This work presents dc characteristics (gain and leakage current) of a GaN/InGaN/ZnO npn collector-up heterojunction bipolar transistor (HBT) measured at 300, 200, and 100 K. The GaN-based epilayers of HBT were grown by metallorganic chemical vapor deposition, and the n-ZnO film was then deposited on top of p-InGaN by sputtering. X-ray diffraction analysis demonstrates that annealing at for 60 s in ambient improved the quality of the ZnO film. Moreover, this study shows that the current gains from the Gummel plot increased as the temperature decreased because the leakage current of the collector current is not a strong function of temperature. However, gains from the measured common-emitter current–voltage characteristics increased slightly as the temperature decreased due to a reduction in the recombination current coupled with lower injection efficiency. These preliminary results show the potential of fabricating GaN/InGaN/ZnO HBTs without dry etching to reach the p-GaN layer, as required in the emitter-up geometry.

Novel Design of Thermal-Via Configurations for Collector-Up HBTs

We devise a finite-element model to analyze the thermal performance of collector-up (C-up) heterojunction bipolar transistors (HBTs) with a thermal-via configuration. A demonstration on the GaInP/GaAs C-up HBT is presented in this Brief, and the novelty of this work is that both 2D and 3D temperature-distribution analyses are performed. The 2D results indicate that the original thermal-via configuration can be reduced by 29%. Furthermore, the results show that the maximum temperature within the collector calculated from 3D analysis is lower than that from the 2D analysis. Based on the 3D analysis, it is revealed that the reported configuration can be reduced by 32%. Therefore, the C-up HBT with a compact thermal-via should be helpful for miniaturization of heat-dissipation packaging configurations within HBT-based high-power amplifiers.

Thermal analysis of multi‐finger GaInP collector‐up heterojunction bipolar transistors with miniature heat‐dissipation packaging structures

AbstractWe build up a finite element modeling (FEM) approach to analyze the thermal performance of collector‐up (C‐up) heterojunction bipolar transistor (HBTs) with a heat‐dissipation via configuration. Highly compact heat‐dissipation packaging structures of GaInP/GaAs C‐up HBTs have been designed and evaluated systematically. In this work, we devise the 2‐D and 3‐D models to simulate the actual devices and to investigate the temperature distribution behavior. Results from 2‐D model indicate that the large heat‐dissipation via configuration can be further reduced by 29% to meet the requirement of HBT‐based small high‐power amplifiers (HPAs) for the cellular phones. Furthermore, the demonstrated results show that the maximum temperature within the collector calculated from 3‐D model is lower than that from 2‐D model. In the 3‐D analysis, it is revealed that the configuration can be reduced by 32%. Therefore, thinning the heat‐dissipation via constructed underneath the GaInP/GaAs C‐up HBT should be helpful for miniaturization of HBT‐based HPAs in future mobile communication systems. Copyright © 2009 John Wiley & Sons, Ltd.

Extraction of the InP/InGaAs metallic collector-up heterojunction bipolar transistor small-signal equivalent circuit

An efficient technique for determining the small-signal equivalent-circuit model of a Metal collector-up Heterojunction Bipolar Transistor (C-up MHBT) is presented. The technique employs analytically derived expressions for direct calculation of HBT T-Model equivalent circuit element values in terms of the measured S-parameters. This approach avoids errors due to uncertainty in fitting to large, over determined equivalent circuits and does not require the use of test structures and extra measurement steps to evaluate parasitics. Physically realistic results are demonstrated under various biasing conditions for the n-p-n InP/InGaAs HBT with metallic collector up structure. The agreement between the measured and model-produced data is excellent over the large frequency range and for several polarizations conditions for devices.

A Hybrid Evolutionary Modeling/Optimization Technique for Collector-Up/Down HBTs in RFIC and OEIC Modules

A hybrid computer-aided design (CAD) tool for automatic simulation and characterization of advanced collector-up/down heterojunction bipolar transistors (HBTs), which are expected to be used as the high-power-amplifier (HPA) module in radio-frequency integrated circuit (RFIC) and the blue laser diode (LD)/heterojunction phototransistor (HPT) module in optoelectronic integrated circuit (OEIC), has been successfully established. By expanding the essence of reported techniques, the newly-developed equivalent-circuit modeling approach focuses on combining the genetic algorithm (GA) with refined analytical-modeling equations yielding reliable initial values of model parameters. This SPICE-like simulator reliably and efficiently relates device/circuit performances directly to the direct current/radio frequency (dc/RF) measurements since it implicitly accounts for physical correlations among model parameters and does not require ad hoc de-embedding test structures as well as special simplifying assumptions in the optimization period. Evolutionary programming is performed to achieve tedious circuit-level simulations in shortest turnaround times and the computational efficiency permits execution of an optimization involving random generation of circuit parameters. In this study, a detailed comparison of direct-measured, analytical-derived, and numerical-simulated results, for the pnp InGaAs as well as npn InGaP collector-up HBTs as the HPA module in RFIC and the npn ZnSe-Ge collector-down HBT as the blue LD/HPT module in OEIC, is presented. To further demonstrate the accuracy and robustness of this approach, the npn AlGaAs-InGaAs collector-down HBT, which can be incorporated in a preamplifier for optical communication, is investigated.

Improved Design of Thermal-Via Structures and Circuit Parameters for Advanced Collector-Up HBTs as Miniature High-Power Amplifiers

An improved methodology, based on the genetic algorithm, is developed to design thermal-via structures and circuit parameters of advanced InGaP and InGaAs collector-up heterojunction bipolar transistors (C-up HBTs), which are promising miniature high-power amplifiers (HPAs) in cellular communication systems. Excellent simulated and measured results demonstrate the usefulness of this technique.

Effects of Rapid Thermal Annealing on Bias-Stress-Induced Base Leakage in InGaP/GaAs Collector-Up Heterojunction Bipolar Transistors Fabricated with B Ion Implantation

The effects of rapid thermal annealing (RTA) on bias-stress-induced base leakage were investigated in InGaP/GaAs collector-up heterojunction bipolar transistors (C-up HBTs) fabricated with boron ion implantation. C-up HBTs annealed at 700°C for 1 s had negligible leakage, while non-annealed C-up HBTs had leakage (with an activation energy, E a , of 0.17 eV) that exponentially increased with bias time. Because this E a is almost the same as that of the hole traps (0.25 eV) observed in the InGaP emitters of non-annealed C-up HBTs, we attribute the leakage to hole tunneling from bases to emitters. By reducing the initial trap density using RTA, we stabilized current gain even after 1,030h of testing at a junction temperature of 210°C and a collector current density of 40 kA/cm 2 .

Efficient optimization of InGaAs and SiGe RF HBTs with a mixed-mode genetic-algorithm technique

An efficient genetic-algorithm-based (GA-based) technique for modeling and analysis of RF heterojunction bipolar transistors (HBTs) has been successfully established. This mixed-mode optimization method focuses on complementing the GA with a set of generalized analytic-modeling equations (GAMEs), requiring no special assumptions, to effectively extract small-signal parameters. Over a wide range of biasing conditions, consistent results between the GA-derived and measured S-parameters on the pnp InGaAs collector-up HBT as well as npn SiGe HBTs, which can be used in small high-power amplifiers for mobile communication systems, clearly demonstrate the superiority of the proposed approach.

Fabrication of sub-transistor via holes for small and efficient power amplifiers using highly selective GaAs∕InGaP wet etching

We investigated the properties of a citric acid-based GaAs∕InGaP selective wet etchant. We found that the citric acid-based etchant has a much higher selectivity and exhibits less undercutting than those of a conventional sulfuric acid-based etchant that we had used. Then, we applied the citric acid-based wet etchant to the fabrication of via holes with high thermal diffusibility underneath heterojunction bipolar transistors. The citric acid-based etchant exhibited GaAs∕InGaP selectivity of about 9800 at pH 9.0 and enabled reliable etch stopping without pinholes. The citric acid-based etchant also suppressed undercutting and enabled the integration of the via holes. We used the optimized citric acid-based wet etching for finishing the via hole etching after rough high-speed wet etching with the conventional sulfuric acid-based etchant. The two-step wet etching process resulted in a successful fabrication of the sub-transistor via hole structure with collector-up heterojunction bipolar transistors.

Characterization and Modeling of Bias-Stressed InGaP/GaAs Collector-Up Tunneling–Collector HBTs Fabricated With Boron–Ion Implantation

To characterize and model the degradation of collector-up (C-up) heterojunction bipolar transistors (HBTs), we bias stress InGaP/GaAs C-up tunneling-collector HBTs (TC-HBTs) fabricated under various conditions for etching the collector mesas and of implanting boron ions into the extrinsic emitter. Contrary to the previous reports on reduction in collector current I/sub C/ of bias-stressed emitter-up HBTs fabricated with ion implantation, no I/sub C/ Gummel shift is observed in the case of C-up TC-HBTs, probably due to the lower damage resulting from the lower ion dosage. On the other hand, the base current of the bias-stressed C-up TC-HBTs increases with the decrease of the ion dose and with the increase of the collector mesa undercut under the collector electrode that is also used as an implant mask. We attribute the increased base current to the increased carrier recombination at the extrinsic base surface. Making the area of the emitter-base junction smaller than that of the base-collector junction-using electron-cyclotron resonance plasma etching together with lateral spreading of heavily implanted boron ions-results in a stable current gain even after a 1030-h testing at a junction temperature of 210/spl deg/C and a collector current density of 40/sup 2/kA/cm.