Collector Doping Levels Research Articles

Influence of the Selectively Implanted Collector Integration on +400 GHz fMAX Si/SiGe:C HBTs

Optimization of SiGe HBT performances towards very high cut-off frequencies fT and fMAX requires high collector doping level together with low collector/base junction capacitance CBC. This compromise is usually achieved by localizing a dedicated collector implant (so-called SIC implant) under the intrinsic emitter/base region of the device. In this paper, we present the influence of the integration choice of the Selectively Implanted Collector (SIC) on the performance of +400 GHz fMAX Si/SiGe:C HBTs featuring a selective epitaxy of the base [1]. We describe in the first part of this paper the different process flows investigated for the SIC integration. Second part is dedicated to the analysis of the electrical results obtained for the different SIC modules and to the understanding of these results. We conclude on the perspectives to further improve hf performances.

Preliminary results of storage accelerated aging test on InP/InGaAs DHBT

We report on the reliability of InP HBT technology which has applications in very high-speed ICs. This work presents the storage accelerated aging tests results performed on InP/InGaAs HBT at stress temperatures of 180, 210 and 240 °C up to 3000 h. We have performed aging tests for two generations of InP HBT which differ from the collector doping level and from material used for planarization. From the Gummel plots, we note that the major degradation mechanism is located at the base–emitter junction periphery. Investigations on the physical origin of the observed failure mechanism has been performed using TCAD simulations.

A compact model for SiGe HBT on thin-film SOI

Heterojunction bipolar transistor (HBT) fabrication on thin-film silicon-on-insulator (SOI) has been recently demonstrated. Due to the space volume constraint (thin film) for the device fabrication, the HBT structure is different from bulk HBT. In fact, compared to a bulk device, the buried layer has been suppressed and a lateral collector contact configuration is introduced. This device features a vertical expansion followed by a lateral expansion of the base-collector space charge region. This nonconventional charge behavior induces a kink in the base-collector junction capacitance characteristics, and as a consequence a modified Early effect. Furthermore, the low current transit time is modified compared to a bulk HBT. In this paper, all these effects are analyzed and a compact model for SOI-HBT is proposed. The model is validated on real SOI-HBTs with different collector doping levels.

A 1.8-GHz high-efficiency 34-dBm silicon bipolar power amplifier

The low-voltage power capabilities of a low-cost high-performance silicon bipolar process were investigated. By optimizing the emitter finger layout, epilayer thickness, and collector doping level, efficiency values up to 83% were achieved by on-wafer load-pull measurements on a single-cell test device operating at 1.8 GHz and 2.7-V power supply. The detrimental effect of the emitter distributed resistance on the current capability of long-emitter bipolar transistors was also considered.. An analytical model for a proper device design was derived and experimentally validated. Using the optimized unit power device, a 1.8-GHz 2.7-V three-stage monolithic power amplifier was implemented, which provides a 57% power-added efficiency and a 33-dB gain while delivering a 34-dBm output power to the load.

Simulation and design of SiGe HBTs for power amplification at 10 GHz

Device modeling using a commercial numerical simulator has been employed for design of SiGe heterojunction bipolar transistors for high frequency, high power applications. In this study, the effects of the design of the epitaxial layer structure on power gain at X-band (10 GHz) were investigated. In particular, the base doping and width, the germanium concentration, profile and width, and the emitter and collector doping levels were investigated. Device layout issues such as emitter finger width and spacing and transistor self-heating effects were not considered. A Gaussian profile was assumed for the base doping based on a SIMS profile and the known boron out-diffusion during epitaxy. Device simulations were found to show that displacement of the collector p–n junction from its corresponding SiGe/Si heterojunction, such as arising from boron out-diffusion from the base, was found to contribute to the formation of a parasitic barrier in the conduction energy band that produced a degradation in power gain and device performance. A similar, but smaller parasitic barrier was also found to form at the emitter–base junction as a result of p–n junction displacement. The device performance was also investigated as a function of the displacement of the peak base doping from the center of the SiGe base. The simulation results show that the device can achieve significant power gain at X-band frequencies, but that the device performance achieved in practice is likely to be a sensitive function of the exact boron doping profile in the base and the extent, if any, of the displacement of the emitter and collector p–n junctions from the SiGe/Si heterojunctions at the ends of the base.

Noise parameter optimization of UHV/CVD SiGe HBT's for RF and microwave applications

This paper demonstrates a predictive noise parameter estimation methodology for UHV/CVD SiGe HBT's which combines ac measurement, calibrated ac simulation and two of the latest Y-parameter-based noise models: (1) the thermodynamic noise model, and (2) the SPICE noise model. The bias current and frequency dependence of the minimum noise figure, the optimum generator admittance, and the noise resistance are calculated using both models and compared with measurements. The observed agreements and discrepancies are investigated using circuit analysis of the chain noisy two-port representation. For the devices under study, the SPICE model description of thermal noise produces a better overall agreement to data in terms of all the noise parameters. Experiments on devices with different collector doping levels show that both low noise and high breakdown voltage can be realized with one profile without significantly compromising the ac current gain and the ac power gain.

SiGe power HBT's for low-voltage, high-performance RF applications

Silicon-Germanium (SiGe) power heterojunction bipolar transistors (HBT's) are fabricated by using two or ten device unit cells with an emitter area of 5/spl times/0.5/spl times/16.5 /spl mu/m/sup 2/ each. The large power transistor features 1 W RF output power at 3-dB gain compression, 3.5 V bias, and 2.4 GHz with a maximum power-added-efficiency (PAE) of 48% for class A/B operation. At a supply voltage of 1.5 V, the transistor delivers a 3-dB RF output power of 150 mW with a PAE of 47%. It is shown that a high collector doping level is advantageous for low-voltage operation. Further, by using special bias sense ports, the interconnect losses are found to degrade the device performance to a considerable degree.

Importance of collector doping in the design of AlInAs/GaInAs/InP double heterojunction bipolar transistors

AlInAs/GaInAs/InP double heterojunction bipolar transistors (DHBTs) have been made with an InP collector thickness of 0.75 μm and collector dopings of 1.4, 2.4, and 3×1016 cm−3. It is shown that because of the conduction band potential barrier between the GaInAs base and the InP collector in DHBTs and particular velocity-field characteristics of InP, the dc and rf performance of the DHBT is very sensitive to the collector doping level. With a collector doping of 3×1016 cm−3 devices conducted a collector current density of 1×105 A/cm2 without gain compression and had a IC-VCE saturation voltage of about 2 V. Base-collector and collector-emitter breakdown voltages were 22 and 14.5 V, respectively, and fT and fmax were in the range of 65–70 GHz.

An AlSb–InAs–AlSb double-heterojunction P-n-P bipolar transistor

We report the experimental demonstration of AlSb–InAs P-n-P double-heterojunction bipolar transistors. The devices exhibited net current gain and supported a substantial collector voltage of VCE≳2.5 V. The device structure was grown by molecular-beam epitaxy on a (001)-oriented p+ GaAs substrate. The base thickness was 100 nm, with a degenerate n-type base doping level (Si) of 2×1018 cm−3. The p-type emitter and collector doping levels (Be) were 5×1016 cm−3. The collector currents obeyed a typical Gummel relation, with parameters close to those expected from theory, making allowance for the high degree of degeneracy and the nonparabolicity in the InAs base region. However, the base currents were still high, apparently due to extensive interface recombination via unknown defects at the InAs–AlSb emitter-base junction. The base currents could be described well by a Sah–Noyce–Shockley model, modified to account for the unusual abrupt staggered lineup heterojunction and the degeneracy on the InAs side.

Estimate of peak voltage for triggering current mode second breakdown of BJTs during inductive turnoff

Abstract Calculation of the peak voltage which triggers avalanche injection in an n+pnn+ bipolar transistor with an inductive load has been carried out. An approach has been taken where the effects of both the ionization rates and the space-charge current density on carrier generation are included in evaluation of the peak voltage. Calculated peak voltage is found to be dependent on epitaxial layer thickness and on collector doping level. The analytical results are in excellent agreement with experimental data.

Emitter-collector breakdown voltage BV ceo versus gain h FE for various n-p-n collector doping levels

The communication presents a set of design curves of collector-emitter breakdown voltage BVceo versus gain hFE for various collector doping levels and thickness for n-p-n transistors. The results include epitaxial layer punch through and radial c-b junction breakdown.