Collector Current Research Articles

A 5.43 nV/√Hz Chopper Operational Amplifier Using Lateral PNP Input Stage with BJT Current Mirror Base Current Cancellation

This paper presents a low-noise chopper operational amplifier using a lateral PNP input stage with bipolar junction transistor (BJT) current mirror base current cancellation. The BJT has a lower noise characteristic than the metal–oxide–semiconductor (MOS) transistor, where low-noise characteristics can be achieved by implanting the BJT to the input stage of the amplifier; however, the base current of the BJT input stage causes low input impedance of the amplifier. The BJT current mirror base current cancellation technique is implemented to enhance the input impedance of the BJT input stage by canceling the base current. BJT current mirror base current cancellation is implemented with a simple scheme using NPN transistors with deep n-well in a generic complementary metal–oxide–semiconductor (CMOS) process. For further noise reduction with the BJT input stage, a chopper amplifier scheme is adopted to reduce low-frequency components such as 1/f noise terms in the low-frequency range. The prototype chip is fabricated in a 0.18-μm CMOS process. The active area of the prototype amplifier is 0.213 mm2. The measured input-referred noise is 5.43 nV/√Hz. The measured input base current of the amplifier with base current cancellation is 67.971 nA. The total amplifier current consumption is 278.3 μA, with a power supply of 3.3 V.

On the Mechanisms of Linearity Peak Modeling in Common-Emitter SiGe HBTs Using Mextram 505

An important aspect of compact modeling for RF application is to accurately model the biasing current at which transistor linearity is maximized, i.e. where the third order intercept point, IP3, peaks. We have shown recently that for common-emitter SiGe HBTs, Mextram 504.12 has problem modeling the IP3 peak behavior at high injection [1]. We have further developed a couple of new modeling options in Mextram 505 [2] for CB junction depletion capacitance intended to improve IP3 peak modeling [1]. However, the detailed mechanisms of how these improved CB junction depletion capacitance models translate into IP3 peak modeling improvement remains unclear and require further investigation.For instance, the collector current, which is the output current, consists of the transistor main current In that flows from the collector to the emitter, and the CB junction capacitance discharging current that flows from the collector to the base. With the change of CB junction depletion capacitance model, which distortion current is dominant, In or the CB discharging current, in determining IP3 peak? Through detailed analysis of the harmonic components of the individual branch currents at the collector node of the Mextram large signal equivalent circuit, we find that the In distortion current dominates in determining IP3 peak behavior.The next logic question is if the In distortion current improvement with the Mextram 505 CB depletion capacitance models is directly due to the normalized base hole charge term, q1I in Mextram terminology, that goes directly into the In expression, or indirectly due to propagation of the CB discharging current induced distortion to IN, through circuit interactions. We will show that it is the later rather than the former with carefully designed custom Verilog-A codes of Mextram, by using separate CB depletion capacitance models in the main current equation formulation and the CB depletion charge equations. Changing the CB depletion capacitance model used in the main current equation leads to no visible changes in IP3, while changing the CB depletion capacitance model used in the CB depletion charge equation leads to obvious changes in third order output current and hence IP3. This proves that the observed third order distortion current improvement in In responsible for the improved IP3 peak modeling in Mextram 505 fundamentally results from the CB depletion charge term, despite the small values of third order distortion in the CB depletion charge current itself.We will then further examine how reducing the CB junction depletion capacitance might affect IP3 and how the partition between extrinsic and intrinsic CB junction capacitance affects IP3 peak behavior. Interestingly, simply making all CB depletion capacitance extrinsic gets rid of the IP3 peak modeling problem in Mextram 504, implying that the high injection related increase of the intrinsic CB junction depletion charge control voltage Vjunc and its related smooth limiting parameter Vch are the root problems. A reduction of CB depletion capacitance, intrinsic or extrinsic, is found to be beneficial for IP3 peak improvement.[1] G. Niu, H. Zhang, Y. Li, X. Ding, M. Willemsen, and A. Scholten, “Physics and Compact Modeling of SiGe HBT Linearity Using Mextram,” ECS Transactions, 86 (7), pp. 145-154, 2018.[2] G. Niu, R. van der Toorn, J. C. J. Paasschens, W. J. Kloosterman, The Mextram Bipolar Transistor Model, 505.10, Model Definition Document, Auburn University, 2019.

Origin of Irradiation Synergistic Effects in Silicon Bipolar Transistors

The practical damage of silicon bipolar devices subjected to mixed ionization and displacement irradiations is usually evaluated by the sum of separated ionization and displacement damages. However, recent experiments show clear difference between the practical and summed damages, indicating significant irradiation synergistic effects (ISEs). Understanding the behaviors and mechanisms of ISEs is essential to predict the practical damages. In this work, we first make a brief review on the state of the art, critically emphasizing on the difficulty encountered in previous models to understand the dose rate dependence of the ISEs. We then introduce in detail our models explaining this basic phenomenon, which can be described as follows. Firstly, we show our experimental works on PNP and NPN transistors. A variable neutron fluence and $\gamma$-ray dose setup is adopted. Fluence-dependent `tick'-like and sublinear dose profiles are observed for PNP and NPN transistors, respectively. Secondly, we describe our theoretical investigations on the positive ISE in NPN transistors. We propose an atomistic model of transformation and annihilation of $\rm V_2$ displacement defects in p-type silicon under ionization irradiation, which is totally different from the traditional picture of Coulomb interaction of oxide trapped charges in silica on charge carriers in irradiated silicon. The predicted novel dose and fluence dependences are fully verified by the experimental data. Thirdly, the mechanism of the observed negative ISE in PNP transistors is investigated in a similar way as in the NPN transistor case. The difference is that in n-type silicon, VO displacement defects also undergo an ionization-induced transformation and annihilation process. Our results show that, the evolution of displacement defects due to carrier-enhanced defect diffusion and reaction is the dominating mechanism of the ISEs.

Measurement of RF Linear Operating Area of Bipolar Transistors

The methodology for the measurement of the knee voltage and maximum collector current for the linear operation of bipolar transistors is described and demonstrated on the horizontal current bipolar transistor (HCBT). Both limits are determined by measuring loadlines at 1-dB compression point (P1dB), wherein the hard-limiting nonlinearity occurs only in the positive half-wave of the collector current. The boundary defines the knee voltage, maximum collector current, and the transition between the two in which the onset of the Kirk effect takes place. It is found that the maximum collector current boundary saturates at a constant value for higher collector-emitter voltages and that there are the optimum load impedance and bias point for the maximum output power in the linear regime. They are found for HCBT, which achieves the output power of 21.25 dBm (P1dB) at 2.4 GHz, with the maximum collector-emitter voltage set to the open-emitter breakdown voltage of 9 V.

Compact Thermal Sensors for Dense CPU Thermal Monitoring and Regulation: A Review

Nearly all integrated circuits contain power and thermal management circuits. These two functions are intimately connected and help improve the power performance of the system. In recent generation computers, the functionality and complexity of the thermal sensing and management circuits have accelerated in order to improve the performance. Integrated thermal sensors are utilized to monitor the peak temperatures of the CPU's to ensure that they do not exceed the reliability limits. There are many hot-spots on the CPU which have to be monitored, and these locations are not necessarily obvious during the design stage. As a result, it is required that there be multiple sensors on the CPU to enable accurate coverage. Thermal sensors are needed for cold-spot monitoring as well, in order to determine the required V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> level during low voltage, low power modes. The sensors are also used for fan regulation and power estimation. There can be many tens of sensors in a product, which require them to be small and low power. A variety of mechanisms have been utilized to form the sensing element. These include the parasitic PNP transistor, MOS transistors, resistors, as well as the thermal diffusivity of Si. In the past ten years, a trend towards miniaturization of thermal sensors has occurred. This review paper surveys the recent miniaturized integrated sensors which have been reported in the literature. The design tradeoffs for the CPU application are discussed, as well as the relative advantages of the different sensing mechanisms and their performances.

A snapback-free and high-speed SOI LIGBT with double trenches and embedded fully NPN structure

A novel 600 V snapback-free high-speed silicon-on-insulator lateral insulated gate bipolar transistor is proposed and investigated by simulation. The proposed device features an embedded NPN structure at the anode side, and double trenches together with an N-type carrier storage (N-CS) layer at the cathode side, named DT-NPN LIGBT. The NPN structure not only acts as an electron barrier to eliminate the snapback effect in the on-state within a smaller cell pitch but also provides an extra electron extracting path during the turn-off stage to decrease the turnoff loss (Eoff). The double cathode trenches and N-CS layer hinder the hole from being extracted by the cathode quickly. They then enhance carrier storing effect and lead to a reduced on-state voltage drop (Von). The latch-up immunity is improved by the double cathode trenches. Hence, the DT-NPN LIGBT obtains a superior tradeoff between the Von and Eoff. Additionally, the DT-NPN LIGBT exhibits an improved blocking capability and weak dependence of breakdown voltage (BV) on the P+ anode doping concentration because the NPN structure suppresses triggering the PNP transistor. The proposed LIGBT reduces the Eoff by 55% at the same Von, and improves the BV by 7.3% compared to the conventional LIGBT.

Cost-effective and compact analog compensation method of thermal drift of implantable piezoresistive blood pressure sensors

Implantable pressure sensors are important tools of preclinical research activity in laboratories. Unfortunately, their use is limited by cost, autonomy and temperature-related drifts. Cost and ease of use depend on several parameters, in particular battery life and miniaturization required to be able to implant animals and monitor them over time that is long enough to be physiologically relevant. While thermal drifts inherent in implantable sensors due to animals’ body temperature variation vary depending on their operating principe. Reduction of thermal drift and energy consumption and overall miniaturization. The blood pressure sensor studied is based on a Honeywell NPB030 piezoresistive probe chosen due to its low cost and compactness. We look for reducing its thermal drifts over temperature range [34 °C–39 °C] and pressure range [0 - 300 mmHg]. With a classical conditioning circuit, the sensor's overall relative drift is 3,2%/°C (13.4 mV/°C/420 mV), resulting from two contributions, one of 2.7%/°C (0.1 mV/°C/3.6 mV) due to the piezoresistive probe alone, another of 0.1% (0.98 mV/°C/916 mV) due to the conditioning circuit alone. An NPN transistor is added in series with the Wheaston Bridge formed by the piezoresistors of the pressure probe to correct the thermal drift. Thanks to optimization of bias resistors of the transistor using Cadence/Pspice, the measured overall thermal drift of the compensated sensor is reduced to 0.09%/°C (0.371 mV/°C/405 mV), in very good agreement with simulation. It's worth noting that the optimization is made possible due to our original method to determine the value of each piezoresistor in the Wheaston Bridge. Our approach proves effective to reduce thermal drift of the studied pressure sensor. Additional space required, cost and consumption will be very low. This method should be assessed and validated with CMS components.

Temperature dependence of bipolar junction transistor current-voltage characteristics after low dose rate irradiation

Temperature variation on board can have a significant impact on electronic circuit parameters. In this paper, we investigate and model how both irradiated NPN and PNP-Bipolar Junction Transistors (BJTs) at room temperature respond electrically to temperature variation. A temperature-dependent analytical model for total-ionizing-dose-induced excess base current in BJTs is proposed. Our model captures base current dependence on temperature on irradiated parts. To do so, the devices under test are irradiated at room temperature with all terminals grounded. After irradiation, base currents are obtained, and the concentrations of oxide defects (i.e., oxide trapped charge and interface traps) created during irradiation are calculated. At the end, results from our analytical model and experimental data are compared to SPICE simulations. Both base current and defect densities resulting from room temperature irradiations are used as inputs to SPICE simulations and the analytical model. Experimental data obtained from measurements at both low and high temperatures on parts irradiated at room temperature are shown to compare well to the simulation results and analytical model over a range of temperatures. The modeling work shows that SPICE simulations can support qualification for commercial-off-the-shelf (COTS) linear bipolar components with temperature for space applications.

On the Mechanisms of Linearity Peak Modeling in Common-Emitter SiGe HBTs Using Mextram 505

This paper presents detailed mechanisms of how improved intrinsic collector-base junction depletion capacitance (Ctc ) model in Mextram 505 improves OIP3 peak modeling in common-emitter SiGe HBTs. Harmonics of individual branch currents are examined using custom Verilog-A codes. Interestingly, the third order Ctc charging current is found to be much lower than the third order main current (IN ), which dominatesthe third order collector current. Early effect is further excluded as the reason for improved third order current modeling. Circuit level propagation of nonlinear Ctc current towards IN is concluded to be the main mechanism by which IP3 peak behavior is improved in Mextram 505.

A System for Controlling the Thermal Behavior of Voltage Source Inverters

The thermal behavior of semiconductor devices of voltage source inverters for a traction frequency converter and its control systems are investigated. A test bed for studying thermal processes in steady state and transient modes occurring in semiconductor modules with air forced cooling systems is described. The results of an experimental investigation for the Infineon FF300R06KE3 module are analyzed and compared to the results of a mathematical model. Transfer functions of a semiconductor module as an object of temperature control are synthesized with respect to the collector current, cooling air flow, and frequency switching. The control system of thermal behavior of a voltage source inverter with two control actions on the object of temperature control (cooling air flow and frequency switching) is developed. It is proposed to use an electric drive with an induction motor and scalar control system for the purposes of regulating the cooling air flow. The effectiveness of the proposed control system is confirmed by means of simulation in MATLAB/Simulink in transient and steady-state modes.

Gamma-Induced Degradation Effect of InP HBTs Studied by Keysight Model

The gamma irradiation effect in indium phosphide (InP) heterojunction bipolar transistors (HBTs) is studied in this paper. The direct-current (DC) and alternating-current (AC) characteristics are investigated before and after an irradiation dose of 10 Mrad(Si). The main effects of gamma irradiation for InP HBTs are the following: increase of forward Gummel base current at low bias regime, decrease of common emitter collector current, increase of junction capacitances, and decrease of cutoff frequency. The Keysight model is adopted to describe behaviors of InP HBTs including DC and AC behaviors. The Keysight model parameter values are extracted before and after irradiation, in turn to study the physical mechanisms responsible for irradiation-induced degradation in InP HBTs.

Research on the Multiphysics Field-Circuit Coupling Model of Press Pack IGBT Considering the Application of Hybrid HVDC Breakers

Press pack insulated gate bipolar transistor (PP IGBT) is suitable for the hybrid high voltage direct current (HVdc) breaker to clear the fault current of the flexible HVdc transmission system with its advantages of double-side cooling, short-circuit failure mode, and easy to connect in series. However, it should have the ability to transmit the fault current, which is up to five or six times of its rated current, within several milliseconds depending on the distances between two stations without external cooling system. The junction temperature of PP IGBT will increase sharply and it is not possible to be measured during that situation. Therefore, the accurate prediction of junction temperature is extremely important for the packaging design of PP IGBT according to its working condition. In this article, an electro-thermo-mechanical multiphysics field-circuit coupling model of PP IGBT, which is coupled with the electrical, thermal, and mechanical fields, is proposed to predict the collector current, clamping force, and junction temperature. The 3-D mechanical model is decoupled with the 1-D electro-thermal Cauer network model to simplify this multiphysics model without reducing its accuracy. Both the normal and worst working conditions are analyzed through this multiphysics field-circuit model.

UWE-4: First Electric Propulsion on a 1U CubeSat—In-Orbit Experiments and Characterization

The electric propulsion system NanoFEEP was integrated and tested in orbit on the UWE-4 satellite, which marks the first successful demonstration of an electric propulsion system on board a 1U CubeSat. In-orbit characterization measurements of the heating process of the propellant and the power consumption of the propulsion system at different thrust levels are presented. Furthermore, an analysis of the thrust vector direction based on its effect on the attitude of the spacecraft is described. The employed heater liquefies the propellant for a duration of 30 min per orbit and consumes 103 ± 4 mW. During this time, the respective thruster can be activated. The propulsion system including one thruster head, its corresponding heater, the neutralizer and the digital components of the power processing unit consume 8.5 ± 0.1 mW · μ A−1 + 184 ± 8.5 mW and scales with the emitter current. The estimated thrust directions of two thruster heads are at angles of 15.7 ± 7.6∘ and 13.2 ± 5.5∘ relative to their mounting direction in the CubeSat structure. In light of the very limited power on a 1U CubeSat, the NanoFEEP propulsion system renders a very viable option. The heater of subsequent NanoFEEP thrusters was already improved, such that the system can be activated during the whole orbit period.

TRANZYSTOROWY UKŁAD DO POMIARU TEMPERATURY

W artykule zostały przedstawione schematy miernika temperatury opartego na strukturach tranzystorowych. Została przeanalizowana zależność prądu kolektora od temperatury bez i przy zastosowaniu linearyzacji funkcji przetwarzania. Zaproponowano metodę linearyzacji opartą na formowaniu prądu kompensacyjnego, która pozwoliła zmniejszyć błąd pomiaru temperatury do ± 0,006°C w zakresach temperatury 40… 60°C i 60… 80°C oraz do ±0,08°C w zakresie 10… 90°C.

A Self-Adaptive Measurement System for IGBT Collector Current Using Package Parasitics

Insulated gate bipolar transistor (IGBT) collector current measurement based on the package parasitics between the power emitter (E) and the Kelvin emitter (E') is a lossless and real-time monitoring method. A step to improve accuracy is to precisely match the time constant (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> × C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> ) of the measurement circuit against the package parasitics (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EE'</sub> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EE'</sub> ). This article proposes an automated time constant matching method to realize the tuning of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> × C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> to L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EE'</sub> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">EE'</sub> , and a detection circuit to continuously measure the IGBT collector current using the package parasitics. In the proposed method, the Miller plateau voltage is first sampled, and a polynomial curve fit is carried out to determine the fitting parameters associated with the IGBT collector current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> ). A programmable resistor R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> is then adjusted automatically based on the step response of the readout voltage until the time constant is matched. A ratio between the readout voltage and a known I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> is then calculated based on the Miller plateau voltage. The proposed system is verified using a field-programmable gate array controller and discrete components. Experimental results confirmed the functionality of the proposed method, showing that the readout voltage versus I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> relationship has good agreement in the range of 0-165 A, with less than 3% error. The proposed method can also be used for overcurrent protection with a detection time of less than 0.7 μs.

Defect Dynamic Model of the Synergistic Effect in Neutron- and γ-Ray-Irradiated Silicon NPN Transistors.

A defect dynamic model is proposed for the positive synergistic effect of neutron- and γ-ray-irradiated silicon NPN transistors. The model considers a γ-ray-induced transformation and annihilation of the neutron-induced divacancy defects in the p-type base region of the transistor. The derived model of the base current predicts a growth function of the γ-ray dose that approaches exponentially an asymptotic value, which depends linearly on the neutron-induced initial displacement damage (DD) and a linear decay function of the dose whose slope depends quadratically on the initial DD. Variable fluence and dose neutron-γ-ray irradiation experiments are carried out, and we find all of the novel dose and fluence dependence predicted by the proposed model are confirmed by the measured data. Our work, hence, identifies that the defect evolution under γ-ray irradiation, rather than the widely believed interface Coulomb interaction, is the dominating mechanism of the synergistic effect. Our work also paves the way for the modification of displacement defects in silicon by γ-ray irradiation.

A PNP-triggered dynamic substrate GGNMOS with improved performances

A novel PNP-triggered dynamic substrate GGNMOS (gate-grounded NMOS) structure is proposed and verified in 0.18 μm salicided CMOS process. Owing to the dynamic substrate technique and imbedded PNP transistor which injects triggering current to the substrate under ESD (electrostatic discharge) events, the proposed structure features a small trigger voltage, a small snapback region, a high robustness, and a larger margin of ESD design window is achieved. Compared with traditional dynamic substrate GGNMOS, the proposed structure promotes FOM (figure of merit) by 60%. So it is a more feasible solution in ESD protections applications of low-voltage and thin gate oxide process for its overall improved performances.

Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO

A push-pull oscillator topology that uses only one type of active device is proposed in this article. A magnetic transformer is leveraged to set positive feedback around a common-collector differential npn transistor pair, implementing the push-pull operation. This results in half the bias current for a given amplitude of oscillation, compared to more standard oscillator topologies. A thorough phase noise analysis of the circuit is carried out, emphasizing the crucial role of the magnetic transformer in the circuit operation and noise optimization. Proof-of-concept prototypes implemented in a 130-nm SiGe BiCMOS technology operate at 17 GHz and show a phase noise as low as −116 dBc/Hz at 1-MHz offset, while drawing 13.7 mA from the 3.3-V supply. The tuning range is 15%. While the circuit is demonstrated in SiGe BiCMOS technology, it lends itself equally well to implementations in other technologies where only one fast device is available, such as SiGe HBT, InP HBT, and GaN HEMT.

A 210–291-GHz (8×) Frequency Multiplier Chain With Low Power Consumption in 0.13-μm SiGe

This letter presents a 210–291-GHz $8\times $ multiplier chain in the 0.13- $\mu \text{m}$ SiGe Bipolar CMOS (BiCMOS) technology for the broadband generation of carrier signals, imaging, and spectroscopy. It consists of three cascaded Gilbert-cell doublers with compact input matching networks to generate quadrature collector currents in the switching quad for broadband flat conversion gain. The multiplier chain generates a saturated output power of −7.7 dBm at 244.5 GHz with a 3-dB bandwidth of 81 GHz. It consumes 0.24 W of dc power and occupies 0.86 mm 2 of chip area.

An ultra low power CMOS based temperature to digital converter in 0.045 µm technology

This research propose a VLSI based temperature to digital converter (TDC) which is implemented with the aid of CMOS technology whose precise functionality is to sense the temperature-dependent source-gate voltage (VSG) of PMOS Transistor. It measures an inaccuracy of ±40 mK on 20 samples from one batch ranging between −60 °C to +60 °C temperature. This result is mainly due to the generation of pmos transistors drain currents which minimizes the spread in their gate to source voltages in addition to a PTAT digital circuit in support of the proper stretch in the pmos transistors emitter currents. The entire design has been implemented in 0.045 µm technology and draws a current of 0.3 µA which shows that the proposed TDC can be considered as ultra-low power device as the power consumed by it is 18.09E-12 W between the room temperatures of −60 °C to +60 °C. As per the accuracy of the proposed TDC the calibration cost can be reduced which would avoid the difficulty in the batch calibration. The supply voltage given to the device is 0.45 volts and a temperature inaccuracy of ±18 mk is achieved.