Coarse ADC Research Articles

A 1.5MSPS, 120 dB SFDR, ±10 V input range SAR ADC with sampling nonlinearity compensation and inherent 2-b coarse ADC for MSBs decision

This paper presents a high-precision, successive-approximation-register (SAR) analog-to-digital converter (ADC) with maximum input range of ±10 V for industry applications, where the wide-range input signal is sampled directly on part of the capacitive digital-to-analog converter (CDAC) via high-voltage (HV) sampling switches. An inherent 2-b coarse ADC is designed to avoid charge leakage under large input signal, which is reused for nonlinearity compensation from the sampling switch's resistance, while the nonlinearity due to clock feedthrough is compensated by a binary capacitor array. A capacitance reduction structure is used in the CDAC with redundant bits to save the CDAC's area. Fabricated in a 180-nm CMOS process with HV option, the ADC achieves 102-dB SNDR and 120-dB SFDR under 1.5 MSPS throughput. The overall power consumption without BGR and reference buffer is 34.4 mW under ±11-V bipolar HV supplies for sampling network and 1.8-V supply for the core circuits, corresponding to a FoMs of 175.4 dB, respectively. The entire chip occupies 7.2-mm2 area.

A 0.4-to-0.8 V 0.1-to-5 MS/s 10 b two-step SAR ADC with TDC-based fine quantizer in 40-nm CMOS

This paper presents an energy efficient two-step hybrid-domain successive approximation register (SAR) analog-to-digital converter (ADC). Comparator offset calibration and kickback noise reduction techniques are proposed to maintain the high dynamic range and elevated residual signal quality of the coarse ADC. A feedback adjustment technology is proposed to reduce energy consumption of voltage-to-time converter (VTC). The VTC offset and LSB gain error between the coarse ADC and fine time-to-digital converter (TDC) are calibrated to ensure the gain accuracy. The proposed SAR ADC is designed in a 40-nm CMOS process and occupies 0.0363 mm2 silicon area. The post-simulation results show the proposed ADC achieved a spurious-free dynamic range (SFDR) of 74.8 dB and a signal-to-noise and distortion ratio (SNDR) of 56.42 dB at 0.4 V supply voltage and Nyquist input rate. The operating frequency scales from 100 kS/s to 5 MS/s. The converter has a power supply range of 0.4–0.8 V, and the figure of merit (FOM) is 4.85–10.6 fJ/conversion step.

A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique

A 7-bit 3 GS/s two-channel time-interleaved two-step flash analog-to-digital converter (ADC) with 7-GHz effective resolution bandwidth (ERBW) is presented. A reference-embedding flash ADC for a fine stage having only a single capacitive digital-to-analog converter improves the power efficiency and area efficiency as well as the input bandwidth. The proposed sample-and-hold sharing structure not only improves the input bandwidth by removing the effect of the input capacitance of the fine ADC (FADC) but also eliminates the gain error between the coarse ADC and the FADC. The advanced sequential slope-matching offset calibration technique in the eight-time interpolated FADC improves the gain of the voltage-to-time converter and the interpolation linearity. A prototype ADC implemented in a 40-nm CMOS process occupies 0.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including offset calibration circuitry. The measured peak differential non-linearity (DNL) and integral non-linearity (INL) after calibration are 0.53 and 0.47 LSB, respectively. With a 1.49-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.94 and 55.78 dB, respectively. The ERBW without and with time skew calibration is 4.8 and 7 GHz, respectively. The power consumption is 6.8 mW under a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 28 fJ/conversion-step at 3 GS/s.

A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration

This article presents a relative-prime-based time-interleaved (RP TI) sub-ranging successive-approximation register (SAR) analog-to-digital converter (ADC) with on-chip background skew calibration. The proposed calibration aligns the sampling time of every fine ADC (F-ADC) to that of a particular coarse ADC (C-ADC) that works as a reference ADC. To avoid the unwanted calibration tone from the reference ADC, the C-ADC is also time-interleaved to make all samples undergo the same kick back. By setting the numbers of the time-interleaved channels of the C-ADCs and F-ADCs in a relative-prime relationship, every C-ADC can be evenly shared by every F-ADC; thus, the timing skews between the interleaved sub-ADCs are calibrated by adjusting the sampling edges of every F-ADC to the particular C-ADC working as a reference ADC. An 18-channel TI 10-bit 2.2-GS/s SAR ADC was implemented as a prototype with 28-nm CMOS. Owing to the proposed on-chip background skew calibration, the peak tone by skew was reduced by 23 dB from -40 to -63 dB, which corresponds to the residual skew reduction from 1.6 ps to 113 fs near the Nyquist input. Thus, the prototype ADC achieved a spurious free dynamic range (SFDR) over 52.8 dB and a signal-to-noise-and-distortion ratio (SNDR) over 44.9 dB with 18.2-mW power consumption, which leads to a Walden figure-of-merit (FoM) of 57.8 fJ/conversion-step.

A 3 mW 6-bit 4 GS/s Subranging ADC With Subrange-Dependent Embedded References

A subranging analog-to-digital converter (ADC) with reference-embedded comparators (RECs) is proposed. By adjusting the bias current and/or body voltage of the REC's input differential pair, the REC offset can be adjusted to a specific voltage equal to a reference voltage referred to henceforth as the embedded reference. For the ADC's coarse stage, RECs with wide-range embedded references are implemented by adjusting the bias currents using current source arrays to cover the full-scale input. By contrast, for the ADC's fine stage, RECs with narrow-range embedded references are implemented by adjusting the body voltage. In addition, the centers of the embedded references in the different ADC subranges are created by current source arrays, which are digitally scaled according to the coarse ADC's output codes. As a result, the reference-voltage-switching network used in conventional subranging ADCs is not required, and hence the speed of the ADC is increased. Moreover, to eliminate the effects of process variation, the bias currents and body voltages in the RECs are calibrated with an auxiliary resistor ladder. After the calibration, the resistor ladder is removed. Consequently, no resistor ladder is used during normal operation, which greatly saves power. A 3 mW 6-bit 4 GS/s REC-based subranging ADC is implemented in 28-nm CMOS technology. With a near Nyquist frequency input, the ADC achieves SNDRs of 31.8 dB and 30.7 dB at 3.6 GS/s and 4 GS/s, respectively. Moreover, at 3.6 GS/s, the ADC has a Walden Figure-of-Merit (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> ) of 22.7 fJ/conv-step, which is the best compared with prior state-of-the-art 6-bit high-speed ADCs.

A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision

A SAR-assisted SAR ADC that uses a double clock-rate coarse decision technique is presented. The coarse ADC operates with a higher rate clock to reduce the MSBs decision time. The mismatch problem between coarse and fine ADCs is solved by using redundancy and background offset calibration. A simple metastability reduction technique for non-binary SAR ADC that does not require a lookup table is also proposed. The ADC core occupies a 0.0128-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area and consumes 1.9 mW under a 1-V supply. With an 80-MHz input, the ADC achieves an SNDR of 58.1 dB and an SFDR of 72.1 dB. The peak DNL and INL are 0.96 LSB and 1.6 LSB, respectively, and the figure of merit is 24.26 fJ/conversion-step.

Built-in Harmonic Prediction Scheme for Embedded Segmented-Data-Converters

Increase in manufacturing test cost is of paramount issue to chip suppliers, which has been primarily due to costly external testers and long test-time. This paper proposes a loopback-based self-test technique to cost-effectively predict the dynamic nonlinearities of on-chip segmented digital-to-analog-converter (DAC) and analog-to-digital-converter (ADC), by externally looping a DAC back to an ADC, through an external load board employing two parallel paths: a programmable-gain-amplifier (PGA) path and a bypass path for test purpose. A segmented DAC (or ADC) consists of coarse and fine DACs (or ADCs). Two loopback tests are sequentially performed. For the first loopback test, a clean and single-tone sinusoidal signal is applied to a coarse DAC, and it bypasses a fine DAC for test purpose. The obtained DAC output is then fed to a coarse ADC through a bypass path on the load board. Simultaneously, the DAC output is applied to a fine ADC through a PGA path, so that the DAC output signal can fit into the input full-scale range of the fine ADC. For the second loopback test, a sinusoid is fed to a fine DAC, and it bypasses a coarse DAC in this time. Similarly, the DAC output is then applied to a fine and a coarse ADCs through two paths on the load board, at the same time. For postprocessing in on-chip processor, the correlation equations between the dynamic nonlinearities of sub-DACs/ADCs and the aforementioned loopback responses are simultaneously solved to predict the dynamic nonlinearity for each of a DAC and an ADC. Simulation and hardware measurements verified that the proposed technique can be practically used for production testing, by showing less than 0.28-dB and 0.55-dB of the prediction errors, respectively.

A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC

A novel fully time-based two-step analog-to-digital converter (ADC) is proposed. Two time-based ADCs (TB ADCs) are used for coarse ADC (CADC) and fine ADC (FADC), resulting in low-power operation. They are pipelined to increase the sampling frequency. A high-linearity voltage-to-time converter is also proposed to ensure that the CADC has a wide input range. It has a gain-control function to adjust the difference between the gains of the CADC and FADC due to variations in process, voltage and temperature. Moreover, an interpolation time-to-digital converter with a dynamic delayer enables low-power operation. The dynamic delayer is immediately reset when a STOP signal is activated to prevent waste-signal propagation. An 8-bit test chip fabricated with the 65-nm CMOS technology consumed 2.3 mW at 1 GS/s. It also had a sufficiently high signal-to-noise and distortion ratio (SNDR) of 44.4 dB even at the Nyquist frequency. It had a Walden figure of merit of 16 fJ/conversion step.

A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS

A 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) was implemented in a 14 nm SOI FinFET CMOS technology, achieving 59.59 dB SNDR at 50 MS/s while consuming 41.3 µW power. Several techniques were used to increase the energy efficiency while ensuring the linearity. First, a segmented architecture with a 5-bit coarse ADC and an 11-bit fine ADC was used. The aligned Switching with Skip (ASS) method was used to generate the five MSBs of the fine ADC from the computed coarse ADC bits, saving 58% switching power compared with non-segmented architecture with merged capacitor switching (MCS) method. Second, VCM-based MCS scheme is used for SAR bit resolving, saving 85.72% switching power compared with traditional SAR switching. Third, the dual supply mode with analog at 0.8 V and digital at 0.4 V was used. This reduces the total digital logic power consumption by 23% comparing with that using the single supply at 0.8 V. The differential architecture was used to minimize the common mode non-idealities. The proposed ADC has been implemented in a 14 nm SOI FinFET technology and achieved a peak Figure of Merit (FoM) of 1.07 fJ/Conversion-step with simulation results.

A 500-MS/s, 2.0-mW, 8-Bit Subranging ADC with Time-Domain Quantizer

This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ/conversion-step.

A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process**Project supported by the National Natural Science Foundation of China (Nos. 61204033, 61331015), the Fundamental Research Funds for the Central Universities (No. WK2100230015), and the Funds of Science and Technology on Analog Integrated Circuit Laboratory (No. 9140C090111150C09041).

This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μW at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm2.

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320 x 240) resolution. The fabricated chip size is 5 mm x 3 mm, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.

10-bit Two-Step Single Slope A/D 변환기를 이용한 고속 CMOS Image Sensor의 설계

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA() resolution. The fabricated chip size is , and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS

This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a differential segmented capacitive digital-to-analog converter (DAC). The flash ADC controls the thermometer coarse capacitors of the DAC and the SAR ADC controls the binary fine ones. Both theoretical analysis and behavioral simulations show that the differential non-linearity (DNL) of a SAR ADC with a segmented DAC is better than that of a binary ADC. The merged switching of the coarse capacitors significantly enhances overall operation speed. At 150 MS/s, the ADC consumes 1.53 mW from a 1.2-V supply. The effective number of bits (ENOB) is 8.69 bits and the effective resolution bandwidth (ERBW) is 100 MHz. With a 1.3-V supply voltage, the sampling rate is 200 MS/s with 2.2-mW power consumption. The ENOB is 8.66 bits and the ERBW is 100 MHz. The FOMs at 1.3 V and 200 MS/s, 1.2 V and 150 MS/s and 1 V and 100 MS/s are 27.2, 24.7, and 17.7 fJ/conversion-step, respectively.

A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-$\mu$m CMOS

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In this paper, a 6-bit 1-GS/s 49 mW two-channel two-step analog-to-digital converter (ADC) without calibration is implemented in 0.13-<formula formulatype="inline"> <tex Notation="TeX">$\mu{\hbox {m}}$</tex></formula> CMOS process. The proposed multiplying digital-to-analog converter (MDAC) processes the analog signal with two clock periods for one conversion: half for sampling, half for Coarse ADC (CADC) resolving, and one for residue amplification. A self-timing technique is used to prevent disturbance at the beginning of the residue amplification. The reduction of the MDAC output swing by enhancing the accuracy of CADC increases the output devices' over-drive voltage and decreases output loading. The proposed design methods allow closed-loop MDAC to operate at high speed while maintaining low power consumption. The measured SFDR, SNR, and SNDR are 40.7 dB, 33.8 dB, and 33.7 dB, respectively, at the Nyquist rate input. The ADC power dissipation is 49 mW and corresponds to a figure-of-merit (FoM) of 1.24 pJ/conv.-step. The active area occupies 0.16<formula formulatype="inline"><tex Notation="TeX">$~{\hbox {mm}}^{2}$</tex></formula>. </para>

A 150 MS/s 10-bit CMOS Pipelined Subranging ADC with Time Constant Reduction Technique

A 150MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52dB SNDR for a 10MHz input frequency at 150MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35µm CMOS technology, with an active area of 2.7mm2, consuming only 178mW from a single 3V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.

Relativistic Rise Measurements with Very Fine Sampling Intervals

We have studied the ionization loss in small gas samples using a longitudinal drift ionization detector and fast analog to digital conversion techniques. We find this technique can substantially improve the mass resolution capability of gas particle detectors. We have also shown that only a rather coarse ADC resolution is required to capture all the information needed with the truncated mean sampling method of determining the relative energy loss.