CMP Step Research Articles

CMP: Four Decades of Innovation and a Promising Future

The invention of CMP by IBM in 1983 represents an inflection point in the evolution of semiconductors. It was a bold and risky idea to mechanically apply abrasives to the surface of a wafer, but this new process for restoring a wafer to a planar state was the key to continued areal scaling and increased device complexity. Initially applied to a simple application for filling trenches with insulator, the potential of this technique was evident. Through understanding of material properties and subsequent manipulation of slurry chemistry, CMP was applied to enable the more challenging and technically critical processes for Shallow Trench Isolation and Tungsten contacts. The late 1990’s saw the introduction of copper interconnects. IBM was first to market this technology which continues to support conductors down to lines widths on the order of 10 nanometers! The CMP process required for copper interconnects demanded a thorough understanding of the materials present and potential surface phenomena for exploitation. For this need, a new and complex mechanism for copper planarization was invented. Equally challenging was the need for a subsequent non-selective barrier removal step. For this a unique, self-balancing approach was also invented, borrowing some elements from previous STI technology. Device architecture has progressed from planar geometry to FINFETs to Gate All Around, or Nanosheet technology. This evolution has required increasingly more CMP process steps with a concurrent demand for increased process control. Gate height control for Nanosheeets is currently paramount for performance, affected by many CMP steps in the process flow. A typical requirement is less than 1nm added variability per CMP step! Looking forward, CMP continues to be tapped to enable technology evolution. Polish steps are becoming part of the patterning process to enable pitch splitting for upcoming nodes. A VTFET integration approach can enable further area scaling but presents integration challenges; CMP is being asked to enable “third color” schemes for the protection of NFET vs PFET devices which is necessary at various points in the in the VTFET process flow. Heterogeneous Integration is demanding nanometer control of topography across large contact pads and large lateral distances. Finally, extreme scaling is creating fundamental challenges for metal polish at the contact and interconnect levels. CMP tool architecture currently does not provide for control of ambient conditions at the wafer surface during wet transport and post CMP cleaning. Subsequently, unwanted metal dissolution is observed. New tool designs will be needed to control wafer surface conditions, and particularly oxygen exposure through all steps within the CMP tool. This talk is dedicated to the special session in honor of Professor S.V. Babu

A Method of Chemical-Mechanical Polishing of a Thick Silver Layer on Patterned Silicon Wafer

Microfluidics-based biochips for biochemical analysis are receiving much attention nowadays. These composite microsystems, also known as lab-on-a-chip or bio-MEMS, offer a number of advantages over conventional laboratory procedures. They automate highly repetitive laboratory tasks by replacing cumbersome equipment with miniaturized and integrated systems, and they enable the handling of small amounts, e.g., micro- and nano-liters, of fluids. Thus they are able to provide ultra-sensitive detection at significantly lower costs per assay than traditional methods, and in a significantly smaller amount of laboratory space. Advances in microfluidics technology offer exciting possibilities in the realm of enzymatic analysis (e.g., glucose and lactate assays), DNA analysis (e.g., PCR and nucleic acid sequence analysis), proteomic analysis involving proteins and peptides, immuno-assays, and toxicity monitoring.Biochips can be used to detect molecules and/or sequence nucleic acid molecules with aid of an array of electrochemical detector cells containing one or more electrodes per cell where each cell being electrically isolated at a wafer level. For many applications it is beneficial to form a non-planar working electrode using a metal which will corrode during CMP steps.We’ve developed a novel Ag and Cu integration process which a) solves problems of metal corrosion over 3D topography during CMP step and b) prevents metal surface contamination with CMP residual slurry and polishing byproducts not usually removable by brush or megasonic cleaning.Electrochemical studies show corrosion behavior of thick Ag layers in different CMP slurries used in this process. SEM images of cross-sectioned metal lined electrochemical cells (vias) clearly demonstrate advantages of new process (right) without traces of corrosion vs conventional CMP process (left).This process can be used also for polishing of other metals and dielectrics over topography where aggressive cleaning post-CMP steps are not desirable. Figure 1

Effect of Surface Chemistry on Ruthenium Wet Etching

Different types of ALD Ru films, including as-deposited, annealed Ru, without and with a subsequent CMP step, were used for wet etching study. With respect to the as-deposited Ru, the etching rate of the annealed Ru film in metal-free chemical mixtures (pH = 7-9) was found to decrease substantially. X-ray photoelectron spectroscopy characterization indicated that this behavior could be explained by the presence of the formation of RuOx (x = 2,3) caused by the anneal. A short CMP step applied to the annealed Ru wafer removed the surface RuOx, at least partially, resulting in a significant increase of the etching rate. The change in surface roughness was quantified using atomic force microscopy.

Ultra-fine Line Multi-Redistribution Layers with 10 μm Pitch Micro-Vias for Wafer Level and Panel Level Packaging realized by an innovative Excimer Laser Dual Damascene Process

Abstract Multi-chip integrated Fan-Out packages and high I/O CSPs demands for higher routing density on wafer level. Due to that, the classical mask aligner lithography and photosensitive thin-film polymers used for BEOL reach its limits and new technologies and materials are necessary to generate lines and space down to two μm. These multi-metal layers set also higher demands on the mechanical properties of the materials. This paper presents a new excimer laser dual damascene process for ultra-fine routing for BEOL. Various materials like low cure temperature polyimide, BCB and 15-μm thick dry-film ABF material are structured by using an excimer laser stepper with a reticle mask to realize feature size below four μm with a high throughput. Micro-vias with a diameter below five μm are realized with high aspect ratio, which overcome the photolithographic limitations of the common used photosensitive thin-film polymers. The laser structuring allows to use innovative dielectric materials for WLP with optimized mechanical and electrical parameters for example inorganic filled polymers like dry-film ABF materials, which do not have to be photosensitive. The ablations depth per laser pulse and the cross-section of the ablated structures in dependence of the ablation parameters was investigated. The depth of embedded lines was set by number of pulses aside of integrated micro-vias. The lines and micro-vias were metallized with copper by galvanic process and the following CMP step removes the copper outside the ablated structures. The CMP removes only the copper and the metal of the seed-layer, which has the functions of an adhesion and barrier layer, stays intact. The under-etching of the conventional wet etch seed layer removal is a major problem for the fine line structures realized by the Laser Dual Damascene process. Due to that, the removal of the seed layer (usually titan) was investigated and it could be shown, that this layer can be removed by the excimer laser system. The stepper like system allows a sub-micron alignment accuracy with no need of a capture pad of the embedded lines. Test structures have been designed and fabricated with lines and spaces below 10 μm to demonstrate the dense multi-layer routing capability where the excellent reliability can be proven by air to air thermal cycling (from −55°C up to 125°C), current leakage and electro migration test.

(Invited) Critical Review of CMP Requirements in the Future

With the introduction of tri-gate at 22nm technology node by Intel, other logic chip manufacturing technology developers have steadily migrated from planar to 3 dimensional FinFET technology at the fron-end-of-line. Historically, at 0.8μm technology node, there was no CMP although 2-3 metal levels were used. At 0.35μm technology node, a CMP step was introduced. CMP became mainstream with multiple steps requiring CMP at 90nm technology node which continued until 2x nm technology node. However, at 1x (e.g. 14nm) technology node, CMP began to transition from a ‘process simplifier’ to a ‘process enabler’ step. Expanding applications of CMP have made possible the integration of FinFET, RMG (Replacement Metal Gate) and TSV (Through-Silicon-Via)[1]. In sub 1x logic fabrication, the total number of CMP steps may reach 20 or more. Use of FinFET technology in 1x and sub 1x provides much better performance at the same power budget or equal performance at a much lower power budget compared to planar mode[2]. Further, III-V compounds are expected to be integrated at 5nm technology node. III-V materials enable Vdd scaling to address power without sacrificing performance due to the very high electron injection velocity at virtual source compared to Si[3]. These III-V films will require CMP with special care due to the probability of toxic gas release (AsH3/PH3). Beyond 5nm, it is widely assumed that FinFET technology will not be able to provide the small scale features and therefore, gate-all-around technology will be used. To implement gate-all-around, one potential pathway may be to use 2D TMD (2 dimensional transition metal dichalogenide) films. 2D TMD gate-all-around film allows for increasing direct S/D (source/drain) tunneling[4]. With new types of films getting integrated in smaller features, it is necessary therefore to understand the type and nature of various films being used to fabricate devices using sub 1x nm features. In this paper, various US patent applications by leading device manufacturers within the past year will be reviewed to explore the most important CMP steps needed to fabricate new devices. Further, new slurry formulation efforts to enable new CMP requirements for the sub 1x nm devices will be reviewed for the same timeline.

Inspection, Characterization and Classification of Defects for Improved CMP of III-V Materials

Understanding, characterizing and reducing defectivity after CMP is more critical than ever for future technology nodes <10 nm. III-V (e.g. InP and InGaAs) materials are of interest as high mobility channel materials for nMOS for achieving better device performance. In order to integrate these materials, one or more CMP steps are foreseen. Apart from improvement of roughness, we have found that there exist a range of defects on blanket wafers that need to be understood in order to optimize the polishing conditions and consumables. This paper will highlight a methodology to characterize and investigate the origin of defects. Further steps taken to minimize these defects are highlighted for 300 mm III-V wafers.

Development of Next Generation Post Copper CMP Cleaners

Development of post copper CMP cleaning formulations that effectively remove the residues left from the CMP step and corrosion at the conductor and barrier to almost undetectable levels is described. Organic residue removal efficiency and corrosion of interconnects and barrier materials are discussed. Post CMP particle and residue defectivity data will also be presented to demonstrate the cleaning efficiency of the new formulations.

Low temperature MOCVD TiN barrier deposition for high aspect ratio TSVs : A solution for 3D integration

In recent years, 3D integration has become an alternative solution to the “More Moore” concept for providing circuits with higher performance or increased functionality. Via-Middle TSV is considered a reference integration scheme and requires void-free copper fill of very high aspect ratio TSVs. Metallization of such structures, in particular barrier and seed layer deposition, becomes a critical process step as barrier material to copper diffusion must provide good efficiency to copper diffusion for further integration and especially on TSV sidewalls, requiring sufficient step coverage. Ionized PVD is today widely extended from BEOL to TSV metallization. This technique has, however , several limitations for 3D integration coming from its poor step coverage in 10:1 aspect ratio features thus requiring thick material deposition to cover sidewalls which will lead to expensive process both for deposition and further CMP steps and high stress leading to adhesion issues. Considering the maturity level of the alternative processes, MOCVD metallization appears to be a very promising Solution. MOCVD TiN layers have been widely reported to provide excellent step coverage and diffusion barrier efficiency in BEOL processes. The presented study describes a process based on an MOCVD TiN deposition that can be performed from 175 to 400 °C. This polyvalent process can be performed for anytype of 3D integration from Mid process TSVs where performance is the key factor to Via last integration for which low temperature and low cost processes are required. The paper will first discuss the process development and characterization of this material with particular focus on key parameters for 3D integration. In addition, film integration in Via-Middle TSVs will be described, comparing step coverage performance in high aspect ratio TSVs with the I-PVD reference process. Then, electrical measurements of daisy chains and interconnect lines from a 300 mm 3D demonstrator will be presented.

CMP Process Control for Advanced CMOS Device Integration

New CMP steps are required to define the structures for new integration schemes for high-k metal gate and FinFET. The performance and yield of these new devices directly depend on CMP control of film thickness variation. As a consequence, CMP requirements are becoming increasingly stringent. This paper highlights the new process control technologies which enable efficient and cost-effective solutions for the new CMP steps, including FullVision® endpoint & in situ profile control (ISPC) for dielectric and poly CMP, and real-time profile control (RTPC) for aluminum, tungsten, and copper CMP.

Evolution of Post CMP Cleaning Technology

In the sub 40 nm technology nodes, new generation of materials are being incorporated into the complex film stack prior to planarization using CMP. The challenge of cleaning wafers after CMP step has evolved over the years from cleaning simply silicon dioxide to now cleaning porous ultra low-k film as well as various metallic films such as Cu, Ta, Al, Ru, Co, Mn, and sometimes alloy films such as GeSbTe(commonly called GST). It is no longer possible to have one common clean formulation working for all technologies. In this paper, evolution of post CMP cleaning technology will be discussed, primarily focused on Cu process but will address the post CMP cleaning challenges with some of the emerging materials applications.

CMP Solutions for the Integration of High-K Metal Gate Technologies

In order to enable high-k metal gate technology, new CMP steps and slurries are needed to meet the stringent planarity and defect requirements for device performance. This paper will describe several of these slurry technologies in detail, including poly-open-polish, Aluminum CMP, and improvements required in Tungsten polishing. The keys to these technologies are outlined and polishing performance given in detail. The critical mechanisms involved in the material polishing for each of these steps are also introduced. All of these new technologies are needed in order to build a successful high-k metal gate device for advanced node integration via a replacement gate build strategy.

CMP for Cu Interconnect with Advanced Barrier Materials

In this paper, we discuss CMP technology for Cu interconnects with a Co seed enhancement liner (SEL) and Cu with a Ru barrier. Typical forms of galvanic corrosion for each type of barrier are also reviewed. To meet CMP performance requirements, specific polishing and cleaning processes for each CMP step were developed. The overall performance of CMP was evaluated using a variety of patterned wafers, and results are presented.

Cu CMP Edge Uniformity Improvement Studies for 32 nm Technology Node and Beyond

AbstractStudies of the wafer edge uniformity step by step, from hard mask deposition, reactive ion etch, electroplating to post Cu CMP had been done using scanning electron microscopy (SEM) measurements, showed that the major wafer non-uniformity comes from the Cu CMP step. Improvement of Cu CMP edge uniformity had been achieved through engineering of platen 1 using real time profile control as well as CMP head zone pressure adjustment and platen 3 slurry optimizations

Wet cleaning and surface characterization of Si 1− xGe x virtual substrates after a CMP step

New reactants such as ozone dissolved in ultra-pure water have been widely used the last few years instead of the original Radio Corporation of America (RCA) cleaning (which is a combination of the Standard Cleaning 1 (SC1) and the Standard Cleaning 2 (SC2)). In a first part of the study (Microelectron. Eng. 83 (2006) 1986), we had quantified the efficiency of a new cleaning sequence (that calls upon HF and H 2O/O 3 solutions) on polished Si 1− x Ge x virtual substrates ( x = 0.2–0.5). We are discussing here the surface morphology and wetability together with the oxide thickness and structure typically obtained after this so-called “DDC-SiGe” wet cleaning. Flat surface morphologies are found after cleaning whatever the Ge content (from 20 to 50%). Typical root mean square roughness is around 0.4 nm. We have used X-ray Photoelectron Spectroscopy to determine the characteristics of the surface termination after this “DDC-SiGe” cleaning. An oxide mainly composed of SiO 2 is formed, with a low fraction of Ge sub-oxide and GeO 2. The distribution of chemical species is not that different from the one obtained after the use of a SC1 cleaning. However, the chemical oxide formed is slightly thicker. Such a HF/O 3 cleaning leads, when used on thick Ge layers grown on Si, to the formation of a really thin Ge sub-oxide. Our oxidation model assumes a competition in O 3 solutions between the oxidation rates of Si and Ge atoms (faster for Si) and the dissolution of the Ge oxide formed in solution. This mechanism, which implies the formation of a slightly porous oxide, is different from the one seeming to occur in SC1-based solutions. Indeed, the addition of surfactant in a SC1 solution modifies the oxidation rate compared to standard SC1 or O 3-based solutions, suggesting a diffusion of reactants towards the interface between the SiGe and the oxide in formation, assisted by the reactions of species within the cleaning solutions.

Effects of High-Temperature Porogens on Materials Properties of Novel 2-Pahse Low-k Dielectrics

A solid-first scheme was employed for making ultra low-k materials (k < 2.5) based on methylsilsesquioxane (MSQ) and high-temperature porogens in order to circumvent the reliability issues related to as-deposited porous dielectric. Based on thermal stability data, the MSQ/poly(styrene-b-4- vinylpyridine) material system was recommended to be cured at 300 {degree sign}C for subsequent backend processes, and the porogen to be removed at 400 {degree sign}C for 2 hours after CMP step. The mechanical properties of ultra-low-k films used in different integration schemes were further investigated using nano-indentation and FT-IR for various porogen loading. The moduli of 2-phase films were higher than their porous films, and even better than dense MSQ, for porogen loading below a critical level (~50%), which could be attributed to their enhanced degree of crosslinking in MSQ. In addition, MSQ/porogen films cured at 300 {degree sign}C possessed good elastic modulus (> 4.0 GPa) to pass CMP test.

A new CMP-less integration approach for highly scaled totally silicided (TOSI) gate bulk transistors based on the use of selective S/D Si epitaxy and ultra-low gates

In this paper, we present an innovative way of fabricating MOS transistors with totally Ni-silicided (Ni-TOSI) gates without any CMP step before the full gate silicidation process. The combination of the use of a hard-mask-capped ultra-low initial Si gate with a selective S/D epitaxy step enables us to perform the total gate and junction silicidation in one single step similarly to a standard MOS flow. Full gate silicidation and well-controlled junction silicidation is achieved down to minimum gate lengths of 40 nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45 nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process.

Morphological and Structural Evolution of an Ultra-low-k Dielectric During the Porogen Removal

AbstractThe use of porous ultra-low-k materials between interconnections for sub 45nm technologies has introduced some barrier diffusion and mechanical problems. In order to avoid the problems caused by the porosity, a hybrid dense material (porogen and matrix) can be used in an alternate integration scheme. In this approach, the porogen is removed after CMP steps by a thermal cure or UV assisted thermal cure. In this work, we have first characterized the impact of the temperature and the duration of the thermal cure on the material. The crosslinking degree increases and the porogen amount decreases with increasing cure temperature. The most important impact of the curing duration happens between 350°C and 400°C. The increase of the curing duration leads to an increase of the porogen loss and a decrease of the refractive index. Secondly, in order to assess the structure of the layer as a function of the depth, the material was etched in a 0.05% HF solution and then characterized. According to the temperature and duration of the cure, the etch-rate can vary as a function of the material depth. This variation is related to a complex gradient inside the material.

Long Wavelength Roughness Optimization during Thin Cu Film Electropolish

Recent studies of Cu electropolish indicate planarization is not possible due to a large diffusion layer thickness relative to a small post-electroplate step height and small Cu overburden available for electropolish. Assuming an integration scheme that includes a CMP step followed by electropolish, the subsequent challenge of maintaining surface roughness over 300 μm range while electropolishing thin Cu films is addressed by optimizing applied current. For a typical electropolish solution of 6.4 M H 3 PO 4 , 5.4 M glycerin and 17.5 M H 2 O, an rms value of 38 A, comparable to the incoming post-CMP wafers, is demonstrated for 2500 A Cu removal.

Integration of CMP Fixed Abrasive Polishing into the Manufacturing of Thick Film SOI Substrates

AbstractThe specification for the total thickness variation (TTV) of the device layers on thick-film silicon on insulator (SOI) wafers tighten for future applications. Therefore, the bulk removal polishing process of current technology after grinding cannot meet the demands in terms of flatness. The currently required amount of material removal for polishing out the induced sub surface damage (SSD) of the grinding is very high. Additionally, slurry-based CMP processes show unsatisfactory grindline and topography removal. This in turn reflects negatively to processing times, throughput and overall flatness performance.Encouraging early results of FA pad use for silicon and SOI polishing have already been further developed [1]. Low SSD grinding has been introduced to silicon manufacturing [[1]]. In this work, an integrated manufacturing process sequence is presented. Starting from low SSD grinding of the bonded SOI wafer couple, an optimized FA CMP step is replacing the conventional bulk polishing with reduced removal. The SSD after FA CMP is investigated by oxide induced stacking fault (OISF) method [[2]] and results are used to adjust the final polishing step of the substrates. The overall process sequence is highly advantageous in terms of performance in TTV and provides a highly competitive and effective method for achieving best possible surface quality with minimized total silicon removal. This method is not only useful for SOI wafers but also in other areas of silicon processing.

Effect of oxide and W-CMP on the material properties and electromigration behaviour of layered aluminum metallisations

It has been found that chemical mechanical polishing increases the electromigration resistance of a Ti/AlCu/Ti/TiN metal stack. (111) X-ray diffraction polefigures indicate an increased (111) texture of AlCu deposited on a substrate that received at least one CMP step. This improved (111) texture can be attributed to a decreased roughness of the underlying oxide when chemical mechanical polishing is used.