CMOS Voltage Reference Research Articles

A Nano-power Switched-capacitor Voltage Reference Using MOS Body Effect for Applications in Subthreshold LSI

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in 0.18 ?m standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is 17.6 ppm/oC, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately 0.03 mm2.

Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of −40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

A sub‐1 V nanopower temperature‐compensated sub‐threshold CMOS voltage reference with 0.065%/V line sensitivity

AbstractWe present the design of a nanopower sub‐threshold CMOS voltage reference and the measurements performed over a set of more than 70 samples fabricated in 0.18 µm CMOS technology. The circuit provides a temperature‐compensated reference voltage of 259 mV with an extremely low line sensitivity of only 0.065% at the price of a less effective temperature compensation. The voltage reference properly works with a supply voltage down to 0.6 V and with a power dissipation of only 22.3 nW. Very similar performance has been obtained with and without the inclusion of the start‐up circuit. Copyright © 2013 John Wiley & Sons, Ltd.

A high PSRR CMOS voltage reference with 1.2 V operation

A high power supply rejection ratio (PSRR) CMOS band-gap reference (BGR) with 1.2 V operation is proposed in this paper. The reference features include an error amplifier with a trimming circuit and a trimming resistor array on the chip. Local positive feedback is used in the error amplifier to obtain high gain. By trimming the resistor array, the PSRR of the error amplifier is trimmed around one to obtain a high PSRR. The trimming resistor array is controlled externally. The post simulation results indicate that the PSRR is up to ?130 dB@DC and ?89 dB@10 kHz. The experimental results show that, under a supply voltage of 1.2 V the measured PSRR is ?103 dB@dc and ?74 dB@10 kHz.

An ultra-low-power CMOS voltage reference generator based on body bias technique

A CMOS voltage reference, based on body bias technique, has been proposed and simulated using SMIC 0.18μm CMOS technology in this paper. The proposed circuit can achieve a temperature coefficient of 19.4ppm/°C in a temperature range from −20°C to 80°C, and a line sensitivity of 0.024mV/V in a supply voltage range from 0.85V to 2.5V, without the use of resistors and any other special devices such as thick gate oxides MOSFETs with higher threshold voltage. The supply current at the maximum supply voltage and at 27°C is 214nA. The power supply rejection ratio without any filtering capacitor at 10Hz and 10kHz are −88.2dB and −36dB, respectively.

A low power CMOS voltage reference based on body effect

A low power CMOS voltage reference based on body effect

A CMOS Voltage Reference Based on Mutual Compensation of Vtn and Vtp

A novel temperature-stable nonbandgap voltage reference, which is compatible with standard CMOS technology, is presented in this brief. No diodes or parasitic bipolar transistors are used. Based on mutual temperature compensation of the threshold voltages of nMOS and pMOS transistors, a temperature-insensitive voltage reference with significant reduction in temperature dependence of mobility is achieved without using subthreshold characteristics. The problem of a fixed voltage reference value is also avoided by different parameter design. Experimental results of the proposed voltage reference implemented with a 0.35-μm CMOS process demonstrate that the output of the voltage reference is 847.5 mV, a temperature coefficient of 11.8 ppm/ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C with a temperature range from 0 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C to 130 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C is obtained at 3-V power supply, a power-supply noise attenuation of 72 dB is achieved without any filtering capacitor, and the line regulation is better than 0.185 mV/V from 1.8-V to 4.5-V supply voltage dissipating a maximum supply current of 8 μA. The active area of the presented voltage reference is 90 μm ×120 μm.

A HIGH PRECISION CMOS VOLTAGE REFERENCE WITHOUT RESISTORS

With the application of the voltage divider to the traditional bandgap reference without resistors, a high precision CMOS voltage reference without resistors has been proposed. The temperature coefficient has improved because the divider introduces the temperature compensation. The output reference voltage is 410.39 mV at the room temperature. The temperature coefficient of the voltage reference is 3.02 ppm/°C in the range from -20°C to 120°C. Moreover, the power supply rejection ratio of the voltage reference is -52.6 dB and the power consumption is 5.61 μW.

A 140 mV 0.8 μA CMOS voltage reference based on sub-threshold MOSFETs

A CMOS voltage reference circuit based on sub-threshold MOSFETs is proposed, which utilizes a temperature-dependent threshold voltage, a peaking current mirror and sub-threshold technology. The reference has been fabricated in an SMIC 0.13 μm CMOS process with only MOS transistors and resistors. The experimental results show a reference voltage variation of 2 mV for a supply voltage ranging from 0.5 to 1.2 V and 0.8 mV for temperatures from −20 to 120 °C. The proposed circuit generates a reference voltage of 140 mV and consumes a supply current of 0.8 μA at room temperature. The occupied area is only 0.019 mm2.

A low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs

This paper describes a CMOS voltage reference using only resistors and transistors working in weak inversion, without the need for any bipolar transistors. The voltage reference is designed and fabricated by a 0.18 μm CMOS process. The experimental results show that the proposed voltage reference has a temperature coefficient of 370 ppm/°C at a 0.8 V supply voltage over the temperature range of −35 to 85 °C and a 0.1% variation in supply voltage from 0.8 to 3 V. Furthermore, the supply current is only 1.5 μA at 0.8 V supply voltage.

Generating sub-1V reference voltages from a resistorless CMOS bandgap reference circuit by using a piecewise curvature temperature compensation technique

A piecewise curvature compensated CMOS voltage reference that is able to generate a sub-1V reference voltage is presented. The presented voltage reference circuit is operated at a minimum operating voltage of 1.5 V (theoretically 1.408 V) and generates a stable 0.658 V reference voltage with a temperature coefficient of 9.617 ppm/°C over the temperature range of −10 °C to 130 °C. When implemented in a 0.18 μm CMOS technology, the presented design occupies a compact silicon area of 0.022 mm 2. Spectre SPICE simulation showed that the presented design achieves a line regulation of 0.89%, a power supply rejection ratio of −42.3 dB, a power consumption of 0.449 mW at 1.8 V power supply and a high immunity to process variation.

Sub 1 V CMOS bandgap reference design techniques: a survey

This paper presents a review of constraints, limitation factors and challenges to implement sub 1 V CMOS bandgap voltage reference (BVR) circuits in today’s and future submicron technology. Moreover, we provide insight analysis of BVR circuit architectures a designer can relay upon when building CMOS voltage reference.

A 300 nW, 15 ppm/$^{\circ}$C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

A low-power CMOS voltage reference was developed using a 0.35 mum standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745 mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/degC at best and 15 ppm/degC on average, in a range from - 20 to 80degC. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4-3 V, and the power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The power dissipation was 0.3 muW at 80degC. The chip area was 0.05 mm2 . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.

CMOS voltage reference based on threshold voltage and thermal voltage

A fully CMOS based voltage reference circuit is presented in this paper. The voltage reference circuit uses the difference between gate-to-source voltages of two MOSFETs operating in the weak-inver...

A low power CMOS voltage reference circuit with sub threshold MOSFETs

In this paper, a novel approach is proposed for the design of low power CMOS band gap reference circuit. In the literature, an inversion technique is proposed to make the voltage reference to be independent of temperature by using parasitic bipolar transistors. In the above technique, this paper proposes the use of MOSFETs operating in sub threshold region for generating a voltage with negative temperature coefficient. The performance of the proposed scheme is studied by implementing the band gap reference circuit for 1.2 V in TSMC035 CMOS process. Studies through Mentorgraphics IC station and Eldo simulator demonstrate that the proposed scheme has a voltage reference with temperature coefficient of less than 50 ppm/°C over the temperature range of −10°C to 120°C. The proposed scheme results in 18 times lesser area and dissipates ten times lower power compared with that using parasitic bipolar transistors. The circuit technique has been validated using both NMOS and PMOS diode connected sub threshold MOSFETs for generating voltages with negative temperature coefficient.

A CMOS piecewise curvature-compensated voltage reference

This paper presents a novel approach to the design of a high-precision CMOS voltage reference. The proposed circuit utilizes MOS transistors instead of bipolar transistors to generate positive and negative temperature coefficient (TC) currents summed up to a resistive load to generate low TC reference voltage. A piecewise curvature-compensation technique is also used to reduce the TC of the reference voltage within a wider temperature range. The output reference voltage can be adjusted in a wide range according to different system requirements by setting different parameters such as resistors and transistor aspect ratios. The proposed circuit is designed for TSMC 0.6μm standard CMOS process. Spectre-based simulations demonstrate that the TC of the reference voltage is 4.3ppm/°C with compensation compared with 107ppm/°C without compensation in the temperature ranges from −15 to 95°C using a 1.5V supply voltage.

An Assessment of µ-Czochralski, Single-Grain Silicon Thin-Film Transistor Technology for Large-Area, Sensor and 3-D Electronic Integration

Single-grain (SG) thin-film transistors (TFTs) fabricated inside location-controlled silicon grains using the mu-Czochralski method are benchmarked for analog and RF applications. Each silicon grain is defined by excimer laser recrystallization of polysilicon. Thin-film transistors may be fabricated in this manner on silicon or low-cost flexible plastic substrates as processing temperatures remain below 350degC, making the SG-TFT a potential enabling technology for large-area highly integrated electronic systems or systems-in-package with low manufacturing cost. Operational amplifier and voltage reference circuits of varying complexity were designed and measured in order to evaluate the effects of channel position and processing variation on analog circuits. A two-stage telescopic cascode operational amplifier fabricated in an experimental 1.5 mum SG-TFT technology demonstrates a DC gain of 55 dB (unity-gain bandwidth of 6.3 MHz), while a prototype CMOS voltage reference with a power supply rejection ratio (PSRR) of 50 dB is also demonstrated. With fT comparable to single-crystal MOSFETs of comparable gate length, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with on-chip inductors and operating in the 433 MHz ISM band is demonstrated. Excellent agreement with simulations is attained using a modified BSIM-SOI model extracted from measurements of experimental SG-TFT devices.

Single-grain Si thin-film transistors SPICE model, analog and RF circuit applications

Single-grain thin-film transistors (SG-TFTs) fabricated inside location-controlled using μ-Czochralski process exhibit SOI-FETs like performance despite processing temperatures remaining below 350°C. Thus, the SG-TFT is a potential technology for large-area highly-integrated electronic system and system-in-package, taking advantage of the system-on-flexible substrate and low manufacturing cost capabalities. The SG-TFT is modeled based on the BSIMSOI SPICE model where the mobility parameter is modified to fit the SG-TFT behavior. Therefore, analog and RF circuits can be designed and benchmarked. A two-stage telescopic cascode operational amplifier fabricated in a prototype 1.5μm SG-TFT technology demonstrates DC gain of 55dB and unity-gain bandwidth of 6.3MHz. A prototype CMOS voltage reference demonstrates a power supply rejection ratio (PSRR) of 50dB. With unity-gain frequency, fT, in the GHz range, the SG-TFT can also enable RF circuits for wireless applications. A 12dB gain RF cascode amplifier with integrated on-chip inductors operating in the 433MHz ISM band is demonstrated.

A CMOS threshold voltage reference source for very-low-voltage applications

This paper describes a CMOS voltage reference that makes use of weak inversion CMOS transistors and linear resistors, without the need for bipolar transistors. Its operation is analogous to the bandgap reference voltage, but the reference voltage is based on the threshold voltage of an nMOS transistor. The circuit implemented using 0.35μm n-well CMOS TSMC process generates a reference of 741mV under just 390nW for a power supply of only 950mV. The circuit presented a variation of 39ppm/°C (after individual resistor trimming) for the −20 to +80°C temperature range, and produced a line regulation of 25mV/V for a power supply of up to 3V.

CMOS voltage reference with multiple outputs

A voltage reference with two outputs is presented. Both of them are insensitive to temperature, supply voltage and threshold voltage. One of the outputs is ∼0.8 V, and the other one is ∼0.38 V. For the output voltage of 0.8 V, this voltage variation because of supply voltage change from 2.0 to 3.5 V is ±0.66%, and because of temperature change from 0 to 80°C is ±52 ppm/°C. For the output voltage of 0.38 V, this voltage variation because of supply voltage change from 2.0 to 3.5 V is ±1.8%, and because of temperature change from 0 to 80°C is ±50 ppm/°C. The active area of the circuit is ∼0.021 mm2, and the power consumption for the supply voltage of 2 V is 0.8 mW.