CMOS Voltage Reference Research Articles

Optimal superior-order curvature-corrected voltage reference based on the weight difference of gate-source voltages

A new curvature-correction technique for improving the temperature behavior of a CMOS voltage reference will be presented. The reducing of the temperature coefficient for the reference voltage will be realized compensating the nonlinear temperature dependence of the gate-source voltage for a MOS transistor working in weak inversion with the difference between two gate-source voltages. These MOS transistors are biased at drain currents with different temperature dependencies (PTAT and PTAT ?, respectively), ? parameter being selected to the optimal value for the implementing technology. The PTAT voltage generator will be designed using an original Offset Voltage Follower block, with the advantage of a reduced silicon occupied area as a result of replacing classical resistors by MOS active devices. SPICE simulation reports TC = 1.95 ppm/K for an extended temperature range, 273 K < T < 363 K, without considering the parameters spread. The circuit is compatible with low-power low-voltage designed, having a maximal power consumption of 0.4 μW for a minimal supply voltage of 1.1 V.

An Ultra Low-Voltage Ultra Low-Power CMOS Threshold Voltage Reference

This paper describes a CMOS voltage reference that makes use of weak inversion CMOS transistors and linear resistors, without the need for bipolar transistors. Its operation is analogous to the bandgap reference voltage, but the reference voltage is based on the threshold voltage of an nMOS transistor. The circuit implemented using 0.35 μm n-well CMOS TSMC process generates a reference of 741 mV under just 390 nW for a power supply of only 950 mV. The circuit presented a variation of 39 ppm/°C for the -20°C to +80°C temperature range, and produced a line regulation of 25 mV/V for a power supply of up to 3 V.

The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25 V of Output Voltage Using a Fractional VBE Amplification Scheme

This paper describes a CMOS voltage reference circuit which occupies small die area and has less than 1.25 V of output voltage. The reference voltage is determined by a resistor ratio, and it is possible to set the reference voltage from zero to near the supply voltage with the same temperature independence as those of Widlar's and Brokaw's bandgap voltage references. The temperature-independent reference voltage is formed by adding two voltages: the amplified fractional V BE (base-to-emitter voltage) of a bipolar transistor with a negative TC (temperature coefficient) and the amplified V T (thermal voltage) with a positive TC. When a reference voltage smaller than 1.25V is required, the voltage gain of the amplifier for V BE becomes less than one, and the voltage gain of the amplifier for V T becomes small. This enables the size of bipolar transistors for V T generation to be small. The proposed voltage reference circuit was implemented in a standard 0.35-pm CMOS technology. A temperature-independent current source was also obtained from the same circuit. The results were a TC (temperature coefficient) of46ppm/°C over 130°C change, a line regulation of 2.2 mV/V for the 0.5 V reference voltage with 8.7 7μA of current consumption in the voltage reference part, and a 6% change over 130°C change for the 13μA current source.

Ultra-low-power temperature compensated voltage reference generator

A CMOS voltage reference generator, based on the difference between the gate–source voltages of two NMOS transistors, has been implemented with AMS 0.35μm CMOS technology (Vthn=0.45 and Vthp=0.75V at 0°C). The minimum and maximum supply voltages that ensure the correct operation of the reference voltage generator, are 1.5 and 4.3V, respectively. The supply current at the maximum supply voltage and at 80°C is 2.4μA. A temperature coefficient of 25ppm/°C and a line sensitivity of 1.6mV/V are achieved. The power supply rejection ratios without any filtering capacitor at 100Hz and 10MHz are larger than −74 and −59dB, respectively. The occupied chip area is 0.08mm2.

A Temperature and Supply Voltage Independent CMOS Voltage Reference Circuit

A pure CMOS threshold-voltage reference (V TR ) circuit achieves temperature (T) coefficient of 5 μV/°C (T = -60 ∼ +100°C) and supply voltage (V DD ) sensitivity of 0.1 mV/V (V DD = 3 ∼ 5V). A combination of subthreshold current, linear current and saturation current in n-MOSFETs provides a small voltage and temperature dependence. Three different regions in I-V characteristics of MOSFETs generate a constant V TR based on threshold voltage at 0 K. A feedback scheme from the reference output to gates of n-MOSFETs extremely stabilizes the output. The circuit consists of only 17 MOSFETs and its simple scheme saves the die area, which is 0.18 mm 2 in the TEG (Test Element Group) chip fabricated by 1.2 μm n-well CMOS process.

CMOS Zero-Temperature-Coefficient Point Voltage Reference with Variable-Output-Voltage Level

A CMOS voltage reference circuit based on a voltage at the zero-temperature-coefficient point of drain current is proposed. The output voltage of the proposed circuit is variable by a substrate bias. The proposed circuit is simulated with a standard 0.8-μm CMOS technology. The output voltage keeps 800 mV, and its fractional temperature coefficient is 9.94 ppm/°C over the temperature range from -100°C to 150°C at a zero-bias. The PSRR of the output voltage is -42.55 dB at 100 Hz. The minimum power-supply voltage is 2.1 V. The output voltage can be shifted down to 670 mV while maintaining its temperature-insensitivity.

Threshold voltage based CMOS voltage reference

The paper describes a CMOS voltage reference design that uses the temperature dependence of NMOS and PMOS threshold voltages to form a temperature-insensitive reference. No diodes or parasitic bipolar transistors are used. The circuit architecture accommodates a wide range of output voltages. A test chip is fabricated using a 0.5 /spl mu/m CMOS process. The prototype achieves a temperature coefficient of 32 ppm//spl deg/C for a temperature range of -10/spl deg/C to 80/spl deg/C and a supply voltage sensitivity of 10 mV/V.

CMOS voltage reference based on gate work function differences in poly-si controlled by conductivity type and impurity concentration

A new CMOS voltage reference circuit consisting of two pairs of transistors is presented. One pair exhibits a threshold voltage difference with a negative temperature coefficient (-0.49 mV/°C), while the other exhibits a positive temperature coefficient (+0.17 mV/°C). The circuit was robust to process variations and exhibited excellent temperature independence and stable output voltage. Aside from conductivity type and impurity concentrations of gate electrodes, transistors in the pairs were identical, meaning that the system was robust with respect to process fluctuations. Measurements of the voltage reference circuit without trimming adjustments revealed that it had excellent output voltage reproducibility of within ±2%, low temperature coefficient of less than 80 ppm/°C, and low current consumption of 0.6 μA.

A CMOS voltage reference based on weighted ΔV/sub GS/ for CMOS low-dropout linear regulators

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-μm CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0°C). The occupied chip area is 0.055 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 μA. A typical mean uncalibrated temperature coefficient of 36.9 ppm/°C is achieved, and the typical mean line regulation is ±0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).

A low-voltage low-power voltage reference based on subthreshold MOSFETs

In this work, a new low-voltage low-power CMOS voltage reference independent of temperature is presented. It is based on subthreshold MOSFETs and on compensating a PTAT-based variable with the gate-source voltage of a subthreshold MOSFET. The circuit, designed with a standard 1.2-μm CMOS technology, exhibits an average voltage of about 295 mV with an average temperature coefficient of 119 ppm/°C in the range -25 to +125°C. A brief study of gate-source voltage behavior with respect to temperature in subthreshold MOSFETs is also reported.

A comparison of deterministic and statistical sampling techniques for quality analysis of integrated circuits

AbstractThere has been a great amount of publicity about Taguchi methods which employ deterministic sampling techniques for robust design. Also given wide exposition in the literature is tolerance design which achieves similar objectives but employs random sampling techniques. The question arises as to which approach—random or deterministic—is more suitable for robust design of integrated circuits. Robust design is a two‐step process and quality analysis—the first step—involves the estimation of ‘quality factors’, which measure the effect of noise on the quality of system performance. This paper concentrates on the quality analysis of integrated circuits. A comparison is made between the deterministic sampling technique based on Taguchi's orthogonal arrays and the random sampling technique based on the Monte Carlo method, the objective being to determine which of the two gives more reliable (i.e. more consistent) estimates of quality factors. Results obtained indicated that the Monte Carlo method gave estimates of quality which were at least 40 per cent more consistent than orthogonal arrays. The accuracy of prediction of quality by Taguchi's orthogonal arrays is strongly affected by the choice of parameter quantization levels—a disadvantage—since there is a very large number (theoretically infinite) of choices of quantization levels for each parameter of an integrated circuit. The cost of the Monte Carlo method is independent of the dimensionality (number of designable parameters), being governed only by the confidence levels required for quality factors, whereas the size of orthogonal array required for a given problem is partly dependent on the number of circuit parameters. Two integrated circuits—a 7‐parameter CMOS voltage reference and a 20‐parameter bipolar operational amplifier—were employed in the investigation. Quality factors of interest included performance variability, acceptability (relative to customer specifications) and deviation from target.

Correction to "A CMOS Voltage Reference"

Correction to "A CMOS Voltage Reference"

An Application of Monolithic CMOS Voltage Reference to Wrist Watch

An Application of Monolithic CMOS Voltage Reference to Wrist Watch