CMOS Voltage Reference Circuit Research Articles

An 18-nW CMOS Current and Voltage Reference Circuit With Low Line Sensitivity and Wide Temperature Range

An 18-nW CMOS Current and Voltage Reference Circuit With Low Line Sensitivity and Wide Temperature Range

Optimal Design of Voltage Reference Circuit and Ring Oscillator Circuit Using Multiobjective Differential Evolution Algorithm

This paper deals with the optimal design of different VLSI circuits, namely, the CMOS voltage reference circuit and the CMOS ring oscillator (RO). The optimization technique used here is the multiobjective differential evolution algorithm (MDEA). All the circuits are designed for 90 nm technology. The main objective of the CMOS voltage reference circuit is to minimize the voltage variation at the output. The targeted value of the reference voltage is 550 mV. A CMOS ring oscillator (RO) is designed depending on the performance parameters such as power consumption and phase noise. The optimal transistor sizing of each circuit is obtained from MDEA. Each circuit is implemented in SPICE by taking the optimal dimensions of the transistors, and the performance parameters are achieved. The designed voltage reference circuit achieves a reference voltage of 550 mV with 600 nW power dissipation. The reference voltage variation of 8.18% is observed due to temperature variation from −40°C to + 125°C. The MDEA-based optimal design of RO oscillates at 2.001 GHz frequency, has a phase noise of −87 dBc/Hz at 1 MHz offset frequency, and consumes 71 μW power. This work mainly aims to optimize the MOS transistors’ sizes using MDEA for better circuit performance parameters. SPICE simulation has been carried out by using the optimal values of MOS transistor sizes to exhibit the performance parameters of the circuit. Simulation results establish that design specifications are closely met. SPICE results show that MDEA is a better technique for the optimal design of the above-mentioned VLSI circuits.

A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation

In this paper, a 0.6 V subthsheshold CMOS voltage reference (CVR) achieving wide temperature range and high power supply ripple rejection (PSRR) is presented. The proposed CVR structure can compensate the high temperature leakage and current mirror induced mismatches so as to increase the operating temperature range. The generated reference voltage of the proposed CVR circuit is the threshold voltage difference of two NMOS transistors, leading to relatively small variations. Moreover, the enhanced current source helps achieve high PSRR. The proposed CVR circuit is implemented in a standard 0.18-μm CMOS technology. Measurement results show that, with one single trimming, a mean output of 344 mV with standard deviation of only 2.89 mV and average TC of 44.6 ppm/°C over a wide temperature range from −40 °C to 125 °C is achieved. The measured PSRR is −68 dB, −52 dB and −52 dB at 10 Hz, 100 kHz and 10 MHz, respectively. The measured line sensitivity (LS) is 0.06%/V with a power supply from 0.6 V to 2 V while consuming 19.8 nW at 0.6 V supply. The active area is 0.019 mm2.

A CMOS symmetric self-biased voltage reference

This paper presents a novel CMOS voltage reference circuit named symmetric self-biased voltage reference (SSVR), which enables not only to discard the voltage headroom issue of a conventional constant-gm current source and the inevitable need of an extra bias in a modified constant-gm current source, but also to maintain stable bias voltages with strong tolerance against significant variations of power supply and temperature. Test chips of the SSVR were implemented by using a 0.11-μm CMOS process. Measured results demonstrate that the symmetric configuration of the proposed SSVR helps to achieve constant voltage references against the VDD variation from 0.7 to 1.2 V and the temperature variation from −15 °C to 125 °C. The fabricated chip consumes constant 18.5 μA currents for 0.7 ∼ 1.0-V supply voltages and its core occupies the area of 0.04 × 0.047 mm2.

A 0.6 V temperature-stable CMOS voltage reference circuit with sub-threshold voltage compensation technique

A 0.6 V temperature-stable CMOS voltage reference circuit with sub-threshold voltage compensation technique

An Ultralow Power Subthreshold CMOS Voltage Reference Without Requiring Resistors or BJTs

This brief presents a novel ultralow power CMOS voltage reference (CVR) with only 4.6-nW power consumption. In the proposed CVR circuit, the proportional-to-absolute-temperature voltage is generated by feeding the leakage current of a zero- $V_{\mathrm {gs}}$ nMOS transistor to two diode-connected nMOS transistors in series, both of which are in subthreshold region; while the complementary-to-absolute-temperature voltage is created by using the body diodes of another nMOS transistor. Consequently, low-power operation can be achieved without requiring resistors or bipolar junction transistors, leading to small chip area consumption. The proposed CVR circuit is fabricated in a standard 0.18- $\mu \text{m}$ CMOS process. Measurement results show that the prototype design is capable of providing a 755 mV typical reference voltage with 34 ppm/°C from −15 °C to 140 °C. Moreover, the typical power consumption is only 4.6 nW at room temperature and the active area is only 0.0598 mm2.

Sub-1 V, pico-watt subthreshold CMOS voltage reference circuit with dual temperature compensation

A pico-watt CMOS voltage reference is developed using an SK Hynix 0.18µm CMOS process. The proposed architecture is resistorless and consists of MOSFET circuits operated in the subthreshold region. A dual temperature compensation technique is utilized to produce a near-zero temperature coefficient reference output voltage. Experimental results demonstrate an average reference voltage of 250.7mV, with a temperature coefficient as low as 3.2ppm/°C for 0 to 125°C range, while the power consumption is 545pW under a 420mV power supply at 27°C. The power supply rejection ratio and output noise without any filtering capacitor at 100Hz are −54.5dB and 2.88µV/Hz1/2, respectively. The active area of the fabricated chip is 0.00332mm2.

A high-PSRR low-power CMOS voltage reference based on weighted VGS difference

A high PSRR CMOS voltage reference circuit suitable for applications with noisy environments like power telemetry solutions and system on a chip (SOC) integrations is presented. The reference voltage is generated based on the difference between weighted gate-to-source voltages (VGS) of MOS transistors operating in subthreshold region. The circuit PSRR is improved using a new circuit configuration which removes the need for a passive resistive branch to scale up VGS voltages. The PSRR is further enhanced by reordering the pole-zero locations of the PSRR transfer function and then using supply-independent biasing circuit. Implemented in a 0.18μm standard CMOS process, the circuit occupies an area of about 0.035mm2. The minimum supply voltage is 1.4V and the maximum temperature coefficient is about 82ppm/°C. The PSRR at 100Hz and 10MHz frequencies are approximately −70dB and −100dB respectively. Using a 1.8V supply voltage, it consumes at least 42nA and at most 125nA depending on operating temperature and process corners.

250-mV Supply Subthreshold CMOS Voltage Reference Using a Low-Voltage Comparator and a Charge-Pump Circuit

This brief proposes a subthreshold CMOS voltage reference circuit, which reduces the minimum supply voltage by replacing the analog amplifier in the conventional CMOS voltage reference circuit with a low-voltage comparator, a charge-pump circuit, and a digital control circuit. The subthreshold CMOS voltage reference circuit was fabricated using a 0.11-μm CMOS process. Its core area was 0.013 mm 2 and it consumed 5.35 μW at V DD = 250 mV and f CLK = 1 MHz. Its minimum supply voltage was 242 mV. Ten sample chips generated 193-207-mV reference voltage with 0.4-3.2-mV/100-mV line sensitivity at V DD = 250-400 mV and 58-186 ppm/°C temperature coefficient at 10 °C-90 °C.

Design and implementation of a micro-power CMOS voltage reference circuit based on thermal compensation of Vgs

In this work a simple all MOS voltage reference circuit has been proposed. To obtain reference output voltage, the thermal compensation has been generated by using a series composite NMOSTs. The voltage reference circuit has been fabricated in a standard 0.18μm CMOS technology. The proposed circuit is capable of working for the supply voltage ranging from 1.25V to 2V. The maximum power dissipation of the proposed circuit is 0.48μW at the supply voltage of 2V. The measurement has been performed over a set of 10 samples. It resulted in the mean temperature coefficient (TC) of 19.302ppm/°C for the temperature range of −40°C to 85°C. The measured mean line sensitivity is 2.217mV/V for the supply voltage ranging from 1.25V to 2V at the room temperature. The measured mean power supply rejection ratio at 10Hz and 1MHz is −55.31dB and −16.67dB respectively for the supply voltage of 1.8V. Moreover, the measured mean noise density without any filtering capacitor at 100Hz and 100kHz are 12.39μV/Hz and 0.39μV/Hz respectively. Due to its simple circuit implementation, the active area of the circuit is 0.0077mm2.

Radiation-Hardening Technique for Voltage Reference Circuit in a Standard 130 nm CMOS Technology

A radiation-hardening technique for a CMOS voltage reference circuit is proposed. Its operation principle consists in combining linearly two different NMOS threshold voltages and a Proportional-To-Absolute-Temperature (PTAT) voltage, which allows the compensation of both temperature-induced and radiation-induced discrepancies. This circuit was implemented in a standard 130 nm CMOS technology and designed in two different layouts. Measurements show a good operation with a minimal supply voltage of 2.5 V, a PSRR of 80 dB at 3.3 V. The voltage output shift is around 0.5% under irradiation up to 40 krad(Si). The active area of the circuit is about 0.04 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of −40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

A 140 mV 0.8 μA CMOS voltage reference based on sub-threshold MOSFETs

A CMOS voltage reference circuit based on sub-threshold MOSFETs is proposed, which utilizes a temperature-dependent threshold voltage, a peaking current mirror and sub-threshold technology. The reference has been fabricated in an SMIC 0.13 μm CMOS process with only MOS transistors and resistors. The experimental results show a reference voltage variation of 2 mV for a supply voltage ranging from 0.5 to 1.2 V and 0.8 mV for temperatures from −20 to 120 °C. The proposed circuit generates a reference voltage of 140 mV and consumes a supply current of 0.8 μA at room temperature. The occupied area is only 0.019 mm2.

A low power CMOS voltage reference circuit with sub threshold MOSFETs

In this paper, a novel approach is proposed for the design of low power CMOS band gap reference circuit. In the literature, an inversion technique is proposed to make the voltage reference to be independent of temperature by using parasitic bipolar transistors. In the above technique, this paper proposes the use of MOSFETs operating in sub threshold region for generating a voltage with negative temperature coefficient. The performance of the proposed scheme is studied by implementing the band gap reference circuit for 1.2 V in TSMC035 CMOS process. Studies through Mentorgraphics IC station and Eldo simulator demonstrate that the proposed scheme has a voltage reference with temperature coefficient of less than 50 ppm/°C over the temperature range of −10°C to 120°C. The proposed scheme results in 18 times lesser area and dissipates ten times lower power compared with that using parasitic bipolar transistors. The circuit technique has been validated using both NMOS and PMOS diode connected sub threshold MOSFETs for generating voltages with negative temperature coefficient.

The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25 V of Output Voltage Using a Fractional VBE Amplification Scheme

This paper describes a CMOS voltage reference circuit which occupies small die area and has less than 1.25 V of output voltage. The reference voltage is determined by a resistor ratio, and it is possible to set the reference voltage from zero to near the supply voltage with the same temperature independence as those of Widlar's and Brokaw's bandgap voltage references. The temperature-independent reference voltage is formed by adding two voltages: the amplified fractional V BE (base-to-emitter voltage) of a bipolar transistor with a negative TC (temperature coefficient) and the amplified V T (thermal voltage) with a positive TC. When a reference voltage smaller than 1.25V is required, the voltage gain of the amplifier for V BE becomes less than one, and the voltage gain of the amplifier for V T becomes small. This enables the size of bipolar transistors for V T generation to be small. The proposed voltage reference circuit was implemented in a standard 0.35-pm CMOS technology. A temperature-independent current source was also obtained from the same circuit. The results were a TC (temperature coefficient) of46ppm/°C over 130°C change, a line regulation of 2.2 mV/V for the 0.5 V reference voltage with 8.7 7μA of current consumption in the voltage reference part, and a 6% change over 130°C change for the 13μA current source.

A Temperature and Supply Voltage Independent CMOS Voltage Reference Circuit

A pure CMOS threshold-voltage reference (V TR ) circuit achieves temperature (T) coefficient of 5 μV/°C (T = -60 ∼ +100°C) and supply voltage (V DD ) sensitivity of 0.1 mV/V (V DD = 3 ∼ 5V). A combination of subthreshold current, linear current and saturation current in n-MOSFETs provides a small voltage and temperature dependence. Three different regions in I-V characteristics of MOSFETs generate a constant V TR based on threshold voltage at 0 K. A feedback scheme from the reference output to gates of n-MOSFETs extremely stabilizes the output. The circuit consists of only 17 MOSFETs and its simple scheme saves the die area, which is 0.18 mm 2 in the TEG (Test Element Group) chip fabricated by 1.2 μm n-well CMOS process.

CMOS Zero-Temperature-Coefficient Point Voltage Reference with Variable-Output-Voltage Level

A CMOS voltage reference circuit based on a voltage at the zero-temperature-coefficient point of drain current is proposed. The output voltage of the proposed circuit is variable by a substrate bias. The proposed circuit is simulated with a standard 0.8-μm CMOS technology. The output voltage keeps 800 mV, and its fractional temperature coefficient is 9.94 ppm/°C over the temperature range from -100°C to 150°C at a zero-bias. The PSRR of the output voltage is -42.55 dB at 100 Hz. The minimum power-supply voltage is 2.1 V. The output voltage can be shifted down to 670 mV while maintaining its temperature-insensitivity.

CMOS voltage reference based on gate work function differences in poly-si controlled by conductivity type and impurity concentration

A new CMOS voltage reference circuit consisting of two pairs of transistors is presented. One pair exhibits a threshold voltage difference with a negative temperature coefficient (-0.49 mV/°C), while the other exhibits a positive temperature coefficient (+0.17 mV/°C). The circuit was robust to process variations and exhibited excellent temperature independence and stable output voltage. Aside from conductivity type and impurity concentrations of gate electrodes, transistors in the pairs were identical, meaning that the system was robust with respect to process fluctuations. Measurements of the voltage reference circuit without trimming adjustments revealed that it had excellent output voltage reproducibility of within ±2%, low temperature coefficient of less than 80 ppm/°C, and low current consumption of 0.6 μA.