CMOS VCO Research Articles

A Compact 0.73~3.1 GHz CMOS VCO Based on Active-Inductor and Active-Resistor Topology

In this paper, a wideband VCO that covers popular Long-Term Evolution (LTE) 0.7 GHz and LTE 2.6 GHz frequencies is designed and developed in a standard 0.18 μm CMOS process. The VCO utilizes active inductors to achieve coarse-tuning of the inductance and a compact chip area. Moreover, an active feedback resistor is introduced into the active inductor for fine-tuning of the inductance. The feedback resistor also affects the equivalent resistance of the active inductor; therefore, wide inductance tuning and low power consumption can be obtained by optimizing the resistor. The core area of the fabricated CMOS chip is merely 0.046 mm2, excluding all testing pads. With a 6.7~10.1 mW DC consumption, the measured oscillation frequencies range from 0.73 GHz to 3.1 GHz, which demonstrates a 123.8% tuning range. At the frequencies of interest, the measured phase noises are from −80.7 to −84.5 dBc/Hz at a 1 MHz offset frequency.

Design of Low-Power CMOS VCO with Three Transistors NAND Gate and MOS Varactor

Design of Low-Power CMOS VCO with Three Transistors NAND Gate and MOS Varactor

A 196.5 dBc/Hz FOM T 16.8–21.6-GHz Class-F23 CMOS VCO With Transformer-Based Optimal Q-Factor Tank

This letter presents an optimal tank- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> Class-F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">23</sub> voltage-controlled oscillator (VCO) in 65-nm CMOS. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -factor of the transformer-based multi-LC resonator is maximized in the Class-F operation mode by the proposed graphical <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -optimization method. The frequency tuning range (TR) is expanded by 26% as well. The phase noise (PN) is improved by reshaping the impulse sensitivity function (ISF) with the 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> and 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> harmonic tuning. Occupying 0.112 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the VCO at 16.8 GHz exhibits −112.2 dBc/Hz PN at 1 MHz offset and 196.5 dBc/Hz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{FOM}_{T}$ </tex-math></inline-formula> at 10 MHz offset. The measured TR is 25% (16.8–21.6 GHz). The oscillator core consumes 7 mW at 1 V supply.

Wide Tuning-range LO Chain with a Hybrid Inductor for LTE and SAW-less GSM Transceiver

A low phase noise, multi-standard local oscillator (LO) chain for LTE and GSM is presented. The LO chain is composed of a dynamic divider and a CMOS VCO with a hybrid inductor using both bondwire and a planar spiral inductor in the same area. This approach improves both tuning range and phase noise characteristics without additional area loss. Based on this concept, the LO chain with a hybrid inductor VCO is implemented in a 65nm CMOS process. The measured performance satisfies wide tunability and most stringent GSM transmitter phase noise specification, which proves that the LO chain can be used for LTE and SAW-less GSM transceiver.

58 GHz CMOS VCO with 16% efficiency

This Letter presents a millimetre-wave CMOS oscillator, which achieves 4.9 dBm output power with 16% peak power efficiency. A phase noise of − 98 dBc / Hz at 1 MHz offset frequency and 26.7% tuning range around 57.5 GHz centre frequency were verified experimentally. To the best knowledge of the authors, the output power, efficiency, and phase noise performance are the best among fundamental CMOS oscillators in the frequency range of interest, while the tuning range is the third highest result reported to date. The circuit occupies a silicon area of ∼ 9000 μ m 2 without the matching inductors on a 22 nm fully depleted silicon on insulator (FD-SOI) CMOS technology.

The State of the Art in CMOS VCOs: Mm-Wave VCOs in Advanced CMOS Technology Nodes

There is a growing interest in the realization of highly integrated radar transceivers operating at millimeter-wave (mm-wave) frequencies. In this case, CMOS is the natural technology choice. Modern nanoscale CMOS technologies offer excellent transistor performance with transit frequencies ( f T ) and maximum oscillation frequencies ( f max) exceeding several hundreds of gigahertz. This enables the realization of highly integrated, digitally intensive transceiver systems on chip for mmwave applications, such as 77-GHz automotive radar [1] or wireless data communication systems [2]. Several advanced nanoscale CMOS nodes even surpass the f T and f max values achieved by silicon germanium (SiGe) heterojunction bipolar transistor technologies [3].

A Low-voltage Low-power Wideband CMOS VCO with Robust Sub-band Switching Technique

A Low-voltage Low-power Wideband CMOS VCO with Robust Sub-band Switching Technique

A 40‐GHz hybrid class‐AB/class‐BCMOSVCO with a current‐combining transformer

AbstractA 40‐GHz hybrid class‐AB/class‐B CMOS VCO with a current‐combining transformer (CCT) using a 65‐nm RF CMOS process is presented. The hybrid class‐AB/class‐B configuration is adapted to two cross‐coupled pairs to lower the power consumption while maintaining the phase noise performance. As a simple coupling network between two cross‐coupled pairs with different bias conditions, the CCT performs the roles of a high Q‐factor resonator, a large impedance transformer, and a buffer without additional circuitry. The VCO operates at 38.15–40 GHz with power consumption in the range of 11–13 mW. The measured phase noise at a 1‐MHz offset from the 40 GHz carrier is −117.1 dBc/Hz with a 1.0 V supply voltage. The proposed power oscillator achieves an FOMT value of −191.3 dBc/Hz.

Wide Tuning Range CMOS VCO

Wide Tuning Range CMOS VCO

2.4 GHZ HETERODYNE RECEIVER FOR HEALTHCARE APPLICATION

&lt;p class="lead"&gt;The objective of this research was to design a basic 2.4 GHz heterodyne receiver for healthcare on a 130um CMOS process. The ultimate goal for the wireless industry is to minimize the trade-offs between performance and cost, and between performance and low power consumption design. In the first part, a low noise amplifier (LNA), which is commonly used as the first stage of a receiver, is introduced and simulated. LNA performance greatly affects the overall receiver performance. The LNA was designed at the 2.4 GHz ISM band, using the cascode with an inductive degeneration topology. The second part of this thesis presents a low power 2.4 GHz down conversion Gilbert Cell mixer. In the third part, a high-performance LC-tank CMOS VCO was designed at 2.4 GHz. The design uses using PMOS cross-coupled topology with the varactor for wider tuning range topology. In the first part, a low noise amplifier (LNA) design reaches the NF of 2 dB, has a power consumption of 2.2 mW, and has a gain of 20dB. The second part of this proposal presents a low power 2.4 GHz down conversion Gilbert Cell mixer. The obtained result shows a conversion gain of 14.6 dB and power consumption of 8.2 mW at a 1.3V supply voltage. In the third part, a high-performance LC-tank CMOS VCO was designed at 2.4 GHz. The final simulation of the phase noise is-128 dBc/Hz, and the tuning range is 2.3 GHz-2.5 GHz while the total power consumption is 3.25 mW.&lt;strong&gt; &lt;/strong&gt;The performance of the receiver meets the specification requirements of the desired standard.&lt;/p&gt;

Design of low phase noise CMOS VCO using cross coupled topology with capacitor feedback

In this paper, a new structure for a capacitor feedback with quality factor enhancement of 5GHz band CMOS VCO is presented. The proposed VCO was able to reduce the parasitic effect of the circuit at high frequencies and without additional body biased voltage. The phase noise was improved with this capacitor feedback circuit. The circuit was analyzed by means of a simplified high frequency model. The improvement of low power consumption resulted from the adopted self-body biased technology without additional body biased voltage. The optimal low voltage design with 0.8V was determined as the aim for low phase noise. The measured bandwidth of the frequency was from 5.07GHz to 6.2GHz with a 20.37% tuning ratio. The core consumption was 2.8mW from the 0.8V supply. The phase noise of the proposed VCO was −117.34dBc/Hz at an offset frequency of 1MHz. The figure of merit was −187.45dBc/Hz and the figure of merit with tuning range (FOMT) was −193.6dBc/Hz.

Low-phase-noise CMOS VCO with new drain–gate feedback path

In this paper a new LC oscillator without tail current source with an impedance transformation block (ITB) has been presented. Using this ITB, the noise generation from active devices is reduced. The cross-coupled transistors remain mostly in the saturation region and prevent decreasing of LC-tank quality factor. Moreover this structure benefits from more relaxed start-up condition as compared to the conventional LC oscillators and preserves its low phase-noise performance even in low voltage operation. This oscillator is designed and simulated in 0.18 µm CMOS process. The simulation results show that the proposed oscillator achieved a phase noise between ź138.5 and ź141.2 dBc/Hz at 3 MHz frequency offset with 23 % tuning range between 4.61 and 5.79 GHz. The corresponding Figure-of-merit in this tuning range is between ź189.1 and ź192.1 dBc/Hz which is among the best reported performance in comparison to the other state of the arts designs.

Design Issues of Inductor for Low Phase Noise CMOS VCO with Wide Tuning Range

본 논문에서는 광대역 특성을 갖는 저위상잡음 CMOS VCO를 위한 인덕터(Inductor) 구조를 제안한다. 제안된 인덕터는 광대역 특성을 위해 낮은 인덕턴스(Inductance)와 높은 quality factor를 가져, 낮은 위상잡음 특성을 나타낼 수 있도록 설계되었으며, 적용할 통신 표준(Standard)의 주파수 대역과 위상잡음 규격 및 Chip 크기를 고려하여, 평면형 spiral 인덕터와, 3-D bondwire 인덕터 구조로 구현되었다. 제안된 인덕터 성능을 입증하기 위해, 2가지 통신 표준의 CMOS VCO를 설계, 제작 및 측정하였다. RFID VCO는 1.7GHz에서 415MHz의 동작 주파수 범위와, 200kHz offset에 대해 -120.7dBc/Hz의 위상잡음 및 1.8V, 21mA의 전력소모를 나타낸다. WCDMA는 3.7GHz에서 1GHz의 동작 주파수 범위와, 3MHz offset에 대해 -130.1dBc/Hz의 위상잡음 및 1.3V, 7.5mA의 전력소모를 나타낸다. 두 VCO 모두 적용된 통신 표준의 설계규격을 만족하며 RFID VCO는 -184.1, WCDMA는 -181.7의 FOM으로, 제안된 인덕터를 적용한 VCO의 우수한 성능을 나타낸다.

A 3.16–7 GHz transformer-based dual-band CMOS VCO**Project supported by the National High Technology Research and Development Program of China (No. 2011AA10305) and the National Natural Science Foundation of China (No. 60901012).

A dual-band, wide tuning range voltage-controlled oscillator that uses transformer-based fourth-order (LC) resonator with a compact common-centric layout is presented. Compared with the traditional wide band (VCO), it can double frequency tuning range without degrading phase noise performance. The relationship between the coupling coefficient of the transformer, selection of frequency bands, and the quality factor at each band is investigated. The transformer used in the resonator is a circular asymmetric concentric topology. Compared with conventional octagon spirals, the proposed circular asymmetric concentric transformer results in a higher quality-factor, and hence a lower oscillator phase noise. The VCO is designed and fabricated in a 0.18-μm CMOS technology and has 75% wide tuning range of 3.16–7.01 GHz. Depending on the oscillation frequency, the VCO current consumption is adjusted from 4.9 to 6.3 mA. The measured phase noises at 1 MHz offset from carrier frequencies of 3.1, 4.5, 5.1, and 6.6 GHz are −122.5, −113.3, −110.1, and −116.8 dBc/Hz, respectively. The chip area, including the pads, is 1.2 × 0.62 mm2 and the supply voltage is 1.8 V.

A Wide Tuning-Range CMOS VCO with a Tunable Active Inductor

This study describes a wide tuning-range VCO using tunable active inductor (TAI) topology and cross-coupled pair configuration for radio frequency operation. The TAI used two feedback loops to form a cascode circuit to obtain more degrees of freedom for inductance value. The TAI-VCO was fabricated using a 0.18 μm CMOS technology. The coarse frequency tuning is achieved by TAIs while the fine tuning is controlled by varactors. The fabricated circuit provides an output frequency range from 0.6 to 7.2 GHz (169%). The measured phase noise is from −110.38 to −86.01 dBc/Hz at a 1 MHz offset and output power is from −11.11 to −3.89 dBm within the entire frequency range under a 1.8 V power supply.

Ku-밴드 광대역 CMOS 전압 제어 발진기

본 논문에서는 상호 교차결합 차동(complementary cross-coupled differential)구조를 기반으로 조절 주파수 범위가 넓은 광대역 Ku-band 전압 제어 발진기를 0.18-㎛ CMOS 공정 기술을 바탕으로 설계 후 제작하여 주파수 조절 범위와 출력 스펙트럼, 위상잡음 등을 측정하여 분석하였다. PMOS와 NMOS가 캐스코드의 push-pull 구조로 연결되어 상호 교차된 차동발진기구조에 주파수 제어용으로 MOS varactor를 사용한 본 전압 제어 발진기는 발진주파수 14.5㎓의 20%인 2.24㎓ 의 매우 넓은 광대역의 주파수 제어를 달성하였음을 측정으로 확인하였다. 3.3V 전원으로부터 18㎃의 DC 전류를 공급하였을 때 발진출력전력은 -1.66㏈m으로 측정되었으며, 5V 전원으로부터 47㎃의 DC 전류를 공급하였을 때 발진 출력전력은 0.84㏈m으로 측정되었다. 위상잡음은 100㎑ offset 주파수에서 ?74.5㏈c/㎐로 측정되었다. 본 논문의 칩은 패드를 포함하여 1.02㎜×0.66㎜의 면적을 갖는다.

A Harmonic Class-C CMOS VCO-Based on Low Frequency Feedback Loop: Theoretical Analysis and Experimental Results

A novel harmonic Class-C CMOS VCO architecture with improved phase noise performance and power efficiency is presented in this paper. The VCO is based on the widely adopted topology consisting in a crossed pair of NMOS devices refilling a symmetric resonator with a center tapered inductor and biased by a top PMOS current generator. The Class-C operation mode is obtained through a low frequency feedback loop constituted by an operational transconductance amplifier operating the difference between the inductor center tap voltage and a reference voltage, pushing gate polarization voltage of VCO crossed pair devices well below their threshold voltage. The Class-C VCO achieves a theoretical 2.9 dB phase noise improvement compared to the standard differential-pair LC-tank oscillator for the same current consumption. A prototype of the VCO is implemented in a standard RF 55 nm CMOS technology and compared to both a standard and an optimized VCO implemented in the same technology. All these VCOs share a copy of a unique resonator. The Class-C VCO is tunable over the frequency band 6.5-7.8 GHz and displaying an average phase noise lower than -127 dBc/Hz @ 1 MHz offset with a power consumption of 18 mW, for a state-of-the-art figure-of-merit of -187 dBc/Hz @ 1 MHz and -191 dBc/Hz @ 10 MHz offsets, respectively.

A new dual −&lt;i&gt;G&lt;/i&gt;&lt;sub&gt;m&lt;/sub&gt; structure with Class-AB operation of low-power low-phase-noise K-band CMOS VCO

A new dual −&lt;i&gt;G&lt;/i&gt;&lt;sub&gt;m&lt;/sub&gt; structure with Class-AB operation of low-power low-phase-noise K-band CMOS VCO

Design of self-bias tail transistor technique for low phase noise CMOS VCO with harmonic suppression using capacitance ground

This paper presents a low phase noise wideband CMOS VCO based on the self-bias tail transistor technique and harmonic suppression using a capacitance ground. This VCO utilizes switching capacitor arrays in which four channels are able to be selected for multi-band application. Moreover, the design of CMOS VCO makes good use of the self-bias tail transistor and capacitance ground filter technique to reduce the phase noise. The MOS varactors are used as fine tuning for wideband operating application. The fully integrated VCO provides excellent performance with high FOM −193dBc/Hz. The bandwidth of the frequency is 1.1GHz and the tuning range is 13.8%. The power dissipation of the core circuit is 8.28mW under a 1.8V supply and phase noise is measured as low as −123.6dBc/Hz at 1MHz offset under 8.5GHz oscillation frequencies. This VCO was made by the TSMC 0.18μm 1P6M CMOS standard process and the chip area is 0.75×0.69 (mm2).

Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band

Flicker noise up-conversion in voltage-biased oscillators can be effectively suppressed by inserting resistances in series to the drain of the transconductor MOSFETs. This solution avoids the degradation of the start-up margin and the adoption of area-demanding resonant filters with proper tuning. This paper presents a detailed theoretical analysis of 1/f noise up-conversion and quantitatively addresses the impact of two major contributions, namely the Groszkowski effect and the loop delay caused by stray capacitances at the drain node of the transistors. A simple flow for the design of an oscillator with suppressed flicker noise up-conversion is presented which is based on first-order closed-form formulas. Finally , theoretical estimates are compared to experimental results on a 65-nm CMOS VCO covering the 3.0–3.6 GHz band.