ABSTRACT Wireless local area network (WLAN) communication technology is widely used in both civilian and commercial fields due to its high transmission rate, good compatibility, and support for simultaneous multidevice connections. WLAN receiver front‐end (RFE) with high dynamic range and high linearity helps improve information transmission distance and speed. Traditional WLAN RFEs are typically implemented using the CMOS process. However, compared with the GaAs pHEMT process, CMOS exhibits several disadvantages, including higher noise figures, lower output power, and increased insertion losses. To achieve better RF performance, this letter proposes a WLAN RFE structure based on the GaAs pHEMT process that eliminates the need for negative voltage. This design achieves better noise figure (NF) and dynamic range without increasing circuit complexity. Measured results show that the WLAN RFE chip using this topology not only supports the four operating modes required for WLAN but also exhibits a lower NF of 0.7 dB and a higher gain of 16 dB in the RX_LNA mode, along with a P1dB of 17 dBm, all within an area of only 1 × 1.05 mm 2 .

In ECG classification applications, binarized convolutional neural networks (bCNNs) show great potential to achieve extremely low power consumption through 1-bit quantization. Existing bCNN approaches typically extract spatial features from the full ECG image without leveraging its sparsity, thereby introducing unnecessary computations and hardware resources. Meanwhile, inter-patient variability of ECG features degrades the classification performance due to accuracy loss caused by the binarization operation. To address these challenges, this paper proposes an energy-efficient ECG classifier based on a bCNN with on-chip learning. A patch-by-patch computation approach is used to reduce both power consumption and memory usage. Instead of processing the entire image, the ECG image is divided into small patches, and only the patches containing valid data are involved in feature extraction. An on-chip learning method is employed to improve classification accuracy among patients by updating the model weights using both the acquired bCNN features and the R-peak interval data. In addition, a reconfigurable convolutional processing element array and a base-2 softmax structure are designed to further reduce the hardware resources. The proposed classifier is verified on an FPGA, achieving a classification accuracy of 97.55% and a specificity of 89.15%. Synthesized using a 55 nm CMOS process, the ECG classifier occupies an area of 0.43 mm${}^{2}$. With a supply voltage of 1.2 V, the classifier consumes an average energy of 0.12 $\mu$J per classification and 0.09 $\mu$J per on-chip learning, making it suitable for wearable ECG classification application.

Abstract In this work a low-power analog integrated image edge detector employing squarer and theshold circuits is presented. A hardware-friendly approximation of the Robert’s Cross operator serves as the foundation for the operation of this architecture. The system-level implementation can be easily adapted to accommodate different image resolutions. As a result, larger integrated smart sensor systems can use the proposed architecture as a building block. Four medium-resolution images were used to test the edge detector, which consumed only 24 nW per pixel while achieving an average Peak Signal-to-Noise Ratio (PSNR) of 27.3 dB and a Structural Similarity Index Metric (SSIM) of 0.82. An interesting characteristic is the high computational speed equal to 320,000 frames per second. Monte Carlo simulations, incorporating process variations and mismatches, along with corner-case analysis, are conducted to verify the robustness of the proposed edge detector. A comparative analysis of post-layout simulation results with an equivalent software-based edge detector and existing literature validates the accuracy and reliable operation of the proposed design. Both schematic and post-layout simulations are carried out using the Cadence IC suite with a 90 nm CMOS process.

This paper addresses the core conflict between long-range communication and ultra-low power requirements in sensing nodes for Wireless Sensor Networks (WSNs) by proposing a wake-up receiver (WuRx) design featuring nanowatt-level power consumption and high sensitivity. Conventional architectures are plagued by low energy efficiency, poor demodulation reliability, and insufficient clock synchronization accuracy, which hinders their practical application in real-world scenarios like WSNs. The proposed design employs an event-triggered mechanism, where a continuously operating, low-power WuRx monitors the channel and activates the main system only after validating a legitimate command, thereby significantly reducing standby power. At the system design level, a key innovation is direct conjugate matching between the antenna and a multi-stage rectifier, replacing the traditional 50 Ohm interface, which substantially improves energy transmission efficiency. Furthermore, a mean-detection demodulation circuit is introduced to dynamically generate an adaptive reference level, effectively overcoming the challenge of discriminating shallow modulation caused by signal saturation in the near-field region. At the baseband processing level, a configurable fault-tolerant correlator logic and a data-edge-triggered clock synchronization circuit are designed, combined with oversampling techniques to suppress clock drift and enhance the reliability of long data packet reception. Fabricated in a TSMC 0.18 µm CMOS process, the receiver features an ultra-low power consumption of 305 nW at 0.5 V and a high sensitivity of −47 dBm, enabling a communication range of up to 400 m in the 920–925 MHz band. Through synergistic innovation at both the circuit and system levels, this research provides a high-efficiency, high-reliability wake-up solution for long-range WSN nodes, effectively promoting the large-scale application of WSN technology in practical deployments.

Abstract In this paper, an ultra-high-speed, low-loss gate driver circuit using a CMOS-type class-D oscillator and a Switched Capacitor (SC) converter directly driven by it are proposed and demonstrated. Conventional buffer drivers suffer from large power losses, making it difficult to operate SC converters in the several hundreds of MHz range. The proposed driver circuit achieves low-loss operation in this frequency range by employing an inductor-based constant-current gate drive that self-oscillates utilizing CMOS-type class-D oscillator. This approach enables a significant reduction of the flying capacitor value in the SC converter. The proposed oscillator driver and SC converter are implemented using only 1.0V transistors in a 65nm CMOS process. The oscillator inductors and flying capacitors are all integrated on-chip. The measurement results show that the SC converter can be driven at 480MHz with a driver power loss of 61mW, achieving a maximum efficiency of 60.2% at an output current of 350mA.

This paper introduces the design of a reference voltage buffer (RVB) for pipelined analog-to-digital converters (ADCs) in a 180 nm CMOS process with a 1.8 V supply voltage. The loop stability of the proposed RVB is verified by the theoretical calculations. The driving capability of the proposed RVB is demonstrated by its large driving current, and the transient response simulation results reveal its impressive speed and precision in the reference voltage settling process. Moreover, the power supply rejection ratio (PSRR) performance indicates that the proposed RVB is insensitive to the variation in power supply voltage, meeting the application requirements for high-speed and high-precision pipelined ADCs.

This paper reports the results of a system-level total ionizing dose (TID) effect simulation study on a SMIC 130 nm LEON2 processor. Firstly, the device-level simulations of the 130 nm NMOS transistors are performed using the Sentaurus TCAD software to analyze the effects of a bias condition, channel width, and irradiation dose on a TID-induced leakage current. Based on the TCAD simulation results, a Verilog-A-based compact model is developed for NMOS transistors to describe the TID-induced leakage current, and it is then embedded into target nodes of the SPICE netlist for the LEON2 processor, enabling system-level TID simulations. The simulation results reveal the processor’s failure threshold and corresponding failure mechanism; meanwhile, the increase in the power supply current with the irradiation dose is also observed. The research reported in this paper can provide beneficial guidance for radiation performance evaluation and radiation hardening by design (RHBD) in 130 nm bulk CMOS processors.

The dramatic growth in the emerging optical applications, including Lidar, short-range optical communication, and optical integrated sensing and communication (ISAC) calls for high-bandwidth transimpedance amplifiers (TIA) with low noise and low power in advanced CMOS technology nodes. To address the issues of existing TIA design, including the conventional RGC structure and the dual-feedback regulated cascode (RGC) TIA, design with complex feedback paths, i.e., limited bandwidth, extra noise, and high power consumption for enough bandwidth, this paper presents a novel TIA with the following key contributions. A novel RGC structure with cascode-feedback is proposed to increase feedback gain, thereby extending bandwidth and reducing noise. Design strategy of the proposed RGC TIA in a low-power advanced CMOS process is carried out to exploit weak inversion operation to achieve better power efficiency. Frequency response and noise analysis are also conducted to achieve target bandwidth and noise performance. The proposed TIA is designed and simulated in 40 nm CMOS with a target PD capacitance of 0.15 pF, achieving a −3 dB bandwidth of 9.2 GHz and a transimpedance gain of 71 dBΩ. The average input-referred noise current spectral density is 18.3 pA/. Operating at 1.2 V, the core circuits consume only 6.6 mW, excluding the output buffer. Compared with prior RGC TIA designs, the proposed TIA achieves a 7.4×~243× enhancement in figure of merit.

Al<sub>1–<i>x</i></sub>Sc<sub><i>x</i></sub>N, as a new generation of wurtzite-type ferroelectric material, has become a focal point in ferroelectric materials research in recent years, due to its high remnant polarization, nearly ideal rectangular polarization-electric field hysteresis loops, inherent compatibility with back-end-of-line (BEOL) CMOS processes, and stable ferroelectric phase structure. The systematic and in-depth studies on the preparation, property modulation, and device applications of this material have been conducted. This paper provides a comprehensive review of the research progress of Al<sub>1–<i>x</i></sub>Sc<sub><i>x</i></sub>N ferroelectric thin films. Regarding the factors influencing ferroelectric properties, it emphasizes the regulatory effects of Sc doping concentration on phase transition and coercive field, explores the influences of substrate (such as Si and Al<sub>2</sub>O<sub>3</sub>) and bottom electrode (such as Pt, Mo, and HfN<sub>0.4</sub>) on thin-film orientation, stress, and interface quality, and systematically summarizes the influences of deposition conditions, film thickness, testing frequency, and temperature on ferroelectric performance. At the level of physical mechanisms governing polarization switching, this review elaborates on the domain structure, domain wall motion dynamics, nucleation sites and growth mechanisms in the Al<sub>1–<i>x</i></sub>Sc<sub><i>x</i></sub>N switching process, revealing its microscopic response behavior under external electric fields and the mechanisms underlying fatigue failure. In terms of application prospects, Al<sub>1–<i>x</i></sub>Sc<sub><i>x</i></sub>N thin films show significant advantages in memory devices such as ferroelectric random-access memory (FeRAM), ferroelectric field-effect transistors (FeFETs), and ferroelectric tunnel junctions (FTJs). Their high performance and integration compatibility provide strong technical support for developing next-generation, high-density, low-power ferroelectric memory and nanoelectronic devices.

A Switching-Inductor Hybrid Step-Down DC-DC Converter for Battery Charger Applications Implemented in CMOS Process

Measurement and Analysis of Multistate Ferroelectric Transistors in 28 nm CMOS Process

Next-generation pixel-based read-out ASICs for high-energy physicsexperiments face demanding performance and integration requirements. A flexible,pixel-level simulation framework is essential to design, validate, and optimizethe readout architecture and its building blocks. This contribution presents aSystemVerilog-UVM verification framework developed for the IGNITE project, a 28 nm CMOS pixel readout and processing ASIC designed for high-intensity4D-tracking with spatial resolution <10 μm and timing resolution <50 ps inharsh radiation environments. The verification environment comprises modularverification components for configuration, parameterized random and clusteredhit generation, and I/O monitoring, supporting realistic stimulus andcoverage-driven verification. The framework enables scalable and reusableverification of pixel architectures, achieving high coverage and reduceddevelopment effort across multiple ASIC generations.

This paper presents pixcore, which is a 32-bit RISC-V microprocessor with an integrated pixel matrix management coprocessor. The integration of the coproccessor with a RISC-V core enabled the management of the pixel matrix using custom RISC-V instructions, allowing for high performance and flexibility. The presented solution was designed in a 16 nm FinFET CMOS process, and the results of the chip implementation were used in post-layout simulations. The conducted simulations confirmed that the developed coproccessor can be successfully used for managing and readout of the hybrid pixel detector. A comparison was made between the proposed solution and the microprocessor-based system that utilized a dedicated peripheral device for the purpose of controlling the pixel matrix. The comparison indicates a reduction in the execution time of the selected algorithms by a factor of 14, measured in terms of clock cycles.

The generally accepted method for manufacturing power ICs is BCD. The key element in BCD technology is the double-diffused MOSFET. Integrating the double-diffused MOSFET into the submicron SOI CMOS process is a pressing challenge in the development of BCD technology. Solving the problem of integrating the double-diffused MOSFET will expand the product range with minimal costs while maintaining the key advantages of mass-produced submicron SOI CMOS ICs. The goal was to develop a manufacturing process for n- and p-channel LDMOS transistors based on the basic 0.35 µm SOI CMOS process with a 200 nm device layer thickness and a 200 nm buried oxide thickness. The result was a process for producing high-voltage double-diffused MOSFET transistors. The technological features of high-voltage MOSFET transistors based on a SOI structure are discussed. The operating mode of these high-voltage MOSFETs is an operating drain voltage of 12 V and an off-state breakdown voltage of over 30 V. The feasibility of manufacturing such transistors is experimentally confirmed. High-voltage transistors manufactured using a 0.35 µm SOI CMOS process are studied. The optimal geometric parameters of the key regions are determined. The developed process enables the production of low-voltage integrated circuits with a supply voltage of 3.3 V and power integrated circuits with a supply voltage of up to 12 V. A BCD process based on the solutions applied in this work will be developed in the future.

This work presents a continuous-time 60 Hz notch filter designed for ultra-low-power bio-sensing applications, featuring a transconductor (OTA) with an output current-splitting technique and a minimum transconductance of 4.86 nA/V. Implemented in the TSMC 0.18 μm CMOS process, the filter achieves a power consumption of only 44 nW, making it highly suitable for portable and implantable biomedical devices. The proposed topology addresses critical challenges in bio-sensing, including power-line interference suppression, low total harmonic distortion (THD), and compact design. Post-layout simulations demonstrate a notch depth of −33.37 dB (−77 dB for a 4th-order implementation) at 60.21 Hz, a bandwidth of 43.2 Hz, and an exceptionally low input-referred noise (IRN) of 0.413 μV/√Hz. The filter’s robust performance across process variations and its ability to preserve signal integrity in electrocardiographic (ECG) applications highlight its potential for use in analog front ends of bio-sensing systems. This work advances the state of the art in low-power, high-performance notch filters, offering a balanced solution for noise-sensitive biomedical signal processing.

This letter reports a low-voltage and low-power voltage-controlled oscillator (VCO). An inductance-capacitance (LC) NMOS cross-coupled VCO uses a degenerated source inductor for phase noise improvement. The switching FET operates in a subthreshold region for low-power operation. The VCO uses a 3-turn two-lobe 8-shaped inductor for interference noise suppression and a center-tapped coupled degenerated-source inductor to dynamically boost the tank Q factor. The two inductors are configured as a low-coupling coefficient transformer. The 8-shaped inductor consists of two 3-turn O-shaped inductors in a twisted series. The die area of the current-biased VCO fabricated in the TSMC 0.18μm CMOS process is 0.8795 ×0.738 mm2. The measured oscillation frequency of the VCO is 2.81 GHz, and the phase noise at 1 MHz offset is - 114.7 dBc/Hz. and the figure of merit (FOM) is -189.32 dBc/Hz at the power consumption of 0.272 mW.

This article presents the design of a perovskite photovoltaic (PV)-based power management system, which uses a power converter (a four-stage bootstrap charge pump) to boost the output of the solar cell and supply selectable rectified power rails to CMOS image sensor circuit blocks. A perovskite photovoltaic, also known as a perovskite solar cell (PSC) was fabricated in the laboratory. The PSC has an open-circuit voltage of 1.14 V, short-circuit current of 1.24 mA, maximum power of 0.88 mW, and a current density of 20.68 mA/cm2 at 62% fill factor. These measured forward scan parameters were closely reproduced with a solar cell simulation model. In a Cadence simulation that used 180 nm CMOS process, the power converter efficiently boosts the maximum output voltage of the PSC from 0.85 V to a rectified 3.7 V. Stage modulation and level shifting enable selectable output rails in the 1.2–3.3 V range to supply the image sensor circuit blocks. Keeping the output capacitance of the power converter much larger than the flying capacitance reduces the ripple voltage to approximately 73 µV, much smaller than the typical 1 mV in several other literatures. Through simulation, this work demonstrates the concept of directly using PSC (to be implemented on an outer ‘packaging’, not on a die) to supply CMOS image sensor power rails, in the same sense as in wearable devices and other consumer devices. This work highlights a path toward self-powered image sensors with improved conversion efficiency, compactness, and adaptability in low-light and variable operating environments.

Convolutional neural networks (CNNs) are increasingly being deployed on edge devices, where stringent power and latency constraints require highly efficient hardware implementations. This paper introduces an energy-efficient analog computing architecture designed for binary classification, with an emphasis on system-level integration and algorithm-hardware co-design. The system integrates a current-mode active pixel sensor (APS) with analog computing units — multiply-accumulate (MAC), ReLU and max pooling — into a continuous analog-domain processing pipeline. This integrated approach minimizes data conversion, requiring only a single analog-to-digital conversion for the final classification result, thereby significantly improving energy efficiency. Furthermore, a comprehensive analysis of hardware nonidealities is conducted from multiple perspectives, and an algorithm-hardware co-design method is proposed to mitigate degradation in inference accuracy. The prototype chip, fabricated in a 55[Formula: see text]nm CMOS process, consumes only 191.5[Formula: see text] [Formula: see text]W and delivers 3 TOPS/W. Supported by the co-design method, it achieves an accuracy of 97.2% on the LFW dataset. This work demonstrates a practical, fully integrated analog solution for low-power binary classification in intelligent sensing systems.

Post-quantum cryptography (PQC) is rapidly being standardized, with key primitives such as Key Encapsulation Mechanisms (KEMs) and Digital Signature Algorithms (DSAs) moving into practical applications. While initial research focused on pure software and hardware implementations, the focus is shifting toward flexible, high-efficiency solutions suitable for widespread deployment. A system-on-chip is a viable option with the ability to coordinate between hardware and software flexibly. However, the main drawback of this system is the latency in exchanging data during computation. Currently, most SoCs are implemented on FPGAs, and there is a lack of SoCs realized on ASICs. This paper introduces a complete RISC-V SoC design in an ASIC for Module Lattice-based KEM. Our system features a RISC-V processor tightly integrated with a high-efficiency Number Theoretic Transform (NTT) accelerator. This accelerator leverages custom instructions to accelerate cryptographic operations. Our research has achieved the following results: (1) The accelerator provides a speedup of up to 14.51× for NTT and 16.75× for inverse NTT operations compared to other RISC-V platforms; (2) This leads to end-to-end performance improvements for ML-KEM of up to 56.5% for security level I, 50.9% for level III, and 45.4% for level V; (3) The ASIC design is fabricated using a 180 nm CMOS process at a maximum operating frequency of 118 MHz with an area overhead of 8.7%. The chip achieved a minimum power consumption of 5.913 μW at 10 kHz and 0.9 V of supply voltage.

This paper presents a passive noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) that features a kickback noise-canceling comparator. In previous architectures, conventional comparators achieved relative gain coefficients by sizing the input transistors, which introduced significant kickback noise. This kickback noise limited the achievable resolution of ADCs by degrading their linearity. The proposed architecture addresses this limitation by incorporating two key techniques into the comparator design. First, a cascade stage is integrated to effectively shield the sensitive input nodes from large voltage swings at the main latch nodes during regeneration. Second, a kickback noise-canceling scheme employs cross-coupled transistors to deliver a precisely controlled amount of canceling charge to the opposite differential input, thus neutralizing the kickback noise. The ADC was designed using a 28-nm CMOS process. Post-layout simulations validated that the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) in a 0.5-MHz bandwidth (BW) at an oversampling ratio (OSR) of 8 are 79.18 dB and 90.69 dB, respectively. This architecture achieves a low power consumption of 213.63 µW at a supply voltage of 1.0 V, resulting in a Schreier Figure of Merit (FoM) of 172.87 dB. This work demonstrates that our kickback noise-canceling technique is an effective approach for developing high-performance, power-efficient NS-SAR ADCs. It represents a significant advancement in the pursuit of better and more efficient technology.