ABSTRACT A power amplifier (PA) with Darlington cell in 0.18‐μm CMOS technology is reported in this letter. By adopting the Darlington cell with cascode structure, the proposed CMOS PA improves the performance. The proposed CMOS PA owns the two‐stage cascade topologies formed by the common source (CS) and common gate (CG) cascode configurations. For the proposed CMOS PA, the first stage is the Darlington cascode topology, and the second stage is the cascode topology, respectively. The proposed CMOS PA at 3.5 GHz has the measured power gain of 18.13 dB, the measured saturated power ( P sat ) of 5.16 dBm, and the measured power added efficiency (PAE) of 8.25%, respectively. The proposed CMOS PA supplied by a 1.8‐V supply dissipates 40.5 mW.

This brief presents a wideband linear CMOS power amplifier (PA) for 5G millimeter wave (mm-wave) applications. In order to improve linearity, this PA adopts an analog pre-distortion (APD) linearizer using an adaptive dual-voltage-path crossing cold-FET pair (ADCCP). The proposed ADCCP is implemented by connecting the drain and gate of differential cold-FET mutually in a crossing manner, which can enhance the equivalent impedance of cold-FET significantly. Moreover, an adaptive bias circuit (ABC) with dual-voltage-path is applied to control V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> of ADCCP to transform the transistor from the saturation region to the turn-off region, which can further increase the equivalent impedance of the cold-FET to enhance linearity. In addition, input and interstage transformers are meticulously designed using gain shaping technique to ensure wideband performance. The implemented PA achieves a 3-dB bandwidth of 18.3-38.3 GHz, with the peak gain of 20.8 dB, peak saturated output power (P<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub>) of 22.7 dBm, and peak power-added efficiency (PAE) of 31.9%. Wideband output power and efficiency performance was achieved with OP<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ≥ 21 dBm, PAE<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> ≥ 22% in 21.5-36.1 GHz (50.7% FBW).

As demand grows for multigigabit data links, high-resolution radar, and precision sensing, operating frequencies are being driven deep into the sub-terahertz (sub-THz) spectrum, where the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i>- and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</i>-bands (110–220 GHz) offer immense bandwidth (BW). However, operating at these frequencies with CMOS silicon technologies reveals several fundamental physical limitations, including limited breakdown voltage, low intrinsic gain, dominant parasitics, and significant passive losses. This article brings together different design methodologies that push these limits and expand the achievable power, gain, and BW of CMOS power amplifiers (PAs) operating near <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${f}_{\max}$</tex-math></inline-formula> The first approach revisits the concept of transistor stacking from a large-signal modeling perspective. By analytically accounting for all parasitic elements and the intrinsic delay of each device, a systematic framework is developed to determine the optimum input, output, and gate impedances for every transistor in the stack. A 45-nm SOI prototype that combines multiple stacked stages through a low-loss 4:1 combiner demonstrates 18.7 dBm saturated output power and 4.8% power-added efficiency (PAE) at 200 GHz, an example of how careful modeling can turn CMOS voltage limits into a scalable power generation strategy. The second methodology focuses on gain enhancement through embedding. At sub-THz frequencies, where matching-network losses can rival transistor gain, a passive feedback network is introduced and tuned on a “gain plane” that maps equi-gain and equi-load-conductance contours. This graphical design tool allows the simultaneous optimization of gain and output power. Implemented in a 65-nm CMOS 2 × 8 cell amplifier, the embedded approach achieves 19.5 dB gain and 9.4 dBm saturated power at 200 GHz, showing how modest feedback can recover otherwise-lost gain and extend usable output levels. The third technique, reverse-feedback amplification, breaks the BW barrier. By introducing a controlled amount of negative resistance into each amplifier cell, a distributed line is formed that supports constructive wave propagation and continuous power addition without interstage matching. Two 45-nm CMOS <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</i>-band amplifiers fabricated using this principle deliver up to 20.4 dB gain and 3.8% PAE across a 156- to 194-GHz 3-dB BW. Together, these methodologies, large-signal stacking, gain plane embedding, and distributed reverse feedback, demonstrate how thoughtful circuit architectures can overcome fundamental device limits to achieve high-power, high-efficiency, and broadband amplification in standard CMOS.

ABSTRACT This paper presents a W‐band two‐way four‐stage power amplifier (PA) implemented in 28‐nm CMOS technology, featuring a novel weighted distributed enhanced group linearizer (WDE‐GL). The proposed WDE‐GL architecture incorporates three stages, each operating at a different power level along the signal path. This design enables compensation with different weights for each linearizer stage, optimizing the linear performance, particularly for high‐gain RF PAs. Each WDE‐GL stage employs an introduced transformer phase‐delayed reverse body‐biasing technique to reduce its insertion loss and improve its compensation slope, achieving an optimal trade‐off between linearity, efficiency, and gain. Furthermore, this approach supports stage‐specific activation, providing flexibility for high‐accuracy and eco‐friendly modes, making it well‐suited for automotive radar systems and electric vehicle applications. The implemented PA achieves, at 77 GHz, a maximum power added efficiency (PAE) of 11.7%, an output power at the 1‐dB compression point (OP 1dB ) of 13.8 dBm, and a saturated output power ( P sat ) of 15.7 dBm, utilizing a core area of 0.11 mm 2 . The WDE‐GL significantly enhances the linear behavior of the PA, reducing the amplitude‐to‐amplitude, amplitude‐to‐phase, and intermodulation distortions. It also increases the OP 1dB and its PAE by 3.4 dB and 4.5%, respectively. These improvements represent enhancements of 120% and 83% compared with the deactivated WDE‐GL case, marking the best reported performance for W‐band PAs.

In this study, we present the design and analysis of a stacked inverter-based millimeter-wave (mmWave) power amplifier (PA) in 90 nm CMOS-targeting wideband Q-band operation. The PA employs two PMOS and two NMOS devices in a fully stacked inverter topology to distribute device stress, remove the need for an RF choke, and increase effective transconductance while preserving compact layout. A resistor ladder biases the stack near VDD/4 per device, and capacitive division steers intermediate-node swings to enable class-E-like voltage shaping at the output. Closed-form models are developed for gain, output power, drain efficiency/PAE, and linearity, alongside a small-signal stacked-ladder formulation that quantifies stress sharing and the impedance presented to the matching networks; L/T network synthesis relations are provided to co-optimize bandwidth and insertion loss. Post-layout simulation in 90 nm CMOS shows |S21| = 10 dB at 39.84 GHz with 3 dB bandwidth from 36.8 to 42.4 GHz, peak PAE of 18.38% near 41 GHz, and saturated output power Psat=8.67 dBm at VDD=4 V, with S11&lt;−15 dB and reverse isolation ≈−16 dB. The layout occupies 1.6×1.6 mm2 and draws 31.08 mW. Robustness is validated via a 200-run Monte Carlo showing tight clustering of Psat and PAE, sensitivity sweeps identifying sizing/tolerance trade-offs (±10% devices/passives), and EM co-simulation of on-chip passives indicating only minor loss/shift relative to schematic while preserving the target bandwidth and efficiency. The results demonstrate a balanced gain–efficiency–power trade-off with layout-aware resilience, positioning stacked-inverter CMOS PAs as a power- and area-efficient solution for mmWave front-ends.

A compact 8–15 GHz Doherty power amplifier (DPA) is proposed and fabricated in 22 nm FD-SOI CMOS. The proposed DPA relies on a quadrature-hybrid splitter and combiner to replace the bulky λ/4 impedance inverters at the input and the output of the conventional DPA enabling load modulation over a large fractional bandwidth (FBW = 61%) with efficient and compact integration. The proposed DPA achieves a peak gain of 19.6 dB; ≥17 dB across 8–15 GHz, 18 dBm P1dB, 19.5 dBm Psat, and a peak PAE of 21% at 10 GHz, while sustaining 17% PAE at 6 dB back-off. The proposed DPA enables a modulation BW up to 200 MHz for a 256-QAM single carrier (SC) signal with a peak-to-average power ratio (PAPR) of 6 dB. Under this setting, the average output power (Pavg) is measured at 12.5 dBm with an RMS error vector magnitude (EVM) of −24.1 dB and an average PAE of 15%. Within the scope of CMOS power amplifiers in 22 nm FD-SOI, we found no published example that jointly demonstrates 8–15 GHz coverage and sustained PAE at 6 dB back-off using a quadrature hybrid.

In this study, we investigate linearity enhancement of a differential cascode CMOS power amplifier (PA). First, the variation of parasitic capacitance in the common-source (CS) transistor, which directly affects IMD3 and AM-PM distortion, is analyzed as a function of input power. Then, second-harmonic generation at the gate node of the common-gate (CG) transistors in the differential structure is examined. It is shown that these second-harmonic components alter the parasitic capacitance of the CS transistors, ultimately degrading the linearity of the PA. Based on this observation, a CMOS PA is proposed that improves linearity by incorporating a second-harmonic filter at the gate node of the CG transistors. The proposed PA is fabricated using a 180-nm RFCMOS process. Measurement results at 2.42 GHz with an 802.11n 64-QAM 20 MHz WLAN modulated signal demonstrate an output power of 21.4 dBm and a power-added efficiency (PAE) of 28.6% at an EVM level of 3.98% .

This paper presents a 28-GHz PA fabricated in the TSMC 90-nm CMOS process for 5G wireless communication phased-array transmitters. The proposed PA incorporates adaptive bias and phase compensation techniques to effectively mitigate AM-AM and AM-PM distortions, achieving high linearity and efficiency. The design features an envelope detector for dynamic bias adjustment, enhancing transconductance to reduce AM-AM distortion. Furthermore, a varactor-based phase correction mechanism is implemented to minimize AM-PM distortion. This work improves both gain and phase control networks, resulting in significant improvements in key performance metrics, including OP1dB, PAEP1dB, and maximum phase distortion before P1dB. The proposed PA achieves an OP1dB of 14.4 dBm, a PAEP1dB of 33.6%, and a maximum AM-PM distortion of 1.5°, demonstrating exceptional performance and scalability for phased-array applications in next-generation millimeter-wave systems.

A two-way K/Ka-band series-Doherty PA (SDPA) with a distributed impedance inverting network (IIN) for millimeter wave applications is presented in this article. The proposed distributed IIN contributes to achieve wideband linear and power back-off (PBO) efficiency enhancement. Implemented in 65 nm bulk CMOS technology, this work realizes a measured 3 dB bandwidth of 15.5 GHz with 21.2 dB peak small-signal gain at 34.2 GHz. Under 1-V power supply, it achieves OP1dB over 13.4 dBm and P sat over 16 dBm between 21 to 30 GHz. The measured maximum P sat, OP1dB, peak/OP1dB/6dBPBO PAE results are 17.5, 14.7 dBm, and 28.2%/23.2%/13.2%. Without digital pre-distortion (DPD) and equalization, EVMs are lower than −25.2 dB for 200 MHz 64-QAM signals. Besides, this work achieves −33.35, −23.52, and −20 dB EVMs for 100 MHz 256-QAM, 600 MHz 64-QAM and 2 GHz 16-QAM signals at 27 GHz without DPD and equalization.

6G communications through sub-Terahertz CMOS power amplifiers: Design challenges and trends

This article presents a dual-mode, dual-band power amplifier (PA) capable of covering both the fifth-generation (5G) FR1 and FR2 bands for 5G user equipment driver applications. The common-mode (CM) path, often overlooked in a typical differential-mode (DM) CMOS PA, is analyzed and utilized as an alternative path to cover a second frequency band. A universal topology is proposed for the utilization of both DM and CM in PA and other RF circuits. By assigning the millimeter-wave (mm-Wave) and sub-7 GHz bands to DM and CM paths, respectively, this PA achieves coverage of both 3.5 and 27 GHz bands with only one amplifying stage and consequently a compact layout. On the DM path, the proposed PA achieves a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{1{\text{dB}}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm {PAE}}_{1{\text {dB}}}$ </tex-math></inline-formula> of 18.1 dBm and 32.4% at 24 GHz, while on the CM path, the corresponding performance is 15.3 dBm and 35.5% at 3.7 GHz. The proposed PA exhibits an adjacent channel leakage ratio (ACLR) of −25.9 dBc, an average power-added efficiency (PAE) of 17%, and an average output power of 12.4 dBm at −24.7 dB EVMRMS with a 64 QAM 200 MSym/s modulation signal at 26 GHz in DM. Similarly, with 256 QAM 50 MSym/s modulation at 3.6 GHz in CM, the PA demonstrates −35.6 dBc ACLR, 22.5% average PAE, and 10.7 dBm average power at −31.1 dB EVMRMS. Furthermore, measurements with two carriers at 24 and 3.7 GHz indicate that the PA has the potential for concurrent operation in both modes. The PA is fabricated in a 65 nm CMOS process with a core area of 0.32 mm2.

The advent of CMOS power amplifiers has enabled compact and cost-effective solutions for RF applications. Among the available options, switching amplifiers are the most competitive due to their superior efficiency. In this paper, we present the design of a fully integrated 130 nm CMOS class-E RF power amplifier optimized for 2.4 GHz ISM band operations that is compliant with the Bluetooth Low Energy (BLE) standard. The amplifier is based on a cascode configuration with charging acceleration capacitance and a combination of standard and high-voltage (HV) MOSFETs, ensuring optimal performance while maintaining device reliability. To identify the best configuration for the proposed circuit, we first provide an overview of basic class-E amplifier operations and critically review optimization techniques proposed in the scientific literature. This review is complemented by a numerical analysis of the potential advantages of using a combined standard-HV MOSFET structure. Post-layout simulations with parasitic parameter extraction demonstrated that the amplifier achieves 40.85% Power Added Efficiency and 20.52 dBm output power.

ABSTRACTThis paper proposes a novel technique based fully integrated 13th‐order derivative CMOS impulse‐radio ultrawideband (IR‐UWB) transmitter with wide range of adaptive data rates for wireless capsule endoscopy systems (WCE). The proposed IR‐UWB transmitter involves BPSK modulator‐integrated RF power amplifier (PA) approach for WCE in first time as per author's best knowledge. The CMOS BPSK modulator with resonator technique generates 13th‐order Modulated Gaussian pulse without the pulse generator. It has a peak‐to‐peak value of 25 mV and PSD level of −72.60 dBm/MHz, data rate variability from 500 Mbps to 5 Gbps. The BPSK modulator with resonator is designed by time constant analysis in first time. In addition, a proposed CMOS PA is designed using four stacked transistors, which achieves a high output power as well as high efficiency for entire frequency band of operation from 3 to 16 GHz and wide impedance matching. The PA achieved an excellent gain of 16.55 dB with gain ripple of 0.25 dB only. Moreover, the PA achieved the saturated output power of 18.2 to 19.3 dBm with OP1dB of 15.96 to 16.72 dBm across entire bandwidth. Without violating FCC guidelines, PA strengths both peak‐to‐peak values, and PSD level of BPSK modulated signal to 80 mV and −46.42 dBm/MHz. An IR‐UWB transmitter has been implemented and fabricated using 65‐nm CMOS Process, which consumes of only 160 fJ/pulse for generating Gaussian pulses order ranging from third‐order to more than 13th‐order at various data rates.

This article presents an analog linearizer that linearizes multiple power amplifiers (PAs) by configuring target predistortion curves, including tunable slopes for both amplitude modulation (AM)–AM and AM-phase modulation (PM) curves, as well as adjustable critical output power points for each curve. Moreover, general memoryless nonlinear models for analog linearizers are proposed, and a boundary parameter-searching approach based on the error vector magnitude (EVM) gradient optimization is introduced to determine the optimal maximum expansion of gain and phase. Prototype validation involves linearization of both a GaN PA and a CMOS PA. The proposed linearizer is implemented in a 65-nm CMOS process, employing nonlinear inductive techniques and diode-connected methods for continuous adjustments in phase and gain expansion. Matching strategies are discussed to increase the corresponding expansion range while decoupling AM-AM and AM-PM. Gain adjustments are determined to control the critical output power points. The experiment shows that the designed linearizer achieves a gain expansion of over 3.5 dB and a phase expansion exceeding 25° at 35 GHz while consuming approximately 74.2 mW. Modulated signal measurements in four scenarios demonstrate significant EVM improvements. Specifically, for the GaN PA with a signal of 256-quadrature amplitude modulation (QAM) and a 400-MHz bandwidth, EVM can be reduced from 6.6% to 2.9% at 31.3 dBm. For the CMOS PA under the same conditions, EVM can be improved from 6% to 2.8%. Overall, this article provides a universal solution for low-cost linearization of various PAs.

This letter presents a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i>-band CMOS wideband power amplifier (PA). The neutralizing capacitor and magnetically coupled resonator (MCR) matching network are designed and implemented to expand the operating bandwidth. In addition, the synchronous gate signal feeding (SGSF) transistor and the multistage staggering (MS) scheme-based high-coupling coefficient (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K_{\text {m}}$</tex-math> </inline-formula>) transformer are analyzed and utilized for structuring all the amplification cells to further expand the 1-dB operation bandwidth. Fabricated in 40-nm CMOS process, the PA chip operates at 160 GHz with 31-GHz (19.8%) 1-dB bandwidth and a peak <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> of 15.5 dB. The maximum saturated output power (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\text {SAT}}$</tex-math> </inline-formula>) and the peak power-added efficiency (PAE) are 10.3 dBm and 9.4%, respectively. The circuit occupies 0.022-mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area only, obtaining a high power density of 487 mW/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.

A low-power strategy that can manage analogue, digital, and RF functionalities on a similar chip is crucial for wireless systems. Various difficulties restrict the widespread adoption of CMOS power amplifiers despite the fact that they provide highly integrated, low-cost wireless communication. Some of the main issues with CMOS power amplifiers include non-linearity, low breakdown voltage, a lack of high-voltage capacitors, and incorrect RF models. The RF signal is amplified without distortions using a linear power amplifier (LPA), which is less effective whenever driven by constant voltage. In order to significantly enhance the effectiveness of the power amplifiers, three frequently utilised techniques—Doherty, envelope elimination and restoration (EER), and envelope tracking (ET) techniques are reviewed in this work. Results point towards ET approach as the one that is ideally suited for future mobile communication systems. The essential component of ET systems, the envelope tracking power source, is what determines how effectively the system functions. It also lists the benefits of FinFET technology over CMOS and looks at three well-liked techniques for increasing power amplifier efficiency. Considering the advent of mobile communications systems, the frequency band and peak-to-average power ratio (PAPR) are quickly growing, posing significant design issues. FinFET as an alternative may considerably reduce the chip area.

A 3.5 GHz CMOS power amplifier (PA) designed for 5G applications is presented in this study, utilizing the 0.18 µm RF CMOS process technology. The circuit architecture comprises two stages: the first stage employs a cascode topology with a negative voltage applied to the transistor body technique to achieve sufficient gain and minimize current, thereby reducing power consumption. In the second stage, to ensure high efficiency, a class-E amplifier is being used. Measurement results indicate a power gain (S21) of 17.2 dB, a power-added efficiency (PAE) of 45.6% and a saturated power (Psat) of 8.5 dBm, obtained at 3.5 GHz. These findings validate the suitability of the proposed design at low-band frequency for 5G applications. The chip area for the proposed design is 2.45 mm². The discrepancy between simulation and measurement is due to the parasitic in the layout design.

This paper presents a dual-band fully integrated high linearity CMOS power amplifier (PA). The PA employs a reconfigurable transformer in the input matching network to achieve low reflection coefficient across both bands, demonstrating significant flexibility in the design of dual-band power amplifiers with high output powers. Additionally, a detailed design methodology for the dual-band matching network is introduced. By utilizing this methodology, the PA has been designed using 55 nm CMOS technology. For continuous-wave operation, the PA achieves a saturated power (Psat) of 28.03 dBm and 27.5–28.2 dBm, with power-added efficiency (PAE) of 33.2% and 24.6–31.1%, in the 2.4 GHz and 5 GHz WLAN bands, respectively. Concurrently, the PA power cells, which employ multi-gate transistor (MGTR) technology, achieve an intermodulation distortion (IMD3) of below 30 dBc at an output power of 15 dBm in both the 2.4 GHz and 5 GHz WLAN bands. The proposed PA outperforms other dual-band or multi-band PAs in terms of output power and exhibits great potential for WLAN applications.

This paper presents a design of class E power amplifier (PA) with integrated active inductor for 5G applications. A high Q-factor active inductor (AI) is proposed utilizing CMOS 0.18-µm technology. A Gyrator-C based is employed to realize an active inductor with a double cascode resistive feedback configuration. The biasing voltage of 1.21 V, current source of 0.5 mA and supply voltage of 2.5 V is used. In order to obtain high efficiency, the proposed AI is implemented in a class E power amplifier by replacing on of the spiral inductors. According to the simulation results, the proposed AI can reach a high Q-factor of 50,000 and an inductance of 2.03 nH at 3.5 GHz. The power added efficiency (PAE) of CMOS class E PA with integrated AI, according to simulation result, is 72 % at 3.5 GHz. The intended PA's PAE was dramatically raised by the class E AI that was built.

This article introduces a novel method for extracting crucial parameters from a fifth-generation (5G) CMOS power amplifier (PA) operating at 24 GHz. The proposed method, micro-genetic algorithm artificial neural network (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-GAANN), presents an innovative synergy between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-GA and ANN, enabling the accurate determination of crucial PA (circuit components) parameters. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-GAANN model has a fixed and robust stimulation function (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${F} {_{\text {SF}}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} {_{\text {SF}}}$ </tex-math></inline-formula>). ANNs are trained to approximate the parameter extraction process based on input-output data generated from the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-GA. The proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-GA incorporates the arithmetic crossover and nonuniform mutation; thus, several parameters of the ANN network are tweaked. Moreover, ANN parameters are enhanced by using <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-GA to achieve an optimal PA design in a shorter period of time. To verify the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-GAANN, we have also compared the training time with particle swarm optimization (PSO) employed in ANN, i.e., PSOANN. Besides, a derivative superposition (DS) linearization technique is used in the PA circuit, along with input load splits (I-LSs) to solve the low input impedance problem of conventional DS. To design a PA, the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-GAANN outperforms the traditional feedforward artificial neural networks (TFFANN). Using <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-GAANN, the PA’s simulated S21 is 25 dB, while the measured S21 is 21.2 dB. With traditional TFFANN, we observe a simulated gain of 24.1 dB for the PA. We achieved a simulated gain of 23.2 dB of the PA without using ANNs. The measured results of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P {_{\text {sat}}}$ </tex-math></inline-formula> and PAE of the PA with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>-GAANN are 9.8 dBm and 32.1%, respectively. Also, a measured PA achieves a high third-order-input-intercept point (IIP3) of 14.1 dBm. The core chip area of the PA is 0.35 mm2.