CMOS Low Noise Amplifier Research Articles

A differential multi-band CMOS low noise amplifier with noise cancellation and interference rejection

In this paper, a differential multi-band CMOS low noise amplifier (LNA), operated in a wide range from 1350 to 2900 MHz , with input matching device, noise cancellation and interference rejection technology, is proposed. Traditional wideband LNAs have poor performances on interference rejection or image rejection. In this design, a multi-band CMOS LNA with matching device noise cancelling, matching device current reuse and source inductance device reuse technologies is proposed, it can improve noise figure, wideband match and interference rejection. There exists a switch-mode notch filter to enhance the interference rejection performance and it does not need additional inductors. A prototype of proposed multi-band CMOS LNA was designed to work at 1450 – 1490 MHz , 1680 – 1685 MHz and 2635 HMz – 2660 MHz . The simulation results show that the gain is between 18 and 19 dB at L-band application (1450–1685MHz) and between 25.8 and 26.1 dB at CMMB Satellite application ( 2635 HMz – 2660 MHz ) , the noise figure is 3.1–3.3 dB, and the third-order intercept point (IIP3) is − 7 dBm . It consumes 27.35 mW under 1.8 V supply voltage in TSMC 0.18- μ m RF CMOS process.

A Design Technique for Power Constrained CMOS Low-Noise Amplifier Dedicated to Wireless Sensor Networks

n wireless sensor network applications, autonomy is a critical feature. So, a new design method under power consumption constraint, dedicated to inductively degenerated Low-Noise Amplifier, is proposed in this article. A detailed analysis of power consumption, gain, noise and linearity performances of this topology is performed. The simulation results using MATLAB show the impact of each MOSFET dimensions into Low-Noise Amplifier performances. Based on these results, a new method to design Low-Noise Amplifier is proposed using an example. A 868-MHz Low-Noise Amplifier is then designed in CMOS 0.35 μm technology to validate our method. Considering the literature, measurement results show good characteristics: 13 dB gain, 1.5 dB Noise Figure with an ultra low-power consumption of 6.7 mW at supply voltage of 2 V.

A low‐power wideband CMOS low‐noise amplifier using current‐reuse technique

AbstractA CMOS low noise amplifier (LNA) for low‐power ultra‐wideband wireless applications is presented. To achieve low power consumption and wide operating bandwidth, the proposed LNA uses a current‐reused technique and a simple high‐pass input matching network. This work is implemented in 0.18‐μm CMOS process technology and shows a 3.1–10.6 GHz bandwidth. With only 1.5 V supply voltage, the LNA can achieve power flat gain of 13.2 dB with input matching of −10.3 dB, the minimum noise figure of 3.33 dB, and input third‐order‐intercept point (IIP3) of −3.3 dBm. The power dissipation is only 9.3 mW. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2077–2080, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24581

Expression of Concern: Numerical Design Optimization Methodology for Wideband and Multi-Band Inductively Degenerated Cascode CMOS Low Noise Amplifiers

In this paper, we develop a systematic design optimization methodology for inductively degenerated cascode CMOS low noise amplifiers (LNA) in fully integrated wideband and multi-band wireless systems. Leveraging an accurate analytical circuit model, we combine global and local numerical optimization techniques in a hierarchical manner to simultaneously determine the fixed and switchable passive component and device parameters in the LNA circuit necessary to meet user-specified performance requirements. To demonstrate the effectiveness of proposed design optimization methodology, we utilize the method to create 3 wideband and 3 multi-band LNA designs that meet a wide-range of impedance matching, noise figure, gain, power dissipation, and linearity requirements. The proposed method provides circuit designers with a fast and effective means for the rapid prototyping and design space exploration of wideband and multi-band inductively degenerated cascode CMOS LNAs.

A 0.18 μm 3.1–4.8 GHz CMOS wideband single to differential LNA for UWB system

AbstractWe have proposed a 3.1–4.8 GHz CMOS wideband single to differential low noise amplifier (LNA) for ultra wideband system. The LNA is fabricated with the 0.18 μm 1P6M standard CMOS process. Measurement of the CMOS LNA was performed using RF probe station. From 3.1 to 4.8 GHz, the wideband LNA exhibits a noise figure of 4.8–5.1 dB, a gain of 12.6–15.3 dB, and an input return loss higher than 10 dB. The input IP3 (IIP3) at 4.1 GHz is −19 dBm, and consumes 19.1 mW of power. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1778–1781, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24441

IEEE Transactions on Antennas and Propagation Announces a Special Issue on Antennas for Next-Generation Radio Telescopes

Topics of interest include multi-pixel approaches based on broadband phased array aperture antennas and phased array feeds, broadband single-pixel feeds, numerical modeling, design optimization, array calibration, beamforming, and experimental results. It is anticipated that one of the main emphases will be the connection between electrical and electromagnetic antenna properties and the system-level performance requirements for efficiency, sensitivity, field of view, imaging dynamic range, and polarization purity. Various antenna configurations are under investigation, with the desire for continuous field of view, low system noise, and high aperture efficiency over wide bandwidths (2:1 or more). These comprise new antenna array concepts that achieve the performance requirements through optimal co-design of the antenna and low-noise front ends. This presents significant challenges in computational electromagnetics and in understanding the behavior of an array and its mutual interaction with low noise amplifiers (LNAs). Current research issues include the development of appropriate performance metrics and measurement techniques for strongly coupled, high sensitivity arrays, reducing the cost of construction, alignment and maintenance of these new instruments, low noise CMOS LNAs, integrated broadband receiver-on-a-chip, and active impedance matching. Papers on these topics and others related to antenna development for radio astronomy are solicited for the Special Issue. Manuscripts should conform to the requirements for regular papers as specified in the Information for Authors on the inside back cover of the IEEE Transactions on Antennas and Propagation and the Transactions Web site (http://www.ict.csiro.au/aps). Potential contributors may contact the Guest Editors bye-mail (see contact information provided below) to determine the suitability oftheir contribution to the special issue. All invited and contributed papers must be submitted through the AP Transactions Manuscript Central Web site (http://mc.manuscriptcentral.com/tap-ieee), with a statement to the Editor-in-Chief of the IEEE Transactions on Antennas and Propagation, Dr. Trevor S. Bird, that they are intended for this Special Issue.

A 3–8 GHz Low-Noise CMOS Amplifier

A wideband CMOS low-noise amplifier (LNA) is proposed by using the concept of mutual coupling technique implemented through a symmetric center-tap inductor. A frequency widening network is designed with a center-tap inductor at the input and the output of an LNA to achieve bandwidth extension with a single stage amplifier. The proposed wideband low noise amplifier is implemented in the 0.18 mum CMOS technology. This design obtains a bandwidth of 3-8 GHz with a power consumption of 3.77 mW from a 1.8 V supply.

Design of a CMOS LNA with an integrated on‐chip filter for DVB‐S applications

AbstractA low noise amplifier (LNA) and a lumped‐element Chebychev‐type bandpass filter (BPF) co‐design, intended for using in digital video broadcasting satellite (DVB‐S), which were fabricated in the TSMC 0.18 μm CMOS technology is presented. The two‐stage LNA is constructed based on the source‐degenerated cascode topology for its superior noise performance and reverse isolation. Moreover, a miniaturized BPF with one transmission zero is connected to the output of the LNA that helps to improve the rejection level in the lower stopband. Experiment results demonstrated a good out‐band suppressed below 60 dB at 7.2 GHz, a maximum power gain of 12 dB, a minimum NF of 4.78 dB, and an IIP3 of −1 dBm while drawing 9.4 mA from a 1.8 V supply. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1580–1584, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24355

A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner

A wideband CMOS low noise amplifier (LNA) with single-ended input and output employing noise and IM2 distortion cancellation for a digital terrestrial and cable TV tuner is presented. By adopting a noise canceling structure combining a common source amplifier and a common gate amplifier by current amplification, the LNA obtains a low noise figure and high IIP3. IIP2 as well as IIP3 of the LNA is important in broadband systems, especially digital terrestrial and cable TV applications. Accordingly, in order to overcome the poor IIP2 performance of conventional LNAs with single-ended input and output and avoid the use of external and bulky passive transformers along with high sensitivity, an IM2 distortion cancellation technique exploiting the complementary RF performance of NMOS and PMOS while retaining thermal noise canceling is adopted in the LNA. The proposed LNA is implemented in a 0.18 mum CMOS process and achieves a power gain of 14 dB, an average noise figure of 3 dB, an IIP3 of 3 dBm, an IIP2 of 44 dBm at maximum gain, and S11 of under -9 dB in a frequency range from 50 MHz to 880 MHz. The power consumption is 34.8 mW at 2.2 V and the chip area is 0.16 mm2.

A 5.79‐dB NF, 30‐GHz‐band monolithic LNA with 10 mW power consumption in standard 0.18‐μm CMOS technology

AbstractA 30‐GHz (Ka‐band) low‐noise amplifier (LNA) with 10 mW power consumption (PDC) using standard 0.18‐μm CMOS technology was designed and implemented. To achieve sufficient gain, this LNA was composed of three cascade common‐source stages, and a series peaking inductor (Lg3) was added to the input terminal of the third stage to boost the peak gain (S21‐max) from 11.7 (at 28.8 GHz) to 14.5 (at 28 GHz), i.e., 23.9% (simulation). Shunt RC feedback was adopted in the third stage for achieving good output impedance matching. At 30 GHz, this LNA achieved excellent input return loss (S11) of −19.5 dB, output return loss (S22) of −23.8 dB, forward gain (S21) of 11.1 dB, reverse isolation (S12) of −49.2 dB, and noise figure of 5.79 dB. The corresponding gain/PDC was 1.11, which is better than those of the CMOS LNAs around 30 GHz reported in the literature. The measured input‐referred 1‐dB compression point (P1dB‐in) and input third‐order intermodulation point (IIP3) were −10.9 and −2 dBm, respectively. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 933–937, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24250

Design and Analysis for a 60-GHz Low-Noise Amplifier With RF ESD Protection

An RF electrostatic discharge (ESD) protection for millimeter-wave (MMW) regime applied to a 60-GHz low-noise amplifier (LNA) in mixed-signal and RF purpose 0.13-mum CMOS technology is demonstrated in this paper. The measured results show that this chip achieves a small signal gain of 20.4 dB and a noise figure (NF) of 8.7 dB at 60 GHz with 65-mW dc power consumption. Without ESD protection, the LNA exhibits a gain of 20.2 dB and an NF of 7.2 dB at 60 GHz. This ESD protection using an impedance isolation method to minimize the RF performance degradation sustains 6.5-kV voltage level of the human body model on the diode and 1.5 kV on the core circuit, which is much higher than that without ESD protection (< 350 V). To our knowledge, this is the first CMOS LNA with RF ESD protection in the MMW regime and has the highest operation frequency reported to date.

Low-power, high-gain and low-noise CMOS distributed amplifier for UWB systems

A 3-10-GHz CMOS distributed amplifier (DA) with flat and low noise figure (NF) and flat and high power gain (S 21 ) is demonstrated. A flat and low NF was achieved by adopting an RL terminating network for the gate transmission line, and a slightly under-damped Q -factor for the second-order NF frequency response. Besides, an flat and high S 21 was achieved by using the proposed cascade gain cell, which constitutes a cascode-stage with a low- Q RLC load and an inductive-peaking common-source stage. In the high-gain mode, the DA consumed 37.8 mW and achieved a flat and high S 21 of 20.47plusmn0.72 dB with an average NF of 3.29plusmndB over the 3plusmn10plusmnGHz band of interest, one of the best reported NF performances for a CMOS UWB DA or low-noise amplifier. In the low-gain mode, the DA achieved S 21 of 11.03plusmn0.98plusmndB and an average NF of 4.25plusmndB with a power dissipation ( PD ) of 6.86 mW, the lowest PD ever reported for a CMOS UWB DA or LNA with an average S 21 of greater than 10 dB.

0.5 V ultra-low power wideband LNA with forward body bias technique

An ultra-low power wideband CMOS low noise amplifier (LNA) fabricated in TSMC 0.18 µm RF CMOS process for sub 1 GHz applications is presented. The capacitive cross-coupled LNA with forward-body-bias (FBB) technique is adopted to achieve wideband input impedance matching and low power, low noise factor. The LNA is tested in the frequency range of 400–900 MHz, and exhibits a voltage gain of 18.5–20.7 dB, and a noise figure of 2.95 dB, drawing only 0.385 mW from 0.5 V power supply.

Parasitic-aware robust concurrent dual-band matching network for a packaged LNA

A generalised form of a concurrent dual-band matching network has been proposed for a packaged CMOS low noise amplifier (LNA). To eliminate the detrimental effects of component non-idealities on matching performance, a modified set of design equations has been developed. The robustness of the proposed network has been demonstrated at the GSM900 and DCS1800 bands. Incorporating this network, an LNA designed in a 0.18 µm CMOS process provides S11 of −33 and −30 dB, gain of 16.54 and 11.03 dB and noise figure of 1.35 and 2.37 dB, respectively, at 900 MHz and 1.7 GHz. The LNA draws a current of 2 mA from 1.8 V supply.

A 1V folded common-gate CMOS LNA for full UWB band

This paper presents a low voltage 2.8-11.2GHz CMOS broadband low noise amplifier (LNA) using folded common-gate (CG) topology. The broadband input matching is achieved by adopting CG topology. Bandwidth extension is proposed by inserting an inductor to create a broadband band-pass characteristic with a choke inductor. A folded topology is employed to reduce the supply voltage and thus power consumption. A source follower jointly acts as the buffer stage for broadband output impedance matching and feed-forward path for gain enhancement. Maximum power gain is 11.2dB and the NF ranges from 2.58 to 4dB over the full band. The LNA achieves an average IIP3 of -6.5dBm while consumes only 4.6mW.The proposed broadband LNA is designed in 0.18-µm CMOS process from 1V supply.

Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit

This paper proposes a novel wide-tunable CMOS low-noise amplifier (LNA) using a variable inductor. The variable inductance can be tuned by shielding the magnetic flux, which uses a metal plate above the inductor. The metal plate can be moved using a MEMS actuator. At the present time, the MEMS actuator has not been implemented yet. In this paper, we present a feasibility study on the proposed LNA using the variable inductor. The proposed LNA uses two variable inductors for input and output impedance matching-tuning. The LNA achieves a power gain (PG) of over 10dB at a tuning range of 1.6-3.2GHz.

A 3–10 GHz CMOS low‐noise amplifier using wire bond inductors

AbstractIn this article, a small‐sized 3–10 GHz CMOS LNA for ultra‐wideband (UWB) applications is presented. To reduce 2 on‐chip inductors, wire bond inductors are used instead of input inductor of multisectional reactive network and source degeneration inductor. The noise figure of low‐noise amplifier (LNA) is 4 dB at minimum and IIP3 + 1.1 dBm at 5 GHz, respectively. The current consumption is 4 mA at 1.8 V supply. The LNA chip size including pads is 1 mm × 1 mm. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 414–416, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24082

Third-order nonlinearity vs. load impedance for CMOS low-noise amplifiers

The linearity of two 90 nm CMOS low-noise amplifiers has been measured and analyzed. The analysis is based on Taylor series expansion of simulated I– V characteristics. The two amplifiers are cascode amplifiers with transistors of the same size but with different loads. Even though the center frequencies of the amplifiers are as high as 15 and 20 GHz, respectively, the measured results correlate well with the low-frequency-based estimation of linearity. The analysis shows that for a low load impedance, the dominating source of nonlinearity is transconductance, while for a high load impedance the nonlinearity of the output conductance instead dominates.

A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network

In this paper, a CMOS low-noise amplifier (LNA) with a new input matching topology has been proposed, analyzed and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a 0.18 - μ m 1 P 6 M CMOS technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure ( NF ) of 4.57 dB and an NF min of 4.46 dB. The reverse isolation S12 of the LNA can achieve - 40 dB and the input and output return losses are better than - 11 dB . The input 1-dB compression point is - 11 dB m and IIP3 is - 0.5 dB m . This LNA drains 10 mA from the supply voltage of 1 V.

Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in 0.18μm CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5GHz, with 1.9dB NF, 50Ω input impedance, 1GHz 3dB power bandwidth, 20.5dB power gain (S21), high reverse isolation (S12)<−48dB, −18.5dB input matching (S11) and −21.3dB output matching (S22), while dissipating as low power as 2mW at 1.8V power supply.