CMOS Low Noise Amplifier Research Articles

A low power low noise amplifier with subthreshold operation in 130 nm CMOS technology

AbstractIn this article, a 5.8 GHz ISM‐band CMOS low noise amplifier (LNA) operating in a subthreshold region is presented. A conventional source degeneration inductor is eliminated for higher signal gain while providing reasonable input impedance. The LNA is fabricated using 130 nm CMOS technology and measured signal gain, noise figure, and power consumption are 13.4 dB, 5.2 dB, and 980 μW, respectively, at target frequency. Also the LNA achieves the highest figure of merit among the recently published subthreshold LNAs. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2762–2764, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23788

Comparative analysis of wideband CMOS low-noise amplifiers for the RF range

A formalized method is presented for the circuit design of wideband low-noise amplifiers (LNAs) for RF applications. For a variety of LNAs thus obtained, a comparative performance analysis is performed by computer simulation in the frequency domain, involving optimization of small-signal LNA models. Optimal designs are thus identified showing a low reflection coefficient and a high gain over a wide frequency range extending to several gigahertz. Account is taken of limitations imposed by existing manufacturing technologies. For the sake of simplicity, the LNA configurations considered do not include frequency-selective networks.

A 0.18‐μm 3.1–4.8 GHz CMOS wideband LNA for UWB system

AbstractWe have proposed a 3.1–4.8 GHz CMOS wideband low noise amplifier (LNA) for ultra wideband system. The LNA is fabricated with the 0.18‐μm 1P6M standard CMOS process. Measurement of the CMOS LNA was performed using RF probe station. From 3.1 to 4.8 GHz, the wideband LNA exhibits a noise figure of 3.3–3.7 dB, a gain of 12.8–13.9 dB, and an input/output return loss higher then 9.4/7.3 dB. The input IP3 (IIP3) at 4.1 GHz is +1.25 dBm, and consumes 16.5 mW of power. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 2368–2371, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23664

Design of dispersive layered SAW filters with CMOS low noise amplifier

Up to now, RF front‐end surface acoustic wave (SAW) filters for mobile communication are mainly fabricated on LiNbO3 and LiTaO3 substrates. A monolithic integration of these filters on Si substrates is highly desirable, but Si is non piezoelectric. One alternative is the deposition of a piezoelectric film on the semiconductor substrate. CMOS technology is very attractive for integrating the radio frequency modules in a single chip. This paper presents the analysis and realisation of a SAW passband filter on silicon substrate based on a piezoelectric ZnO thin film working near 1 GHz , integrated with a CMOS low‐noise amplifier. We propose a modified coupling of modes (COM) approach for a layered ZnO/Si surface acoustic wave filter. The COM parameters in this formulation are the Rayleigh wave velocity, the electromechanical coupling coefficient, the complex reflection coefficient, the transduction coefficient and the inter‐digital capacitance C. This is a dispersive SAW layered filter some parameters of which become frequency dependent due to the phase velocity dispersion. We present the theoretical and experimental results of the filter integrated with a CMOS low noise amplifier.

A Magnetic Feedback Method for Low-Voltage CMOS LNA Reverse-Isolation Enhancement

A magnetic feedback method for enhancing the reverse isolation of low-voltage (1.2-V), single-transistor CMOS low-noise amplifiers (LNAs) is presented. The method neutralizes the gate-drain overlap capacitance of the amplifying transistor, allowing for adequate reverse isolation without gain reduction. The method does not require a differential LNA topology and input matching is facilitated since the degeneration inductor is not a part of a magnetic feedback loop. In addition, it allows for neutralizing the intrinsic part of the parasitic capacitance, which cannot be neglected in short-channel devices. Simulation results utilizing a standard 0.18-m CMOS process indicate a 17-29-dB improvement in the reverse-isolation performance with minimal noise figure deterioration.

Desensitized CMOS Low-Noise Amplifiers

The minimum attainable noise figure for scaled- CMOS low-noise amplifiers (LNAs) is limited by impedance mismatches such as the well-known noise/power tradeoff. In this paper, we show that a power-constrained optimization of the device noise resistance parameter, R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> , significantly reduces the impact of mismatches and variations and leads to an almost simultaneous noise and power match. This process, called desensitization, makes the design largely immune to measurement and modeling errors and manufacturing variations, and significantly reduces frequency-dependent noise mismatches in wide-band LNAs. Measured data from devices and desensitized LNAs designed on 180-nm and 90-nm CMOS processes shows that: (1) a device size selected for optimum R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> middot is less sensitive to source impedance mismatches and provides a wide-band noise match; and (2) LNAs approach a simultaneous input and noise match, and exhibit significant improvements (ges 2x) in their wide-band noise performance.

A Multiband Inductor-Reuse CMOS Low-Noise Amplifier

This paper presents the design and implementation of a new multiband, multistandard CMOS low-noise amplifier (LNA) that reuses inductors for different frequency bands to minimize chip area. The idea is to adaptively reconfigure a CMOS transistor in either common source or common gate configuration to achieve narrow-band (NB) or wide-band (WB) input matching, respectively, while conveniently reusing input and load inductors for both bands. This architecture is suitable for 802.11 a/b/g and Public Safety Broadband (PSB) applications, where the NB configuration covers wireless local area network (WLAN) 802.11 b/g, while the WB configuration accommodates the PSB at 4.9 GHz and WLAN 802.11 a. Two versions of the proposed idea, a tapped-capacitor and a tapped-inductor input-matched LNA, have each been designed and fabricated in 0.13-mum CMOS and measurement results are demonstrated.

A Highly Linear Wideband CMOS Low-Noise Amplifier Based on Current Amplification for Digital TV Tuner Applications

A differential wideband low-noise amplifier (LNA) based on the current amplification scheme is presented for digital TV tuners. In order to highly improve the linearity and exploit the noise cancellation, a common-gate stage with positive current feedback is integrated in parallel with a common-source stage using the current mirror amplifier. The proposed 0.18-mum CMOS LNA exhibits a power gain of 20.5 dB, an IIP3 of 2.7 dBm, an IIP2 of 43 dBm, and an average noise figure of 3.3 dB with 32.4 mW power consumption at a 1.8-V power supply and 0.12 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.

Input match and load tank digital calibration of an inductively degenerated CMOS LNA

This paper presents a technique for independently tuning the center frequency and quality of the input match for a CMOS low noise amplifier implemented using the inductive source degenerating topology. This technique allows for the input match to be centered to the desired frequency in the presence of process shifts and parasitic elements. The complete calibration loop is presented. The implemented calibration circuits allow for fast calibration, low additional power consumption during calibration, and negligible additional power consumption during operation. In addition, the center frequency of the load tank is tuned to match the desired center frequency of operation using the same calibration loop.

A linear current-reused LNA for 3.1-10.6GHz UWB receivers

An ultra-wide-band CMOS low-noise amplifier (LNA) employing a common-gate (CG) stage for wideband input matching is presented. This LNA utilizes the concurrent noise and distortion canceling techniques. Moreover, the current-reused technique exploiting the passive network instead of using the active and power consuming element is introduced to preserve the power consumption while contributing to the noise canceling trend. In other words, this topology is capable of canceling the noise effect of input transistor without consuming much current. Simulation results based on a 0.13µm standard RFCMOS technology shows that a power gain of 13.5dB and the noise figure of 2.7-4.2dB over the -3-dB bandwidth of 2.6-10.7GHz. With the presence of a weak inversion biased transistor, an input third-order intercept point (IIP3) of +5dBm is achieved. The power consumption is 13.5mW from a single 1.2V power supply.

A high-gain differential CMOS LNA for 3.1-10.6GHz ultra-wideband receivers

This paper presents a high-gain differential CMOS low noise amplifier (LNA) for 3.1-10.6GHz ultra-wideband receivers. A novel structure that combines capacitive cross-coupling common-gate topology with common-source topology is proposed, which increases the power gain greatly and imposes little impact on other performances of the LNA.The LNA is designed in the TSMC 0.18µm CMOS technology. Post-layout simulation results show that the LNA achieves a power gain of 14.9 ∼ 16dB and a noise figure of 3.5 ∼ 4.9dB with a current consumption of 6.3mA from a 1.8V power supply. The layout area is 0.7 × 0.9mm2.

A low-power and high-gain fully integrated CMOS LNA

In this paper, we present the design of a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18μm CMOS technology for 2.4GHz frequency range. Using cascode configuration, lower power consumption with higher voltage and power gain are achieved. In this configuration, we managed to have a good trade off among low noise, high gain, and stability. Using common-gate (CG) configuration, we reduced the parasitic effects of Cgd and therefore alleviated the stability and linearity of the amplifier. This configuration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4GHz, with 37.6dB voltage gain, 2.3dB noise figure (NF), 50Ω input impedance, 450MHz 3dB power bandwidth, 11.2dB power gain (S21), high reverse isolation (S12)<−60dB, while dissipating 2.7mW at 1.8V power supply.

Sub-0.2 dB Noise Figure Wideband Room-Temperature CMOS LNA With Non-50 $\Omega$ Signal-Source Impedance

This paper presents a wideband low-noise amplifier (LNA) designed to be used as the first stage of the receiver in the Square Kilometer Array radio telescope. The LNA design procedure and its layout features are discussed. The noise figure optimization procedure determines the signal-source resistance that results in reduced noise figure. When used in the radio telescope, the required signal-source resistance will be presented by the telescope custom-made antenna elements. The LNA, designed in 90 nm bulk CMOS, achieves sub-0.2 dB noise figure from 800 MHz to 1400 MHz, return loss of more than 11 dB, gain of more than 17 dB driven into a 50 load, output 1 dB compression point of 2 dBm, output IP3 of 12 dBm, and output IP2 of 22 dBm while consuming 43 mA from a 1 V supply. In the LNA implementation presented in this paper the load choke inductor and the source inductor are integrated whereas the gate-, bias-, and the choke-inductor between two transistors of the cascode are external. The noise figure of the presented LNA is to our knowledge the lowest noise figure achieved by a power matched wideband CMOS LNA at room temperature.

High-Gain Wideband CMOS Low Noise Amplifier with Two-Stage Cascode and Simplified Chebyshev Filter

An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-μm CMOS process and adopts a two-stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power-gain bandwidth product of 399.4 GHz.

Development of Integrated Broad-Band CMOS Low-Noise Amplifiers

This paper presents a systematic design methodology for broad-band CMOS low-noise amplifiers (LNAs). The feedback technique is proposed to attain a better design tradeoff between gain and noise. The network synthesis is adopted for the implementation of broad-band matching networks. The sloped interstage matching is used for gain compensation. A fully integrated ultra-wide-band 0.18-mum CMOS LNA is developed following the design methodology. The measured noise figure is lower than 3.8 dB from 3 to 7.5 GHz, resulting in the excellent average noise figure of 3.48 dB. Operated on a 1.8-V supply, the LNA delivers 19.1-dB power gain and dissipates 32 mW of power. The gain-bandwidth product of the UWB LNA reaches 358 GHz, the record number for the 0.18-m CMOS broad-band amplifiers. The total chip size of the CMOS UWB LNA is 1.37 times 1.19 mm2.

A Ku-Band Interference-Rejection CMOS Low-Noise Amplifier Using Current-Reused Stacked Common-Gate Topology

A Ku-band CMOS low-noise amplifier (LNA) with high interference-rejection (IR), wide gain control range, and low dc power consumption is presented. The LNA consists of two common-gate metal-oxide-semiconductor field-effect transistors interconnected with an interstage parallel tank for the IR. The stacked common-gate stages share the same dc bias current to reduce power consumption and have controllable gain by changing this dc current. The implemented 0.13 mum CMOS LNA achieves measured power gain of 10.8 dB, noise figure of 4.2 dB, output P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> dB of -4.3 dBm at 15 GHz, while rejecting interference down to a 38.5 dB level. The gain control range is 23.3 dB by varying the gate voltage from 0.2 to 1.2 V. The LNA consumes only 4 mA from a 1.3-V supply.

Compact small signal modeling and PSO-based input matching of a packaged CMOS LNA in subthreshold region

The paper reports a small-signal model of a cascaded, packaged, CMOS low noise amplifier (LNA) operating in subthreshold region. The proposed compact model has been verified through CADENCE simulations in standard 0.18μm process. This model also accounts for the dominating role of some of the device parasitic capacitances in determining the input impedance of the amplifier. The closed form expression of the input impedance obtained-from this model is then used for synthesizing the input matching network of the common-source LNA using standard Q-based technique. It has been noted that the conventional Q-based matching approach does not provide symmetric matching characteristics (S11) about the center frequency (900MHz). To overcome this problem, a swarm intelligence-based evolutionary technique has been adopted for synthesis of the matching network. Symmetric nature is obtained both in terms of S11 as well as the real/imaginary parts of the input impedance.

Improving the Linearity of CMOS LNA Using the Post IM3 Compensator

In this paper, a new linearization method has been proposed for a CMOS low noise amplifier(LNA) using the Post IM3 Compensator. The fundamental operating theory of the proposed method is to cancel the IM3 components of the LNA output signal by generating another IM3 components, which are out-phase with respect to that of the LNA, from the Post IM3 Compensator. A single stage common-source LNA has been designed to verify the linearity improvement of the proposed method through 0.13 ㎛ RF CMOS process for WiBro system. The designed LNA achieves +7.8 ㏈m of input-referred 3 rd -order intercept point (ⅡP3) with 13.2 ㏈ of Power Gain, 1.3 ㏈ of noise figure and 5.7 mA @1.5 V power consumption. IIP3 is compared with a conventional single stage common-source LNA, and it shows IIP3 is increased by +12.5 ㏈ without degrading other features such as gain and noise figure.

Corrections to “CMOS Low-Noise Amplifier Design Optimization Techniques”

In the above titled paper (ibid., vol. 52, no. 5, pp. 1433-1442) as well as two other articles cited, several equations were incorrect. Corrections to these equations are provided.

Simulation study of the noise figure of nanometer-gate nMOS transistors near the scaling limit

We present a comprehensive simulation study of the noise figure of the nMOS transistors embedded in a common-source low noise amplifier (LNA) configuration using bulk 40- and 20-nm nMOSFETs, a 20-nm double-gate (DG) nMOSFET (a generic form of FinFET), and a 10-nm DG nMOSFET near the scaling limit. A physics-based two-dimensional (2-D) mixed-mode simulation approach is used to extract the noise parameters at 60 GHz. Minimum noise measure figure (NMF min) is used to take both the amplifier gain and noise figure into account. The optimal gate bias for a nMOS transistor is found to be 0.2–0.3 V above the threshold voltage. The 40-nm nMOS amplifier has a minimum noise measure figure of 1.8 dB at 60 GHz under the optimized power using current silicide technology. It is shown that the noise performance of CMOS LNAs can be further enhanced by down scaling to 10 nm with sub-1 dB noise figure at 60 GHz.