CMOS Low Noise Amplifier Research Articles

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.

A monolithic 1.57/5.25‐GHz concurrent dual‐band low‐noise amplifier using InGaP/GaAs HBT technology

AbstractA monolithic concurrent dual‐band low‐noise amplifier (LNA) using InGaP/GaAs HBT technology is demonstrated for the first time. The LNA provides narrowband gain and matching simultaneously at both 1.57‐GHz (GPS) and 5.25‐GHz (ISM) bands. It consumes only 15‐mW power and achieves transducer gains (S21) of 25.3 and 14.3 dB, input return losses (S11) of 6.8 and 11.5 dB, reverse isolation (S12) of −30.8 and −32.2 dB, and noise figures of 2.55 and 4.5 dB at these two bands, respectively. The performance at 5.25 GHz is comparable with the 2.45/5.25‐GHz concurrent dual‐band CMOS LNA with a bonding wire as the gate inductor using 0.35‐m CMOS technology 1. © 2004 Wiley Periodicals, Inc. Microwave Opt Technol Lett 42: 58–60, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20206

Highly Linear Receiver Front-End Adopting MOSFET Transconductance Linearization by Multiple Gated Transistors

Highly linear receiver RF front-end adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel (multiple gated transistor, or MGTR), combined with some additional circuit techniques are reported. In MGTR circuitry, linearity is improved by using transconductance linearization which can be achieved by canceling the negative peak value of g/sub m/'' of the main transistor with the positive one in the auxiliary transistor having a different size and gate drive combined in parallel. This enhancement, however, is limited by the distortion originated from the combined influence of g/sub m/' and harmonic feedback, which can greatly be reduced by the cascoding MGTR output for the amplifier and by the tuned load for the mixer. Experimental results designed using the above techniques show IIP/sub 3/ improvements at given power consumption by as much as 10 dB for CMOS low-noise amplifier at 900 MHz and 7 dB for Gilbert cell mixer at 2.4 GHz without sacrificing other features such as gain and noise figure.

A fully integrated concurrent dual‐band CMOS low‐noise amplifier

AbstractThis paper presents a fully integrated concurrent dual‐band CMOS low‐noise amplifier (LNA). The LNA is implemented in a standard 0.18‐μm 6M1P CMOS process and is designed from the system viewpoint to provide higher gain at the higher band, for the first time, to compensate the higher‐band signal's extra loss over the air transmission. The LNA drains 5.3 mA of current from a 1.8‐V supply voltage and achieves voltage gains of 16 and 22.5 dB, input return losses of 28 and 27 dB, and noise figures of 3.0 and 3.1 dB at 2.4 and 5.2 GHz, respectively. © 2003 Wiley Periodicals, Inc. Microwave Opt Technol Lett 39: 52–53, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.11124

A merged CMOS LNA and mixer for a WCDMA receiver

A low-noise amplifier (LNA) and mixer circuit in 0.35-μm CMOS operates at 2.1 GHz. Merging the LNA and mixer lowers the number of transistors in the signal path and thereby also the nonlinearity and power consumption. The circuit meets the specifications for a direct conversion wide-band code-division multiple access (WCDMA) receiver. Its noise figure is 3.4 dB (5kHz to 5MHz), the total conversion gain is 23 dB, the third-order input-referred intercept point is -1.5 dBm, and the local oscillator leakage to the antenna is less than -71 dBm. The fully differential circuit takes 8 mA from a 2.7-V supply.

High ESD performance, low power CMOS LNA for GPS applications

This paper describes the design of a high performance 0.25 μm CMOS low noise amplifier (LNA) for the global positioning system (GPS) operating at 1.57 GHz. The LNA features a 1.5 dB noise figure. The input ESD-protection is in the order of 3 kV HBM and the power consumption is only 6 mW.

13 GHz 4.67 dB NF CMOS low-noise amplifier

The design and measured results of a fully-integrated 13 GHz CMOS low-noise amplifier (LNA) are presented. Effects of substrate resistances on LNA performance are discussed. The LNA has 4.67 dB noise figure and +8.5 dBm of input-referred third-order intercept point (IIP3) with a power consumption of 9.72 mW.

Analysis and optimization of the impact of channel resistance on CMOS LNA noise performance

The intrinsic channel resistance, which is caused by the finite charging time of the carriers in the inversion layer, has remarkable impact on RF CMOS circuits, especially low noise amplifier (LNA), the first block of receiver. The impact of channel resistance on the noise performance of LNA is thoroughly studied and analyzed in this paper, and then new formulae are proposed systematically. Moreover, revised noise figure optimization technique is presented. All of this work will be very instructive for the design of high performance LNA.

A 7-GHz 1.8-dB NF CMOS low-noise amplifier

A 7-GHz low-noise amplifier (LNA) was designed and fabricated using 0.25-/spl mu/m CMOS technology. A cascode configuration with a dual-gate MOSFET and shielded pads were adopted to improve the gain and the noise performance. The effects of the dual-gate MOSFET and the shielded pads are discussed quantitatively. An associated gain of 8.9 dB, a minimum noise figure of 1.8 dB, and an input-referred third-order intercept point of +8.4 dBm were obtained at 7 GHz. The LNA consumes 6.9 mA from a 2.0-V supply voltage. These measured results indicate the feasibility of a CMOS LNA employing these techniques for low-noise and high-linearity applications at over 5 GHz.

Analysis of thermal noise in scaled MOS devices and RF circuits

In this paper physics-based numerical simulation is applied to the evaluation of the noise performance of MOS devices and circuits for technologies with minimum feature size ranging from 0.25 to 0.1 μm. Adopting a simulation approach for noise calculations that considers the transistor as an active transmission line and by post-processing the results of two-dimensional hydrodynamic device simulations, a detailed analysis of the dependences of MOSFET noise parameters and minimum noise figure (NF) on bias and technology scaling is carried out. Furthermore, the impact of scaling on the performance of a simple low noise amplifier is analyzed; analytical models and physics-based device simulations provide predictions about the trend of NF and power consumption of the amplifier, for operation frequencies from 900 MHz up to 20 GHz. The results of this work confirm that noise performance improve as CMOS technology is scaled down, increasing the interest for CMOS low-noise amplifiers.

Miniature 3-D inductors in standard CMOS process

The structure of a miniature three-dimensional (3-D) inductor is presented in this paper. The proposed miniature 3-D inductors have been fabricated in a standard digital 0.35-/spl mu/m one-poly-four-metal (1P4M) CMOS process. According to the measurement results, the self-resonance frequency f/sub SR/ of the proposed miniature 3-D inductor is 34% higher than the conventional stacked inductor. Moreover, the inductor occupies only 16% of the area of the conventional planar spiral inductor with the same inductance and maximum quality factor Q/sub max/. A 2.4-GHz CMOS low-noise amplifier (LNA), which utilized the proposed miniature 3-D inductors, has also been fabricated. By virtue of the small area of the inductor, the size and cost of the radio frequency (RF) chip can be significantly reduced.

Impact of intrinsic channel resistance on noise performance of CMOS LNA

Channel resistance cannot be neglected for CMOS circuits that operate at radio frequency (RF), especially for a low noise amplifier (LNA), which is a very important block in CMOS RF transceivers. The impact of channel resistance on the noise performance of an LNA is thoroughly studied and analyzed and new formulas are proposed systematically in this work. Furthermore, a revised noise figure optimization technique is discussed. Simulation results are also proposed. All of this work will be very instructive for the design of high-performance LNA.

A sub-1-dB NF±2.3-kV ESD-protected 900-MHz CMOS LNA

A sub-1-dB noise figure HBM ESD-protected [-3 kV, 2.3 kV] low noise amplifier (LNA) has been integrated in a 0.35-/spl mu/m RF CMOS process with on-chip inductors. The sensitivity of the LNA performances to the spread of parasitics associated with package and bondwire has been attenuated by using an inductive on-chip source degeneration. At 920 MHz and P/sub dc/=8.6 mW, the LNA features: noise figure NF=1 dB, input return loss=-8.5 dB, output return loss=-27 dB, power gain G/sub p/=13 dB, input IIP3=-1.5 dBm. At a power dissipation of 5 mW and 17.6 mW, a NF respectively equal to 1.2 dB and 0.85 dB is measured. The CMOS LNA takes 12 pins of a TQFP48 package, an area of 1.0/spl times/0.66 mm/sup 2/ (bondwire pads excluded) and it is the first HBM ESD-protected [-3 kV, 2.3 kV] CMOS LNA to break the 1-dB NF barrier.

Low-voltage CMOS low-noise amplifier using planar-interleavedtransformer

A low-voltage CMOS low-noise amplifier (LNA) architecture is presented. A planar-interleaved transformer is used to couple the RF signal between cascode transistors in a conventional LNA topology. Based on the modified RF MOS model, a 5.2 GHz CMOS LNA with fully on-chip input/output matching was designed to verify the low-voltage LNA architecture. The measurement results show that it can be operated with 1 V supply voltage.

Noise optimization of an inductively degenerated CMOS low noise amplifier

This paper presents a technique for substantially reducing the noise of a CMOS low noise amplifier implemented in the inductive source degeneration topology. The effects of the gate induced current noise on the noise performance are taken into account, and the total output noise is strongly reduced by inserting a capacitance of appropriate value in parallel with the amplifying MOS transistor of the LNA. As a result, very low noise figures become possible already at very low power consumption levels.

A 2-dB noise figure 900-MHz differential CMOS LNA

This paper proposes a new circuit topology for RF CMOS low noise amplifier (LNA). Since pMOS devices are approaching the performances of nMOS devices in scaled technologies, the idea is to realize the input stage shunting an inductively degenerated nMOS stage with a pMOS one. In this way, due to the inherent current reuse, the performances can be improved using the same power consumption. Since the devices of an inductively degenerated input stage are working in moderate inversion (at least at moderate power dissipation), prior to the stage optimization an appropriate moderate inversion model is introduced. A fully differential 900-MHz 0.35-/spl mu/m CMOS LNA (plus output buffer) prototype achieves the following performances: 2-dB noise figure (NF), 17.5-dB power gain, -6-dBm IIP3 with 8-mA current consumption from a 2.7-V voltage supply. To the author's knowledge, this is the lowest reported NF for a fully differential CMOS LNA operating at this power consumption level. As an additional feature, this LNA has a programmable gain.

Design of a 1.8 GHz low-noise amplifier for RF front-end in a 0.8 μm CMOS technology

CMOS technologies are widely exploited now in the area of a few-GHz-range radio frequency (RF) circuits as well as in the area of baseband circuits. Accordingly, the CMOS low-noise amplifier (LNA) is gaining its popularity, tailored to the applications such as GSM, PCS, IMT-2000, and wireless LAN. In this paper, compact and comprehensive design strategies for CMOS LNA are presented. Basic topologies are compared and analyzed using key equations newly derived. Using these strategies, an LNA based upon LC resonance using on-chip spiral inductors is designed and investigated. This LNA, targeted for 1.8 GHz PCS, exhibits power gain of about 18 dB and noise figure (NF) of about 2.1 dB by both theory and post-layout simulation under a 0.8-/spl mu/m CMOS process and 3-V supply.

SPICE simulation and tradeoffs of CMOS LNA performance with source-degeneration inductor

In this brief, we study the tradeoffs of CMOS low noise amplifiers using source-degeneration inductor with both experimental data and simulation data. SPICE models based on the quasistatic (QS) assumption ignores the channel resistance and leads designers to overly rely on source-degeneration inductance. The non-QS model is much better. Source inductor adversely affects noise and gain. The parasitic capacitance at the gate imposes additional challenges for matching.

A fully integrated 1.9-GHz CMOS low-noise amplifier

A fully integrated 1.9 GHz CMOS low-noise amplifer (LNA) has been implemented in a 0.8 μm CMOS technology. For low-noise performance, the amplifier employs high-quality spiral inductors with a duality factor of 8.5-12.5, and device layout and bias condition of the active devices were optimized for low-noise conditions. This amplifier showed a noise figure of 2.8 dB with a forward gain of 15 dB at current consumption of 15 mA. To the authors' knowledge, this represents the lowest noise figure reported to date for a fully integrated CMOS LNA operating at 1.9 GHz.

A 12-mW wide dynamic range CMOS front-end for a portable GPS receiver

This paper describes a CMOS low-noise amplifier (LNA) and mixer intended for use in the front-end of a global positioning system (GPS) receiver. The circuits were implemented in a standard 0.35-/spl mu/m (drawn) CMOS process, with one poly and two metal layers. The LNA has a forward gain (S21) of 17 dB and a noise figure of 3.8 dB. The mixer has a voltage conversion gain of -3.6 dB and a third-order intermodulation intercept point (IP3) of 10 dBm, input referred. The combination draws 12 mW from a 1.5-V supply.