CMOS Digital Integrated Circuits Research Articles

Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits

Aided by the advancement of super-conductive materials, rapid single flux quantum (RSFQ) digital circuits are emerging as a promising complement or even replacement of the traditional CMOS digital integrated circuits. RSFQ digital circuits typically work at a low temperature of around 4.2 K, i.e., around −268.95 °C. Nevertheless, the operating frequency of RSFQ digital circuits reaches up to 770 GHz, which is orders of magnitudes faster than contemporary CMOS digital circuits. The high operating frequency causes critical design challenges especially for the clock networks and data path signals, where relative skew on wires need to be observed for achieving the correct functionality. Therefore, for designing a timing-variability-aware SFQ layout, it is necessary to match the PTL delays that are proportional to their respective lengths. And the matching of PTL delays should be carried out by extensions in PTL lengths. To meet the above-mentioned critical timing requirements, it is necessary to incorporate length-matching constraints into a routing problem, which is transformed from the timing requirements of matching the PTL delays during the logical synthesis stage. However, existing routing algorithms are inherently limited by preallocated splitters (SPLs), which complicates the subsequent routing stage under length-matching constraints. In this article, in order to effectively address the length-matching constraints, we reallocate SPLs to fully utilize routing resources. We propose the first multiterminal routing algorithm for RSFQ circuits, which integrates SPL reallocation into the routing stage and achieves 100% routing completion in the tested benchmarks. Compared with the state-of-the-art method, the proposed multiterminal routing algorithm reduces the required area by 17% and the runtime by 7%.

Precise Characterization and Multiobjective Optimization of Low Noise Amplifiers

Although practically all function blocks of the satellite navigation receivers are realized using the CMOS digital integrated circuits, it is appropriate to create a sepa- rate low noise antenna preamplifier based on a low noise pHEMT. Such an RF front end can be strongly optimized to attain a suitable tradeoff between the noise figure and trans- ducer power gain. Further, as all the four principal naviga- tion systems (GPS, GLONASS, Galileo, and COMPASS) work in similar frequency bands (roughly from 1.1 to 1.7 GHz), it is reasonable to create the low noise preamplifier for all of them. In the paper, a sophisticated method of the amplifier design is suggested based on multiobjective optimization. A substan- tial improvement of a standard optimization method is also outlined to satisfy a uniform coverage of Pareto front. More- over, for enhancing efficiency of many times repeated solu- tions of large linear systems during the optimization, a new modification of the Markowitz criterion is suggested compati- ble with fast modes of the LU factorization. Extraordinary attention was also given to the accuracy of modeling. First, an extraction of pHEMT model parameters was performed including its noise part, and several models were compared. The extraction was carried out by an original identification procedure based on a combination of metaheuristic and di- rect methods. Second, the equations of the passive elements (including transmission lines and T-splitters) were carefully defined using frequency dispersion of their parameters as Q, ESR, etc. Third, an optimal selection of the operating point and essential passive elements was performed using the im- proved optimization method. Finally, the s-parameters and noise figure of the amplifier were measured, and stability and third-order intermodulation products were also checked.

Compact modeling of response time and random-dopant-fluctuation-induced variability in nanoscale CMOS inverter

As MOSFETs are scaled down to nanometer feature size, random dopant fluctuation (RDF) severely affects CMOS digital integrated circuits (ICs). This paper proposes compact models for estimation of response time and RDF-induced variability in nanoscale CMOS inverter by solution of differential equation considering both input rise time and gate–drain coupling capacitance. The timing characteristics, including propagation delay, overshooting time and transition time, as well as its variability, are accurately modeled in analytical expressions. The proposed models are verified with HSPICE simulations. Monte Carlo analysis also confirms that the models are simple and effective in different design decisions such as width length ratios, load capacitances and source voltages. The studies show that a 7.59% spread in VT variation due to RDF results in about 5% spread in delay variability for the 65nm CMOS inverter.

Thermal Compensation Method for CMOS Digital Integrated Circuits Using Temperature-Adaptive DC–DC Converter

A cost-effective thermal compensation technique for CMOS digital integrated circuits (ICs) is proposed. The technique features a temperature-adaptive dc-dc converter serving as both temperature detector and variable power supply. The converter adopts a delay-line-based analog-to-digital converter to translate the temperature information into digital signals. By adjusting the output voltage, the dc-dc converter can help stabilize the ICs' operating frequency. The system was fabricated with a standard 1.5-mum digital CMOS process. With a supply of 3.3 V, the converter is capable of providing a variable supply voltage of 1.1-2.0 V with a maximum power efficiency of 92.1%. With this compensation technique, the temperature sensitivity of ICs is reduced from 4046 to 74 ppm/degC within a temperature range of 0-110degC

Transient characteristic analysis of high temperature CMOS digital integrated circuits

This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminalpn junctions. The calculation results can explain the experimental phenomenon.

Physical design of testable CMOS digital integrated circuits

A methodology for physical testability assessment and enhancement, implemented with a set of test tools, is presented. The methodology, which can improve the physical design of testable CMOS digital ICs, is supported in realistic fault-list generation and classification. Two measures of physical testability, weighted class fault coverage and fault incidence, and one measure of fault hardness are introduced. The testability is evaluated prior to fault simulation; difficult-to-detect faults are located on the layout and correlated with the physical defects which originate them; and suggestions for layout reconfiguration are provided. Several design examples are described, ascertaining the usefulness of the proposed methodology. The proposed methodology demonstrated that stuck-at test sets only partially cover the realistic faults in digital CMOS designs. Moreover, it is shown that classical fault models of arbitrary faults are insufficient to describe the realistic fault set. Simulation results have shown that the fault set strongly depends on the technology and on the layout style.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Binary Decision Diagrams (BDDs) For TheTest Pattern Generation

Since fault-free CMOS digital integrated circuits are characterized by very low values of quiescent power-supply current (IDDQ), and the most part of their faults provoke abnormally high values of such current, IDDQ testing is one of the most effective way of testing them. The classical test pattern generation at the logic level is not accurate enough for IDDQ testing, because the values of actual faulty current must be estimated and compared with the accuracy of the current monitor to decide on the fault detection; on the other side, electrical-level approaches are not feasible for VLSI ICs. The test pattern generation for IDDQ testing can be effectively performed with a mixed-level approach, featuring boolean manipulation by means of BDDs at the logic level, and using look-up tables for electrical-level data obtained by preliminary SPICE simulations on library cells.