CMOS Buffer Amplifier Research Articles

A novel tunable gain CMOS buffer amplifier for large resistive loads

An all-OTA analog buffer amplifier configuration capable of driving large resistive loads is presented. The proposed configuration features high input swing, gain tunability, wide-bandwidth, and low design complexity. The concept is validated with simulation results in Cadence Virtuoso using SCL 0.18-μm technology parameters. Using a ±0.9 V power supply, the buffer with a gain of 1, can drive a 1 Vp−p sinusoid into a 50 Ω load with a THD of better than 0.015%, with a 3-dB bandwidth of 1.55 GHz and consumes 9 mW. The proposed configuration is demonstrated with gain values varying from 0.25 V/V to 5 V/V and with different load values 16 Ω to 5.6 kΩ. The voltage gain is tunable over more than a decade with reasonable power levels. With low-gain OTA, the proposed buffer configuration works well without any complex frequency compensation circuit that makes the all-OTA analog buffer amplifier configuration simple compared to the existing buffer amplifiers.

Dual Push–Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays

This brief presents the experimental validation of a low-power, large output swing, class-AB buffer amplifier for column drivers of active-matrix flat-panel displays. By exploiting two complementary input amplifiers and a dual-path push–pull output stage, the proposed circuit achieves high-drive performance and rail-to-rail operation. In addition, two current boosters allow area optimization of the output diving transistors by dynamically lowering their threshold voltage. Implemented in a standard triple-well CMOS 0.35- ${\mu }{\text{m}}$ technology and supplied from a 3-V supply, the proposed buffer amplifier can drive a 1-nF column line load within a 1.11- ${\mu }\text{s}$ settling time under a full voltage swing, while drawing only 1.6 ${\mu }\text{A}$ quiescent current and occupying 5562 ${\mu }{\text{m}}^{{2}}$ of silicon area. As compared to the state of the art, the best figure of merit (pF/ ${\mu }\text{s}{\cdot } {\mu }\text{A}$ ) is found.

입·출력 시간차이를 이용한 전류 부스팅 구조를 갖는 DDI(Display Driver IC)용 저소비전력 고슬루율 CMOS 버퍼증폭기 설계에 관한 연구

입·출력 시간차이를 이용한 전류 부스팅 구조를 갖는 DDI(Display Driver IC)용 저소비전력 고슬루율 CMOS 버퍼증폭기 설계에 관한 연구

Dual output Rail to Rail CMOS Buffer Amplifier with Low Power and High Slew Rate for LCD Source Driver IC

Dual output Rail to Rail CMOS Buffer Amplifier with Low Power and High Slew Rate for LCD Source Driver IC

A compact rail-to-rail CMOS buffer amplifier with very low quiescent current

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push–pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 μm process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1 nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 μA quiescent current from a 3.3 V power supply.

Compact Low-Power High Slew-Rate CMOS Buffer Amplifier with Power Gating Technique

Compact Low-Power High Slew-Rate CMOS Buffer Amplifier with Power Gating Technique

Class-AB CMOS Buffer with Low Power and Low Leakage Using Transistor Gating Technique

A rail-to-rail class-AB CMOS buffer amplifier is proposed in this paper to drive large capacitive loads. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation .The name of applied technique is TRANSISTOR GATING TECHNIQUE, which gives the high speed buffer with the reduced low power dissipation (1.05%), low leakage and reduced area (2.8%) also. The proposed buffer is simulated at 45nm CMOS technology and the circuit is operated at 3V supply with Cadence software. This analog circuit is performed with reduced performance degradation as well as high current driving capability for the large input voltages. The proposed paper is achieved very high speed with very low propagation delay range i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by 30% (in ns) at 3V square wave input. The measured quiescent current is 56μA.

Design of Low Power and High Speed CMOS Buffer Amplifier with Enhanced Deriving Capability

Design of Low Power and High Speed CMOS Buffer Amplifier with Enhanced Deriving Capability

A New Architecture of LCD Driver of Rail-to-Rail Buffer with High Gain Wide Range

A new modified CMOS buffer amplifier with rail-to-rail input and output range is proposed by TSMC 0.35μm 2P4M process at 3.3V supply. The technique adds dummy pairs to sense the common mode range of the input differential pair and adjusts the output current accordingly. The amplifier provides high gain for a wider range of output voltages. Design considerations for reducing the impact of the additional circuitry on the core are provided. The technique described can be adapted for use with traditional fully-differential rail-to-rail amplifiers, which performs 86.9dB ~92dB dc gain, 15 MHz unit-gain bandwidth, high driving ability with high slew rate under a 100pF capacitance and a 3kΩ series resistance loading. The simulation results indicate that the settling times of rising and falling edge are within 3.5μs. It is effective for a high resolution and high speed LCD driver.

A rail-to-rail unity gain buffer amplifier for low-cost high resolution TFT LCD panels

A structural rail-to-rail high voltage CMOS buffer amplifier for driving gamma correction reference voltage of TFT LCD panels is presented. It operates from a single supply and only consumes 0.5 mA at 18 V power supply voltage. The circuit is designed for 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5 mA static current and 1 kohm resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50 mV at 5 mA constant output current, and below 2.5 mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and an input level detector using hysteresis comparator are applied. The complete circuit is realized in a high voltage 0.18 um 18 V CMOS process technology for display driver IC and the area measures only 0.056 mm2. The circuit operates at supply voltages from 8 V to 18 V.

Low-power high-slew-rate CMOS buffer amplifier for flat panel display drivers

A new high-slew-rate CMOS buffer amplifier consuming a very small quiescent current is proposed. This buffer amplifier recursively copies the output driving current and increases the tail current of the input differential pair during slewing. Since the proposed buffer has a possible slew rate higher than 10 V/µs for a load capacitance of 1 nF almost independently of static currents as low as 1 µA, this buffer amplifier is promising for column driver ICs of flat panel displays that require low static power consumption, high current driving capabilities, and small silicon areas.

P-38: Low-Power High-Slew-Rate CMOS Buffer Amplifier for Flat Panel Display Drivers

A new high-slew-rate CMOS buffer amplifier consuming a very small quiescent current is proposed for voltage buffer in flat panel displays. This buffer amplifier recursively copies the output driving current and increases the tail current of the input differential pair during slewing. Since the proposed buffer has a possible slew rate higher than 10 V/μs for a load capacitance of 1 nF almost independently of static currents as low as 1 μA, this buffer amplifier is promising for column driver ICs of flat panel displays.

A New CMOS Buffer Amplifier Design Used in Low Voltage MEMSInterface Circuits

To achieve low voltage high driving capability with quiescent current control, a class-AB CMOS buffer amplifier using improved quasi-complementary output stage and error amplifiers with adaptive loads is developed. Improved quasi-complementary output stage enables it more suitable for low voltage applications, while adaptive load in error amplifier is used to increase the driving capability and reduce the sensitivity of the quiescent current to fabrication process variation. The circuit has been fabricated in 0.8 μm CMOS process. With 300 O load in a ±1.5 V supply, its output swing is 2.42 V. The mean value of quiescent current for eight samples is 204 μA, with the worst deviation of 17%.

A fast-settling 3 V CMOS buffer amplifier

This paper presents a two-stage fast, power-efficient 3 V CMOS buffer amplifier with rail-to-rail input/output voltage ranges. Because of its constant g/sub m/, class-AB input stage, the amplifier is free of slew-rate limitation and its settling-time is quasi-independent on input step amplitude. The amplifier has 6 MHz unity-gain frequency, 1 mW power-consumption and settles to 1% accuracy within 180 ns on 100 pF load. As the class-AB input stage operates at constant quiescent current over the input voltage range, CMRR exceeds 70 dB.

High speed, high linearity CMOS buffer amplifier

A low-noise class AB buffer amplifier which has a rail-to-rail output swing while driving large resistive and capacitive loads is presented in this paper along with the test results. The amplifier is fabricated in a 3 /spl mu/m double-polysilicon double-metal CMOS technology and has on-chip frequency compensating capacitors. The basic performance factors obtained in this design are: A/sub 0/=70 dB, GBW=5.5 MHz, SR=7 V//spl mu/s, and /spl upsi//sub n/=10nV//spl radic/Hz@100 kHz. With a supply voltage of /spl plusmn/5 V, the amplifier has a /spl plusmn/4.7 V output swing and features a low 30 /spl Omega/ open-loop output impedance. The total harmonic distortion is at a low -77 dB for a 7V/sub out,pp/ output level with the fundamental frequency of 20 kHz. From the test results, it is demonstrated that an overall high performance is achieved with this design.

A 1.5 V class AB CMOS buffer amplifier for driving low-resistance loads

Few CMOS opamps that can operate on a single 1.5 V supply have been reported to date, although there is no lack of potential applications. Existing 5 V opamp designs require use of cascode and stacked transistors and consequently are not suited for operation at 1.5 V. A design technique for 1.5 V CMOS opamps has been outlined by Eschauzier et al. (see ISSCC Digest of Technical Papers, p. 246-7, Feb., 1994). The resulting circuit, a four-stage class AB opamp, is complex and data concerning the opamp performance in case of significant resistive or capacitive loads are lacking. The 1.5 V class AB CMOS opamp presented here has a less complex architecture and experimental results demonstrate capability of driving heavy resistive loads with low distortion.

Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges

This paper presents a CMOS buffer amplifier which operates on a single 5-V power supply. The uniquely symmetrical design adds the following advantages: rail-to-rail linear, symmetrical operation at both the input and output; the output stage allows the use of gate channel capacitors of standard MOSFET's as the compensation capacitor saving die area from 80%/spl sim/93% in a standard single polysilicon digital process; large gain-bandwidth product; high power supply rejection ratio; good common-mode rejection ratio; and easy compact layout suitable for design automation (layout as a parametric cell, allows easy adaption to changing processes). The buffer is capable of driving 300 /spl Omega//spl par/100 pF with a loaded gain-bandwidth product of more than 4 MHz and a fully loaded slew rate of greater than 4 V//spl mu/S. >

Class-AB large-swing CMOS buffer amplifier with controlled bias current

A class-AB large swing CMOS buffer amplifier with new error amplifier circuits is presented. The error amplifier accurately controls the quiescent current through the output transistors, thereby reducing the variation of the quiescent power dissipation due to process and temperature variations. The buffer amplifier fabricated using 1.2- mu m CMOS technology occupies an area of 103 mil/sup 2/ and dissipates an average of 4.7 mW under the quiescent condition with the standard deviation of only 3.2% of the average value. It has -63.6 dB THD with 3.5 V/sub pp/ output swing into a 300 Omega /150 pF load at 5 kHz. >

A LARGE-SWING HIGH-DRIVE CMOS BUFFER AMPLIFIER FOR A WIDE LOAD RANGE

A high-swing, high-drive CMOS buffer amplifier, with good stability over a wide range of capacitive and resistive loads, is presented in this paper. A new area efficient output stage with a relatively small compensation capacitor has been used so that the circuit occupies only 120 mils2 in a 3 μm CMOS technology. The buffer has a drive capability of 110 kHz into a 5000 pF load with a rail-to-rail output swing for load resistances greater than 10 kΩ and acceptable total harmonic distortion with loads down to 270 Ω.

Large-swing CMOS buffer amplifier

A circuit configuration for a CMOS buffer amplifier is described. The circuit, which is an enhancement of a previously reported buffer amplifier, features a large output voltage swing and a well-controlled quiescent current. A buffer amplifier of this type has been implemented in a 1.5- mu m CMOS technology. The prototype occupies an area of 275 mil/sup 2/. It works with a 5-V supply and can drive more than 4.2 V (peak to peak) in to 300 Omega with a total harmonic distortion of less than 0.025%.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>