CMOS Analog Multiplier Research Articles

Four-quadrant CMOS analogue multiplier

The letter describes a new four-quadrant CMOS analogue multiplier with a simple circuit configuration. This multiplier is based on the current/voltage characteristics of MOS transistors operating in the triode region. The simulation result shows less than 1% distortion for both input signals of 4Vpp when supply voltages of ± 5V are used.

Reply to "Comment on Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Linearized Trausconductance Stages"

Reply to "Comment on Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Linearized Trausconductance Stages"

Comments on `Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stages' [and reply

For the original article see ibid., vol.SC-21, no.6, p.1120-2 (1986). Recently, S.L. Wong et al, have described a CMOS four-quadrant analog multiplier based on linearized transconductance stages. The commentator points out that the `linearizing' of the Y-input port is unnecessary and does not offer any advantage over using a simple differential pair for the Y-input. The right approach for improving the Y-input dynamic range would be to try to increase the input signal range of the simple differential pair without altering the nature of its transfer characteristics. The original authors disagree, stating that the commenter's point would be valid if the input voltage (V/SUB Y/) range was only restricted by one of the input transistors entering cutoff, but that this is not so. They claim that since the multiplier requires wide X- and Y-input ranges, the use of the linearized Y-cell is necessary.

New four-quadrant CMOS analogue multiplier

The letter describes a new four-quadrant CMOS analogue multiplier with a simple circuit configuration. This multiplier is based on the current/voltage characteristics of MOS transistors operating in the triode region. The simulation result shows less than 1% distortion for both input signals of 4Vpp when supply voltages of ± 5V are used.

Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stages

A novel four-quadrant CMOS analog multiplier has been designed and integrated using linearized differential stages as basic building blocks. The multiplier offers high input resistance and linear input ranges of /spl plusmn/2.5 V for a supply voltage of /spl plusmn/5 V. A 3-dB bandwidth of at least 1.6 MHz is attainable for either input.