CMOS Analog Multiplier Research Articles

Fast CMOS Analog Multiplier and Divider With Continuous-Time Inverter-Based Flash Digitizer

Fast CMOS Analog Multiplier and Divider With Continuous-Time Inverter-Based Flash Digitizer

A four quadrant high-speed CMOS analog multiplier based on the flipped voltage follower cell

In this work the design and implementation of a High-Speed Four-Quadrant CMOS Analog multiplier is presented. The proposed multiplier uses the Gilbert cell as the main core. However, instead of processing both input and output signals in voltage or current mode, the “x” input signal is applied in voltage mode while the “y” input signal and “o” output signal are processed in current-mode. This approach is achieved by means of using very-low-impedance nodes at the “y” and “o” ports which also helps to enhance the overall bandwidth of the proposed multiplier. Both very-low-impedance nodes are implemented using the Flipped Voltage Follower (FVF) as high-speed high-performance low-voltage current mirror. The implemented circuit shows a bandwidth of 260 MHz for a 50Ω‖30pF load, presents a 1.5% THD at 100 MHz, and consumes 7.5 mV using a ±1 V symmetric power supply. In order to validate theory and simulations, a prototype of the multiplier was fabricated and tested using a 0.5 μm CMOS standard fabrication process; a silicon area consumption of 520 μm × 70 μm was observed. Measurements shows that the proposed multiplier is suitable for its implementation in the low corner of the Very High Frequency (VHF) band.

An Efficient Architecture for Accurate and Low Power CMOS Analog Multiplier

A new analog four-quadrant multiplier in CMOS technology is proposed using translinear loops (TLs). The novelty of the work includes an improved structure resulting in high precision output, low power consumption and low body effect error. The higher accuracy is achieved using a symmetrical arrangement of the proposed multiplier, where the errors on the two sides of circuit are subtracted from each other. The simple structure, as well as the sharing bias branch in the squaring circuits, leads to the low power dissipation of the multiplier circuit. In addition, the proposed circuit is thoroughly analyzed in terms of the body effect error and the results are presented. In order to validate the performance of the circuit, the designed multiplier is used in two useful applications: frequency doubler and amplitude modulator. The post layout simulation results of the circuit are performed using Cadence Virtuoso and HSPICE with level 49 parameters (BSIM3v3) of TSMC 0.18[Formula: see text][Formula: see text]m technology. The results show a nonlinearity of 0.93%, a total harmonic distortion (THD) of 0.98% at a frequency of 1[Formula: see text]MHz, a [Formula: see text]3[Formula: see text]dB bandwidth of 736[Formula: see text]MHz and a maximum power dissipation of 0.0619[Formula: see text]mW.

A compact four quadrant CMOS analog multiplier

The design of a very compact four quadrant CMOS analog multiplier is presented. The circuit has a very simple design, consisting of only four transistors and ten resistors, enabling a very small silicon area consumption. Furthermore, the multiplier can work in both subthreshold and saturation region, allowing it to operate over a wide range of frequencies. Subthreshold biasing sets the multiplier into a low-frequency low-power mode, while saturation biasing sets the multiplier to a high-frequency high-power mode. These two modes can be implemented for a very low voltage power supply. Finally, the proposed multiplier uses a minimum amount of nodes, allowing it to operate at high frequencies. Simulations show a maximum operating frequency of 300 kHz @ CL=30pF, a THD of ≈1% for an input sine wave of 100 mV and DC = 800 mV, and a minimum power supply of (VDD-VSS)≈0.5V when operating in the sub threshold region. In order to validate theory and simulations, a prototype of the proposed multiplier was fabricated using ON SEMI 0.5 μm technology, showing its feasibility.

A new strategy to design low power translinear based CMOS analog multiplier

This paper deals with a new method to design CMOS analog multiplier which operates in four quadrants. The main core of the proposed multiplier circuit consists of two common pairs of translinear loops which make a symmetrical configuration for the multiplier circuit. This property minimizes the error, because the resulted error in two squarer circuits are subtracted from each other, then the precision is increased. Also, the shared bias branch in the multiplier circuit causes to consume low power in comparison with conventional structures. In other word, both of the squarer circuits use single bias branch instead of two. The post layout of the circuit is designed and simulated using Cadence and HSPICE software, with TSMC and level 49 parameters (BSIM3v3) in 180 nm technology. The simulation results demonstrate a linearity error of 0.69%, a THD of 0.97% in 1 MHz, a -3dB bandwidth of 623 MHz and a maximum power consumption of 92.34 μW.

New CMOS Current-Mode Analogue to Digital Power Converter

The paper presents a completely new realization of a current-mode power detector employing a four-quadrant CMOS analogue multiplier, integrator, zero-crossing detectors and a grounded capacitor. Based on the value of the integration of the original input signals, a calculation is performed using the definition formulas. The product of input current signals was directly introduced into the integration circuit, and its digital equivalent was subsequently formed. Signal-processing-related errors and errors bound were investigated and presented in the paper. Simulation, performed using HSPICE with $$0.25\,\upmu \hbox {m}$$0.25μm technology, and experimental results confirmed the performance of the proposed circuit. The obtained results show that the scheme improves the detector's accuracy to over 1 %, while widening the operating frequency range to up to 100 MHz. The maximum power consumptions of converter at ±2.5 V supply voltages amount to approximately 8.37 mW.

Low-power high-sensitivity spike detectors for implantable VLSI neural recording microsystems

A spike detector has become a necessity of a contemporary multichannel neural recording microsystem for data-compression. This paper proposes two spike detection algorithms, frequency-enhanced nonlinear energy operator (fNEO) and energy-of-derivative (ED), to solve the sensitivity degradation suffered by the conventional nonlinear energy operator (NEO) at the presence of large-amplitude baseline interferences. The efficiency of NEO, fNEO and ED algorithms are evaluated with Simulink programs firstly and then implemented into three low-power spike detectors with a standard 0.13- $$\mu m$$ μ m CMOS process. To achieve a low-power design, subthreshold CMOS analog multipliers, derivatives and adders are developed to work with a low supply voltage, 0.5 V. The power dissipation of the proposed fNEO spike detector and ED spike detector are only 258.7 and 129.4 nW, respectively. The quantitative investigation shown in the paper indicates that both fNEO and ED spike detectors achieves superior performance than the conventional NEO spike detector. Considering its lowest power dissipation, the ED spike detector is selected for our application. Further statistical evaluations based on the true positive and false positive detection rate proves that the ED spike detectors achieves higher detection rate than that of the conventional NEO spike detector but dissipates 48 % less power.

Design of Integrated Four Quadrant Analog Multiplier

CMOS analog multiplier can be widely used in the filter, mixing or other signal processing circuits, as well as the control system of electronic circuit. This paper shows a design of one analog multiplier, using Gilbert unit as the main part. Our results show that, when the input voltage is between -4V and 4V, Vx and Vy exhibit excellent DC characteristic and well FM and AM characteristic. In addition, Frequency Doubling characteristic are good. Quiescent current is 2.16mA. Especially the value of THD in the same conditions compared to other design is lower. Circuit simulation, layout drawing and authentication software use Virtuso, Spectre, Caliber respectively which integrated in Cadence system. Final schematic and layout have passed DRC, LVS verification.

A new high speed and low power four-quadrant CMOS analog multiplier in current mode

In this paper a new CMOS current-mode four-quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3 V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 μ m standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.1%, a THD of 0.97% in 1 MHz, a - 3 dB bandwidth of 41.8 MHz and a maximum power consumption of 0.34 mW.

A low-power CMOS analog multiplier

A multiplier is an important component for many analog applications. This paper presents a low power CMOS analog multiplier with performance analysis and design considerations. Experiments with SPICE simulation and results from chip testing show that this new structure has extremely low power consumption with comparable linearity and noise performance, making it very attractive for use in a variety of analog circuits.

A low-power low-noise CMOS analogue multiplier

A low-power and low-noise analogue multiplier operating with 1.5 V supply voltage is presented. The core structure consists of only six transistors and brings in the benefits in terms of linearity, power consumption and noise performance. Some design considerations are also provided. The extensive experiments with SPICE simulation show that this new structure is particularly attractive for low-power and low-noise applications in comparison with other previously reported structures.

On the design of low-voltage, low-power CMOS analog multipliers for RF applications

Novel low-voltage, low-power techniques in the design of portable wireless communication systems are required. Two system examples of low-power analog multipliers operating from a 1.2 V supply are presented. These proposed structures achieve the required multiplication function by using current processing. The circuits were fabricated using standard double-poly CMOS processes for a 900 MHz application. Measurement results of the prototypes are comparable to other higher voltage designs.

CMOS Analog Implementation of a Discrete-Time 9-Tap FIR Filter with Circular Buffer Architecture

This paper presents the design and simulation of a 9-Tap CMOS Analog Discrete-Time Finite Impulse Response (FIR) Filter system. This unique design features a Circular Buffer Architecture which achieves high sampling rate that can be easily expanded to improve speed and extended to higher order filters. Novel area-efficient four quadrant CMOS analog adder and multiplier circuits are employed to respond for high frequency and wide linear range inputs. The layout for all circuits has been realized using the design tool MAGIC with a 1.2 μm CMOS process. The performance for each circuit and the whole system are characterized using HSPICE simulation based on the extracted MAGIC netlist. The 9-tap filter was designed to achieve 5 MHz sampling rate. The implemented design requires a total chip area of 1690.9 μm by 2134.2 μm and ±5 volt power supply.

A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect

This paper proposes a novel CMOS analog multiplier. As its significant merit, it is free from mobility reduction and body effect. Thus, the proposed multiplier is expected to have good linearity, comparing with conventional multipliers. Four transistors operating in the linear region constitute the input cell of the multiplier. Their sources and backgates are connected to the ground to cancel the body effect. Their gates are fixed to the same bias voltage to remove the effect of the mobility reduction. Input signals are applied to the drains of the input cell transistors through modified nullors. The simulation results show that THD is less than 0.8% for 0.6 V_p-p input signal at 2.5 V supply voltage, and that the 3 dB bandwidth is up to about 13.3 MHz.

A four-quadrant subthreshold mode multiplier for analog neural-network applications

A new four-quadrant CMOS analog multiplier is presented, based on devices operating in the subthreshold mode of conduction. The proposed circuit is a cross-coupled quad structure in which differential multiplication is obtained by driving the gate and bulk (back gate) terminals of the devices. Analysis and simulation have shown that the new structure has the characteristics required for the design of very large scale integration (VLSI) analog neural networks. Although operating at subthreshold current levels, reasonable speed can be obtained since voltage swings are in the range of a few V(t). The behavior of the basic multiplier has been assessed experimentally using transistor-arrays and simulation studies on a network including 11 neurons and 31 synapses indicate a useful level of functionality.

Four-quadrant CMOS analogue multiplier for artificialneural networks

A four-quadrant CMOS analogue multiplier is presented. The proposed multiplier has large dynamic input range, good linearity and can provide either a differential output current or voltage. These properties make the multiplier very suitable for use in the implementation of artificial neural networks.

Design and applications of a CMOS analog multiplier cell using the differential difference amplifier

This paper presents design techniques for a wide input range CMOS differential difference amplifier (DDA) and discusses its application as a basic block in the implementation of a simple four-quadrant multiplier cell. The cell can be configured as an amplitude modulator or a one-over circuit, which are widely used in many analog signal processing applications. The DDA can also be reconfigured as an opamp, and hence can be used to design many of the opamp-based multiplier circuits. The DDA amplitude modulator (AM) uses a transistor and a resistor as the only components external to the DDA. A DDA one-over circuit, which provides an output proportional to the inverse of the input, is also achieved with the same level of simplicity. High-frequency effects due to the DDA's finite gain-bandwidth (GB) and MOS parasitic capacitances are investigated. Experimental results obtained from a 2µm CMOS MOSIS chip are given.

A four-quadrant CMOS analog multiplier for analog neural networks

A four-quadrant CMOS analog multiplier is presented. The multiplier uses the square-law characteristic of an MOS transistor in saturation. Its major advantage over other four-quadrant multipliers is its combination of small area and low power consumption. In addition, unlike almost all other designs of four-quadrant multipliers, this design has single ended inputs so that the inputs do not need to be pre-processed before being fed to the multiplier, thus saving additional area. These properties make the multiplier very suitable for use in the implementation of artificial neural networks. The design was fabricated through MOSIS using the standard 2 /spl mu/m CMOS process. Experimental results obtained from it are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High frequency wide range CMOS analogue multiplier

A new CMOS analogue cell which can be used to implement a four-quadrant multiplier circuit is introduced. Simulation results of the circuit using the MOSIS 2μm process parameters are given. The circuit has an input range of ±4V and linearity error less than 1% for inputs up to ±3V. The magnitude and phase response are very flat; even at 30MHz the change in the magnitude is less than 0.086dB (1%) and the phase shift is less than 5°.

A ±5-V CMOS analog multiplier

A four-quadrant CMOS analog multiplier is presented. The device is nominally biased with /spl plusmn/5-V supplies, has identical full-scale single-ended x and y inputs of /spl plusmn/4 V, and exhibits less than 0.5% nonlinear error at 75% of full-scale swing. Operation with supplies as low as /spl plusmn/2.5 V is also possible. A comparison of theoretical and experimental results obtained from fabrication of the multiplier in a 3-/spl mu/m p-well CMOS process is made.