The widespread adoption of Internet of Things (IoT) systems has created a strong need for cryptographic solutions that are both secure and energy-efficient, especially due to limited power and hardware resources. This work presents a low-power design of an Advanced Encryption Standard (AES) cryptographic chip that utilizes clock gating techniques to reduce dynamic power consumption. By selectively disabling the clock signal to inactive sections of the circuit, unnecessary switching activity is minimized, leading to improved energy efficiency without affecting overall system performance. The proposed system features a hardware-based AES encryption module designed for efficient operation with reduced power usage while still ensuring high data throughput and robust security. The architecture is described using a hardware description language and implemented on an FPGA platform to analyse key performance parameters, including power consumption, area requirements, and timing characteristics. A comparative evaluation shows that the integration of clock gating significantly lowers power usage when compared to traditional AES implementations lacking such optimization. The findings demonstrate that the proposed design is well-suited for IoT environments where energy efficiency is critical. It achieves an effective balance between security, performance, and power consumption, making it a practical solution for modern embedded and resource-constrained applications.

With the development of mobile communication, intelligent healthcare, self-driving technology, and other application fields, as well as advances in IC and semiconductor devices, numerous integrated systems have imposed increasingly stringent requirements on clock signal quality. The phase-locked loop (PLL) is the mainstream architecture for clock generation at present, and PLL featuring low spur, low noise, and low power consumption has become key design objectives for researchers in recent years. Based on existing research, this paper will provide an overview of two distinct types of PLL architectures, namely the conventional charge-pump phase-locked loop (CPPLL) and the sub-sampling phase-locked loop (SSPLL), and elaborate on their relationship in terms of inheritance and evolution. By briefly introducing their operating principles, circuit architecture and operating characteristics, this paper will demonstrate the merits of SSPLL in generating low-jitter clock signals, and present some key design techniques adopted in the implementation of both types of PLLs. Through the paper, it can be concluded that the mainstream research directions for PLL improvement are mainly focused on three core aspects: the optimization design of voltage-controlled oscillator (VCO), the circuit design of the phase detector/ charge pump (PD/CP), and the dead-zone design.

Circadian clocks have long been hypothesized to tightly link cellular and physiological processes to the appropriate time within the 24-hour cycle of the Earth's daily rotation. According to this hypothesis, circadian rhythms with cycle lengths that differ significantly from 24 hours would be disadvantageous, as they would generate a desynchronization between the endogenous and exogenous cycles that would place stress upon an organism through the required daily resetting at dawn. However, recent work has demonstrated that endogenous circadian cycles that differ from 24 hours by 2 hours or more are prevalent within the green lineage. Herein, we review recent work on the prevalence of, and adaptive advantages associated with, natural variation in circadian cycles. Based on known photoperiodic sensing mechanisms we also describe a set of principles that allow the same changes in circadian period to cause different plant responses. This fine-tuning of clock output pathways provides a flexible mechanism enabling plants to use a wide range of life history strategies for plant adaptation to different environmental niches. Further studies are needed to determine how variations of the clock and other signals are integrated in different plants. These studies highlight the circadian clocks' position as a prime adaptation target for migration of plant species into new environmental ranges.

This paper proposes an external frequency synchronization control circuit for DC-DC converters, in which the frequency synchronization pin (SYNC) is shared with the enable pin (EN),enhancing chip compactness and reducing cost. The chip's enable state is not affected by the external clock signal. An internal phase-locked loop (PLL) ensures the continuity of the switching frequency variation, thereby avoiding output voltage overshoot caused by abrupt frequency changes. The chip supports a frequency synchronization ranging from 200 kHz to 2.4 MHz and is implemented using SK hynix's 0.18 μm BCD process. Test results show that the maximum output voltage overshoot is 58 mV with a 1 A load current and 1 MHz synchronization.

The tracking system of the ATLAS experiment will be upgraded for the upcoming High-Luminosity Upgrade of the LHC (HL-LHC). The main building blocks of the new strip tracker are silicon-stripmodules that consist of a sensor and hybrid PCB's. The modules are mounted on rigid carbon-fibre substructures,the so-called staves (petals) in the barrel (end-cap) regions, that provide common services to the modules. At the end of each stave or petal side, a so-called End-of-Substructure (EoS) card facilitates the transfer of data, power, and controlsignals between the modules and the off-detector systems. The EoS connects up to 28 data lines, each with 640 Mb/s, from the modules to one or two lpGBT chips that provide data serialization and use a10 Gb/s versatile optical link (VL+) to transmit signals to the off-detector systems. The lpGBT also recovers the LHC clock on the downlink and generates clock and control signals for the modules.To meet the tight integration requirements in the detector, fourteen different EoS card designs are necessary. The power to the EoS is provided by a dedicated dual-stage DC-DC package providing 2.5and 1.26 V to the EoS cards. A first production of almost 2000 EoS cards has been stopped due to the errors found in the lpGBT-v1 ASIC, but all accompanying DC-DC converters have been produced.We report on the production experience including detailed QC statistics and design validation (QA) results for the EoS itself with the lpGBT-v1 ASIC and how the two lpGBT issues were identifiedand how many EoS boards were affected by each. With the lpGBT-v2 ASIC now in hand, we report first QC results with the second production iteration.

Precise time synchronization among multiple electronic channels is essential for nuclear physics experiments. In digital data acquisition systems based on XIA Pixie-16 modules, the relative timing between channels is not necessarily preserved when a new data acquisition run is started. A run-dependent timing offset — typically on the order of 10 ns — can occur independently in each channel, which cannot be corrected through offline data analysis alone. To address this issue, a dedicated external electronic circuit is developed. This circuit operates as a programmable double-throw switch that routs a common reference clock signal to all channels at the start of each run, before switching to normal physics data acquisition. This procedure enables direct measurement and thus correction of relative timing offsets for all channels on a run-by-run basis without manual intervention. The method has been successfully applied in a nuclear reaction experiment using multiple Pixie-16 modules, where it effectively corrects the run-dependent timing offset and thus significantly improves the accuracy of timing-dependent observables such as Parallel Plate Avalanche Counter(PPAC) position reconstruction and beam tracking.

The CONSTANS, CONSTANS-like, and TIMING OF CAB EXPRESSION 1 (CCT) domain proteins are key regulators of flowering time and circadian rhythms in annual plants, but their diversity and temporal expression patterns in perennial trees remain poorly understood. Here, we performed a genome-wide characterization of CCT family genes and analyzed their seasonal and circadian expression dynamics in Populus. Using an HMM-based search, we identified 49 putative CCT genes (PtCCTs) in the Populus genome and classified them into five subfamilies (COL, CMF, PRR, ALSM and ZIM) based on domain composition and phylogeny. Synteny and duplication analyses showed that most PtCCTs arose from segmental duplication and have predominantly evolved under purifying selection. Promoter analyses revealed a rich repertoire of cis-regulatory elements, with a marked enrichment of light- and hormone-responsive motifs, particularly G-box and ABRE elements, in PtPRR and a subset of PtCOL promoters. Transcriptome data indicated that many PtCCTs display distinct tissue-specific expression patterns, with PtPRRs and PtZIMs being strongly enriched in dormant buds. Seasonal transcriptomes from leaves and shoot apices revealed discrete expression profiles associated with growth, bud set, and winter dormancy, and most PtPRRs showed increasing transcript levels from September to December. Diurnal time-series data further identified 19 PtCCTs with significant rhythmic expression, separating COL and PRR members into night- and day-phased groups. Network analysis using STRING indicated that PtPRRs interact with photoperiodic pathway components such as PtGI, and re-analysis of diurnal data from wild-type and lhy-RNAi hybrid aspen showed that several PtPRRs exhibit phase and amplitude changes when LHY expression is reduced. Together, these results provide a comprehensive overview of the CCT gene family in Populus and highlight PtPRRs and specific PtCOLs as promising candidates that link the circadian clock and light signaling to seasonal growth cessation and bud dormancy in perennial trees.

To address the discontinuity and constant bias inherent in traditional hard and soft threshold functions, an atomicclock signal denoising method based on the hyperbolic tangent smooth threshold function was proposed. The atomicclock signal was decomposed into a series of intrinsic mode functions (IMFs) and a residual component usingempirical mode decomposition (EMD). A novel threshold function was constructed to achieve a continuous transitionbetween hard and soft threshold behaviors by introducing a smoothing factor. The optimal threshold for each IMFwas determined using Stein’s Unbiased Risk Estimate (SURE) criterion, and each IMF component was denoisedaccordingly. Finally, the denoised IMFs and the residual component were reconstructed to obtain the fi nal denoisedsignal. Case study analyses demonstrated that, in comparison with traditional wavelet threshold denoising methods,the proposed method suppressed noise eff ectively while preserving the smoothness and detailed features of thesignal more favorably. Specifi cally, in terms of noise suppression, the improved thresholding method increased theSNR by 14%, 5% and 26% for cesium clock, hydrogen clock and measured rubidium clock data. In terms of signalfi delity, its RMSE was reduced by 28%, 10% and 25% relative to the soft thresholding method. This method retainedthe authentic information of the signal while suppressing noise, and exhibited good repeatability. It eff ectivelyimproved the frequency stability of the time scale, thereby providing a novel technical approach for enhancing thequality of atomic clock data and the frequency stability of the time scale.

Abstract Thin-film transistors based on amorphous indium-gallium-zinc oxide (a-IGZO) fabricated on flexible substrates offer a high-performance platform for implementing low-power digital circuits. The combination of high electron mobility, low leakage current, and excellent electrical stability enables the realization of fundamental sequential logic elements. This work presents the design and implementation of a low-transistor-count D-type flip-flop utilizing only 14 N-channel MOSFETs operating from a 5 V supply. The circuit is characterized with a 100 MHz data input (D) and a 200 MHz clock signal (CLK), both exhibiting a 3 V peak swing. Electrical characterization demonstrates stable operation with suitable performance metrics, confirming the viability of this technology for integration into more complex digital architectures and emerging applications in flexible and transparent electronics.

Abstract The global navigation satellite system (GNSS) is essential for timing and positioning. In conventional receivers, clock offset is treated as a common error and often lacks careful modeling. However, accurate clock state estimation is crucial in GNSS-based remote timing. Current methods typically model clock error as white noise, which can amplify estimation noise in both the up-coordinate and clock states under certain conditions. Incorporating clock modeling has the potential to mitigate such noise. This study explores the theoretical foundations of clock modeling and examines its influence on GNSS positioning and timing performance. We establish the GNSS timing model and the clock signal model, and clarify the relationship between Allan Variance and the diffusion coefficient. Using a small Rubidium atomic clock and an oven controlled crystal oscillator (OCXO) as examples, we evaluate the effect of clock modeling on frequency offset estimation noise and vertical positioning precision. Theoretical and experimental results demonstrate that clock modeling significantly reduces frequency offset estimation noise, with noise attenuation ranging from 17.19% to 52.83% for OCXO and 87.67% to 97.83% for the Rubidium clock. More stable clocks exhibit greater improvement. Additionally, clock modeling enhances short-term up-coordinate positioning stability, showing improvements of 78.74% for OCXO and 84.23% for the Rubidium clock at 1 s intervals. These findings highlight the potential of clock modeling for rapid online frequency monitoring and improved GNSS timing and positioning performance with OCXOs and compact atomic clocks.

The circadian clock is a crucial regulator of life activities in insects, directly influencing survival competitiveness and population expansion. Cryptochrome-1 (Cry1), a core circadian clock gene, is functionally diverse in insects. Phylogenetic analysis revealed that Bactrocera dorsalis Cry1 (BdCry1) clusters closely with Drosophila melanogaster Cry1 (DmCry1), suggesting potential functional conservation. Subsequent expression profiling demonstrated that BdCry1 exhibited robust circadian oscillations and undergoes significant expression fluctuation near the time of adult eclosion in B. dorsalis. To elucidate the functional role of BdCry1, we generated a knockout strain (BdCry1-/-) via CRISPR/Cas9-mediated mutagenesis. BdCry1-/- flies exhibited delayed eclosion timing and disrupted eclosion rhythmicity. Additionally, qPCR revealed significant changes in the transcriptional expression of key neuropeptide genes, including sNPF, PDF, and PTTH. Circadian monitoring of ecdysone (20E) titers by ELISA demonstrated a loss of rhythmic 20E fluctuations and significantly reduced 20E in BdCry1-/- pupae compared to those in the wild-type (WT) controls. Moreover, RNA interference-mediated knockdown of the ecdysone receptor also disrupted eclosion rhythms in WT, confirming the link between eclosion and 20E signaling. Our findings uncovered a molecular connection between the circadian clock (via Cry1) and 20E signaling in the regulation of eclosion rhythms. These results provide novel insights into the integration of hormonal and circadian systems in insects and identify potential molecular targets for the development of biocontrol strategies. © 2025 Society of Chemical Industry.

High-speed data acquisition systems based on field-programmable gate arrays (FPGAs) often face synchronization challenges when interfacing with commercial analog-to-digital converters (ADCs), particularly under constrained hardware routing conditions and vendor-specific clocking assumptions. This work presents a vendor-independent FPGA–ADC synchronization architecture that enables reliable and repeatable high-speed data acquisition without relying on clock-capable input resources. Clock and frame signals are internally reconstructed and phase-aligned within the FPGA using mixed-mode clock management (MMCM) and input serializer/deserializer (ISERDES) resources, enabling time-sequential phase observation without the need for parallel snapshot or delay-line structures. Rather than targeting absolute metrological limits, the proposed approach emphasizes a reproducible and transparent data acquisition methodology applicable across heterogeneous FPGA–ADC platforms, in which clock synchronization is treated as a system-level design parameter affecting digital interface timing integrity and data reproducibility. Experimental validation using a custom Kintex-7 (XC7K325T) FPGA and an AFE7225 ADC demonstrates stable synchronization at sampling rates of up to 125 MS/s, with frequency-offset tolerance determined by the phase-tracking capability of the internal MMCM-based alignment loop. Consistent signal acquisition is achieved over the 100 kHz–20 MHz frequency range. The measured interface level timing uncertainty remains below 10 ps RMS, confirming robust clock and frame alignment. Meanwhile, the observed signal-to-noise ratio (SNR) performance, exceeding 80 dB, reflects the phase–noise-limited measurement quality of the system. The proposed architecture provides a cost-effective, scalable, and reproducible solution for experimental and research-oriented FPGA-based data acquisition systems operating under practical hardware constraints.

In the article examines the problem of visual information leakage through channels of side electromagnetic radiation of video paths of computing systems. It is shown that the effectiveness of developing information security methods is directly related to an understanding of the mechanisms for intercepting and recovering visual data from SER. It is noted that the information recovery procedure is a multi-stage process, including SER reception, clock and synchronization signal recovery, signal filtering and threshold processing, data bit recovery, and image reconstruction with an increased signal-to-noise ratio. Based on an analysis of the recovery sequence, it is established that the key stage of the process is the recovery of the video path clock signal, since other synchronization signals are formed on its basis. It is concluded that this stage must be taken into account when developing new methods and tools for protecting information from leakage through SER channels.

Compared with single-edge designs, dual-edge-triggered flip-flops (DETFFs) can maintain the same data throughput while operating at half the clock frequency. However, when integrating ferroelectric nonvolatile structures with selector-based DETFFs, the uncertain logic levels of the clock and data signals during the restore phase may lead to unintended ferroelectric field-effect transistor(FeFET) programming. In addition, conventional C-element-based flip-flops suffer from limited performance. To address these issues, this paper presents an input C-element design that enforces input isolation by generating complementary outputs during the restore process, along with an improved output C-element. Experimental results show that, compared with existing C-element-based flip-flops, The proposed design reduces operating power by at least 33.3%, and decreases hold time by at least 58.8%. In addition, the clock-to-Q delay is reduced by at least 9.2%. The proposed flip-flop is capable of storing its output state prior to power-off and effectively isolating both data and clock signals during restoration, enabling accurate recovery of the pre-shutdown state while improving C-element performance.

As data transmission rates escalate across successive generations, the impact of timing jitter on the performance of high-speed systems becomes increasingly significant. Moreover, jitter is exacerbated by frequency-dependent channel characteristics as signals propagate through the interconnects. In this paper, an analytical methodology based on phase noise theory is proposed to accurately quantify the random jitter amplification factor in clock signals. To ensure the high accuracy, the proposed method incorporates the higher-order spectral components of the clock waveform rather than relying on sinusoidal approximations. Extensive simulations and empirical measurements conducted on transmission lines and 5th-generation double data rate (DDR5) channels validate the effectiveness and precision of the proposed approach. This methodology provides essential insights into jitter mitigation strategies pertinent to high-speed channel design.

A 0.52% nonlinearity, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$44.9zF/\sqrt {Hz}$</tex-math> </inline-formula> input capacitance noise capacitance-to-voltage (C/V) converter for MEMS accelerometer is proposed in this study. The multi-step successive approximation (SA) output mechanism is proposed to replace the conventional single-step conversion. Meanwhile, combining with the modulation-demodulation (MD) technique in the traditional continuous-time (CT) C/V converter, a much lower nonlinearity and noise CT C/V converter without increasing power consumption is achieved in this work. In addition, a short time reset signal between modulation and demodulation is proposed to reset the integration capacitors in each conversion cycle, which lets the C/V converter achieve an approximate twice dynamic range enhancement (DRE). The proposed C/V converter is implemented in a standard 180 nm CMOS process. It incorporates an on-chip capacitor signal generator (CSG), whose capacitance is tuned from −80 fF to 80 fF using clock signals at frequencies of 10Hz, 1 kHz, 2 kHz, 3 kHz, 4 kHz, and 5 kHz respectively, where measurement results demonstrate that the converter has correct output voltage across this frequency range, with a conversion error of less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$350~ppm/\sqrt {Hz}$</tex-math> </inline-formula>. The proposed C/V converter is also tested together with an integrated a MEMS accelerometer element. It achieves a maximum nonlinearity as low as 0.52% within ±10 g acceleration and obtains equivalent input noise power spectral density (PSD) as low as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$44.9~zF/\sqrt {Hz}$</tex-math> </inline-formula> when the frequency is beyond 50 Hz.

Any digital system on very large scale integrations requires clock distributions. For the realization, a dedicated clock tree or a mesh clock is frequently used. Field programmable gate arrays have numerous general-purpose programmable wires based on switching matrices to connect the outputs and inputs of look-up tables and input/output ports. However, field programmable gate arrays never use numerous general-purpose programmable wires for their clock distributions as well as other very large scale integrations to satisfy with the clock skew margin. Field programmable gate arrays also take the dedicated clock trees although the programmability is not high. Currently, field programmable gate arrays can support multiple dedicated clock routing or multiple clock trees. However the number of clock trees is fixed and limited to a small number. Even if application requires a lot of clock distributions, the clock distribution cannot be supported in current field programmable gate arrays. Therefore, this paper proposes a more flexible clock distribution method using general-purpose programmable wires based on wiring channels and switching matrices. In addition, to solve clock skew increase problem, we have introduced a new flip-flop with a two-phase clock signal. This paper presents the simulation results of the proposed clock distribution method on an originally designed filed programmable gate array. In addition, this paper also presents the experimental results that the proposed clock distribution method can work correctly on a Cyclone V field programmable gate array.

In Global Navigation Satellite Systems, accurate and stable atomic clocks need to be equipped on satellites to ensure reliable, high-accuracy positioning, navigation, and timing services. It is essential to continuously monitor the behavior of satellite clocks in space and predict satellite clock correction for real-time Global Navigation Satellite Systems applications especially for precise point positioning. Some commercial software is available for clock characterization, but special attention has to be paid when referring to satellite clocks, the analysis and prediction of which may be complicated by outliers, data gaps, and periodic fluctuations in onboard clock data, not often encountered by clock data from a timekeeping laboratory. The typical approaches for clock characterization and prediction currently employed in a timekeeping laboratory are therefore unsuitable for clock applications in space. We present a software package developed in MATLAB at the National Time Service Center, intended for satellite clock characterization and prediction. The software package includes many subroutines and functionalities of particular interest in characterizing and predicting clock behavior in space, such as dynamic frequency stability evaluation, periodic fluctuation analysis, and multi-step prediction of clock signals. The software package allows handling of satellite clock data directly from Receiver Independent Exchange Format clock files widely used in Global Navigation Satellite Systems, facilitating quick characterization analysis and prediction of satellite clocks, with graphically visualized output.

A high-frequency reference clock (CKREF) adopted in charge-pump-based phase-locked loops (CPPLLs) can reduce the feedback division factor, thereby alleviating the noise influence from the phase/frequency detector (PFD), charge pump (CP), and loop filter (LF). However, the PFD, serving as the front end of CPPLLs, suffers from an enlarged blind zone (BZ) that consequently reduces its average gain (KPFD) during high-frequency operation. To address this issue, this work proposes two pulsed-latch-based PFDs (PLPFDs) that mitigate the BZ and enhance KPFD. Through analysis of the relationship between the clock frequency (fCK), the reset loop delay, and the pulsewidth of the clock signal, these two PLPFDs can operate in either a higher-fCK mode or a lower-BZ mode, depending on whether pulse generators (PGs) are used. Implemented using a 0.18-μm CMOS process, HSPICE simulation results demonstrate an operating frequency range of 1.8-3.4 GHz with lower power consumption in the higher-fCK mode, and 0.5-1.7 GHz with a minimized BZ of 0.010-0.027 π in the lower-BZ mode. In particular, these PLPFDs can be readily integrated into CPPLLs that employ various high-frequency CKREF, enabling fast acquisition for advanced communication systems.

MuClock is a commercial transportable microwave clock developed at Exail Quantum Systems, using rubidium atoms cooled by isotropic laser light. MuClock is comparable with typical hydrogen masers in terms of volume and long-term frequency stability, as it nominally reaches a fractional frequency stability of 1 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−15</sup> in less than two days and maintains this level of performance over more than one month of integration time. The evaluation of several systematic frequency shifts is on-going. This article presents the impact of the frequency bias induced by microwave phase transients on the clock frequency stability and accuracy. Using an in-house designed test bench, the phase of the 6.8 GHz microwave clock signal is measured with a phase resolution close to 1 μrad and a temporal resolution below 100 ns. It enables a thorough optimization of the sequence and a better control of each phase transient event, making their contributions to the overall frequency shift negligible. The accuracy of the associated systematic effect is evaluated at 3 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−15</sup>.