Clock Generator Research Articles

A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68

This work presents an ultralow-jitter ring-oscillator (RO)-based injection-locked clock multiplier (ILCM). Using the power-gating (PG) injection method that can completely remove the accumulated phase error of the RO, the proposed ILCM can achieve a very wide injection bandwidth, and, thus, an ultralow-jitter, even when the multiplication factor, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${N}$ </tex-math></inline-formula> , is increased above 60. To overcome the natural limitation of the PG injection, two digitally controlled oscillators (DCOs) were used to operate in a complementary manner. Since the background multi-functional calibrator (MFC) continuously synchronizes the outputs of the two DCOs, the PG-ILCM can generate a seamless output signal by combining these two signals. The proposed injection pulsewidth controller (IPWC) decreased the required delay of the digital-to-time converter (DTC), further reducing the jitter of the output signal. A phase-rotational divide-by-4 divider (PR-DIV4) also was proposed to reduce the operating frequency and the power consumption of the MFC while maintaining the fine resolution of the output frequency. The PG-ILCM, fabricated in a 65-nm CMOS process, used the power of 14.3 mW and an area of 0.102 mm2. The rms jitter measured at 8.16 GHz ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N = 68$ </tex-math></inline-formula> ) was 97 fs.

Dual-Band 802.11ax Transceiver Design With 1024-QAM and 160-MHz CBW Support

A 2W2 802.11ax transceiver design is presented to support dual band simultaneous operation (DBS) and 1024-QAM modulation. The proposed architecture features linearity enhancement for uplink OFDMA and wideband transmission. With integrated low phase noise clock generation and PLL, bestin-class receiving sensitivity and lowest transmission EVM floor are demonstrated through measurements. With 20MHz (HE20) receiving, -96.5dBm/-66dBm sensitivity level is measured for MSC0/11, respectively. The output power reaches 18dBm with -35dB EVM for 80MHz 1024-QAM (HE80 MCS11) transmission at 5GHz band. Narrowband OFDMA signals can be transmitted at full power capacity, and 160MHz channel bandwidth (CBW) can also be supported without digital predistortion (DPD). The fully integrated transceiver occupies 10.5 mm2 silicon area in 22nm CMOS.

Radiation-tolerant all-digital clock generators for HEP applications

The emergence of high-precision timing systems in High Energy Physics motivates new developments in the domain of clock generation and distribution. Particularly, when considering the challenges arising from adopting advanced deep-submicron CMOS technology nodes, all-digital PLL and clock and data recovery (CDR) architectures constitute a promising option for future high energy physics (HEP) experiments. Both LC oscillator and ring oscillator-based all-digital PLL/CDR blocks for front-end ASICs were studied, designed, manufactured and characterized. Their design, the hardening considerations, as well as the performance obtained with these circuits are presented in this article.

BUILT-IN SELF-TEST AND SELF-CORRECTION METHOD FOR MIXED-SIGNAL INTEGRATED CIRCUITS

In modern integrated circuits the number of devices have strongly increased. As a result, identifying the issues which have an impact on their performance stands out as a very complicated and challenging problem. In digital integrated circuits there are methods which are known, as well as some others which are in the active development stages targeted to enable the built-in self-tests, identify, and report those issues. At that, for mixed signal circuits, where the calculations or functions are performed based on the voltage levels, it is much complicated to develop self-testing mechanisms. A novel method of identifying the lack of clock signal and its duty cycle variation is proposed in this paper. The developed architectures and solutions are capable of detecting the lack of the clock signals, as well as informing the digital parts of the systems about the requirement for the coarse or fine tunings of the clock generation systems outside their autocalibration and loops.

Timing and synchronization of the DUNE neutrino detector

The DUNE neutrino experiment far detector has a fiducial mass of 40 kt. The O(1M) readout channels are distributed over the four 10 kt modules and need to be synchronized with respect to each other to a precision of O(10 ns). The entire system needs to be synchronized with respect to GPS time to O(100 ns). The system needs to be reliable, simple and affordable. Clock and synchronization information are encoded on the same fibre using a protocol based on duty cycle shift keying (DCSK) with 8b10b encoding to ensure DC-balance. The use of DCSK allows the clock to be recovered directly by PLL based clock generators without needing to use a separate clock and data recovery (CDR) device. Small scale tests show a timing jitter at the endpoint of ≈10 ps with respect to the timing master.

INVESTIGATING THE ERRORS OF A DIGITAL METER OF RC-TWO-POLE PARAMETERS

A device for an invariant measurement of the electrical parameters of RC-two-pole poles based on the phase method is described. The device implements a structural-algorithmic method of increasing the accuracy of measurements with time division of the measurement channel. A programmable microcontroller (MCC) is used to control the measurement process and to process the measurement results, which allows to minimize the number of parameter and signal transformations and increase the measurement accuracy. In the measuring circuit (MC), two sample resistors are connected in series with the two-pole under study: the main and additional (switchable). The reference voltage is formed in the feedback circuit of the operational amplifier. The MC is powered by a current generator of a sinusoidal signal of a programmable frequency. The MC has two output voltages, the phase shift angle between which is an informative parameter. The output voltages of the MC are supplied to the analog inputs of the MC. In the MCC, the angle is converted into a time interval, which is measured by the discrete counting method by quantizing it with pulses of the MCC clock generator. By analyzing the MC, algorithms for determining the measured parameters are obtained. The parameters of the IC elements are calculated, at which the required measurement ranges of the investigated object parameters are provided. The main content of the article is devoted to the development of the methodology of theoretical calculation of measurement errors. The errors are caused by inaccuracy and instability of the parameters of the MC and MCC elements appearing in the obtained algorithms. The calculation technique is accompanied by numerical example applied to specific measurement ranges. It is shown that in the total errors of measurement the private error caused by the inaccuracy and instability of resistances of sample resistors used in the MC, is predominant.

Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation

Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation

A Review of Innovative Comparator Designs

Three papers on the optimal design of comparator circuits are further analyzed in this work. Each paper presents a method to improve the performance of comparators. Floating inverter amplifier applied an independent capacitor as the source of the preamplifier, which improves the overall performance of the circuit. In another design, a special local clock generator is proposed to control the input of both of the latch stage and the preamplifier, which makes it possible to adjust the speed and improve the energy efficiency. In dynamic bias circuit design, stabilized common-mode voltage is realized by adding a capacitor to the tail of the pre-amplifier of a latch-type comparator, optimizing the power and noise performance successfully.

A New Technology for Reducing Dynamic Power Consumption in 8-Bit ALU Design

Clock gating is an effective way to decrease dissipated power in synchronous design. The most effective way to do this is by masking the clock that turns toward the unused part of design. In this paper, a comparative evaluation of power consumption in existing clock gating techniques in Arithmetic Logical Unit (ALU) design was achieved. an innovative signal clock gating method offers extra immunity in the direction of the present issue in an accessible mechanism. A Gated Clock Generation designs using a tri-state connection and logic gate, generated by the set of bubbled input with NAND gate, is used for the latest suggested clock gating. This design saves power even when the clock is at applying to the target module. Complete power analysis reveals that the proposed technique has an effect on the dynamic power that decreases total power consumption up to 24.90% relative to traditional power. All experiments are done in arithmetic logic unit design. 130 nm standard logic libraries have been used for implementation in order to achieve ALU frameworks. The ALU design architecture was developed using the Verilog HDL, and the simulations are performed utilizing ModelSim-Altera 10.0c (Quartus II 11.1) Starter Version.

A Crystal-Less Clock Generation Technique for Battery-Free Wireless Systems

The size of wireless systems is required to be reduced in many applications, such as ultra-low-power sensor nodes and wearable/implantable devices, where battery and crystal are the two main bottlenecks in system miniaturization. In recent years, battery-free radios based on wireless power transfer (WPT) have shown great potential in miniature wireless systems, while a reliable on-chip clock without a crystal remains a design challenge. Conventional methods utilized the RF WPT tone as the reference for clock generation, but the high RF frequency leads to high power consumption. In comparison, using a lower WPT frequency results in an antenna with a larger size. In this work, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{\mathrm{nd}}$ </tex-math></inline-formula> -order inter-modulation (IM2) component of the two RF WPT tones is extracted to lock an on-chip oscillator, providing a low-jitter PVT-robust clock. In this way, the wireless systems can benefit from: 1) The clock recovery circuits operate at a low IM2 frequency, reducing the power consumption. 2) The WPT can be set to a high RF frequency to minimize the antenna. Fabricated in 65 nm CMOS process, the proposed crystal-less clock generator takes a small area of 0.023 mm2 in a wireless system chip. Measured results show −92 dBc/Hz@10 kHz phase noise and 6.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> power.

A Fully Integrated Multi-Phase Buck Converter With On-Chip Capacitor Dynamic Re-Allocation and Fine-Grained Phase-Shedding Techniques

This article presents a fully integrated multi-phase (MP) buck converter for on-chip power management units. A peak-and-valley differential sensing (PVDS) scheme based on a flying capacitor is proposed to evenly balance the multiple inductor currents without significant power overhead even under mismatches in inductances, parasitic series resistances, and control-signal skews among phases. In addition, dynamic re-allocation of on-chip capacitors enables an even more optimal frequency response and output ripple based on the number of activated phases. It also improves the chip area efficiency, resulting in a higher power density. The proposed DLL-based MP clock generation provides high granularity in the phase-shedding control to achieve high efficiency over a wide load range. The proposed fully integrated buck converter using six bond-wire inductors (1 nH) was fabricated in a 28-nm CMOS process. The chip running at a frequency of 400 MHz/phase can finely adjust the number of active phases by an integer step ranging from 1 to 6 through sensing a load current. A maximum power density of 1.23 W/mm2 and a peak efficiency of 83.7% were measured. This work achieved an ultra-fast dynamic voltage scaling (DVS) rate of 75 mV/ns.

A Flexible 0.73–15.5 GHz Single LC VCO Clock Generator in 12 nm CMOS

This brief presents a compact and flexible 0.73–15.5GHz clock generator with only a single LC-VCO. A 50% duty cycle divide-by-1.5 divider (Div-1.5) is employed to reduce the required VCO tuning range in the wide-range clock generator to 50%, which becomes viable for a single LC-VCO to cover. The divider is realized by duty cycle interpolation (DI) between two digital divide-by-1.5 (DDiv-1.5) clocks with 33.3% duty cycle and 66.7% duty cycle, respectively. The clock generator was fabricated in 12nm CMOS process with an active area of 0.17 mm2. At a 13.28125GHz output, it achieves a 101fs integrated jitter and a −74.79dBc reference spur, while consuming 19.5mW. The measured worst deterministic jitter induced by the 50% duty cycle Div-1.5 is 550fs.

A Waveform Sampling Prototype ASIC for Picosecond-Level Time Measurement

This article presents the design and test results of a waveform sampling application-specific integrated circuit (ASIC) based on the switched capacitor array (SCA). It integrates eight differential-input channels, and each channel consists of a 256-cell capacitor array, 256 12-bit Wilkinson analog-to-digital converters (ADCs), and a serial data readout. A sampling rate of up to 5 Gsps is achieved with a low-jitter delay-locked loop (DLL). Two shared coarse counters running at the rising and falling edges of the reference clock are used to extend the time measurement range. Several crosstalk reduction strategies were adopted in the circuit design, especially in the clock generation circuit and the digitization circuit. The ASIC has been fabricated in 180-nm CMOS process. The test results show that the random noise is approximately 0.7-mV rms after the fixed-pattern noise correction and that the precision of waveform timing is better than 7-ps rms with the sampling interval correction.

On-chip test vector generation and downsampling for testing RSFQ circuits

An on-chip high-frequency testing method for rapid single flux quantum circuits is proposed. This method employs test vectors based on pseudo-random sequences created by an on-chip high-frequency clock generator (CG) and a linear feedback shift register with parallel outputs (LSPO). Downsamplers (DSMs) at the outputs of a circuit under test (CUT) decimate the CUT output data so that high-frequency testing can be performed at sufficiently low data rates between the CUT and room-temperature electronics. The proposed testing can continuously test the circuit at high frequency with low-cost instruments. All of the critical subsystems, including LSPO, CG, and DSM, were designed, fabricated, and successfully tested. We validated proper operation at up to 40 GHz, confirming the concept and execution.

A Fully Integrated Low-Cost HF Multistandard RFID Reader SoC and Module for IoT Applications

The deployment and application of large-scale Internet of Things require a large number of 13.56-MHz radio-frequency identification (RFID) reader chips with lower cost. The existing RFID reader module needs to integrate multiple chips, such as microcontroller and high-frequency (HF) RFID reader IC on a single printed circuit board (PCB), which has the bottleneck of cost, power consumption, stability, and reliability. In order to adapt to the development trend of high integration, miniaturization, and low-power consumption of RFID reader, this article proposes a fully integrated low-cost RFID reader System-on-a-Chip (SoC), which integrates RF transceiver and analog circuit, baseband protocol processing, microcontroller, memory, and interface circuit into a single chip. The proposed reader IC supports communication protocols, such as ISO/IEC 14443 Type A and Type B, ISO/IEC 15693, and ISO/IEC 7816. The reader can communicate with contact and contactless IC cards. The modulation depth of the transmitter circuit ranges from 1% to 100%, and the maximum transmitting current is 126 mA. The receiver circuit is composed of I/Q clock generation, switched capacitor sampling circuit, variable gain amplifier (VGA) with filter, comparator, and pulse shaping circuit, which has good anti-noise performance. This 13.56-MHz RFID reader SoC is fabricated in a 180-nm CMOS process and is housed in a 64-pin QFP package. The total area is 8.75 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including 1.47 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for analog and RF circuits.

Systematic Design of Loop Circuit Topologies Using C/I DS Methodology

Herein, a systematic approach for designing loop topology circuits, such as ring oscillators (ROs), latches, and frequency dividers, is proposed. The design flow is devised to implement the target circuits with minimum power dissipation at the desired operating frequency. Using a modified <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C/I_{\text {DS}}$ </tex-math></inline-formula> methodology, several design examples in different technology nodes are provided showing less than ±5% error in the estimated circuit performance, confirmed by experimental data in 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> technology. A standardized procedure has been developed to extract fundamental device characteristics for different technology nodes, which are subsequently fed into an optimizer script. Examples for implementing current-steering ROs and frequency dividers will be provided. The proposed approach can be employed to custom design high-speed sequential logic circuits, as well as voltage-controlled oscillators (VCOs), digitally controlled oscillators (DCOs), and frequency dividers for applications such as clock generators, sequential circuits, and serial data transceivers in modern integrated systems.

A Low-Cost 0.00063-mm2, 0.44-pJ/b, 2-Gb/s All-Digital Fully Synthesizable CDR for Serial Links Using Single-Phase Input Clock

This brief presents a low-cost blind oversampling CDR (Clock Data Recovery) architecture that obviates the need of a dedicated clock generator or oversampling clock at the receiver end of a high-speed serial link. The proposed CDR reuses an existing at-speed clock available in the system. It deploys a sampler circuit at the input coupled to a data storage and control block that frames the serial input into a parallel output data frame along with the recovered clock. The all-digital CDR algorithm tracks clock impairments and takes appropriate action when UI (Unit Interval) boundaries are violated. Samples obtained at non-uniform time stamps near rise & fall clock edges are used to determine valid data captures. Unlike conventional oversampling CDRs, it achieves high jitter tolerance (JTOL) without storing and post processing multiple data word samples. The absence of a FIFO and elastic buffer in the design greatly reduces design size. As a result, the proposed technique achieves low power, wide-range operation with minimal hardware overhead and design implementation effort while delivering performances at par with conventional approaches. A 2Gbps CDR design in 28nm technology is demonstrated with digital area 0.00063mm2 and power 0.88mW.

Demonstration of a 2-D SnS/MXene Nanohybrid Asymmetric Memristor

This article demonstrates the fabrication and characterization of a low-cost, energy-efficient, easy-to-fabricate SnS/MXene memristor in which an SnS/Ti3C2Tx active layer is sandwiched in between two copper electrodes. The device has been showing substantial merits with an experimental <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text{off}}$ </tex-math></inline-formula> : <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text{on}}$ </tex-math></inline-formula> ratio of ~22 with good cyclic stability, exceptional reproducibility, and data retention capability up to 1000 cycles. This article explains the detailed physics governing the various regions of the proposed memristor characteristics in terms of the dual ionic conduction mechanism. Furthermore, the article explains the memristor’s asymmetric behavior using the concept of the trapping and de-trapping of charge carriers. Real-time band structures extracted using sophisticated ultraviolet photoelectron spectroscopy (UPS) strongly support the claims reported in this article. Finally, this article concludes with a practical application of the fabricated device as a low-cost, tunable asymmetric clock generator circuit.

A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency

Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ([Formula: see text]) is the main dominant source of frequency and gain ([Formula: see text]) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates [Formula: see text] times variation in [Formula: see text] across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5[Formula: see text]GHz is developed in 65[Formula: see text]nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum [Formula: see text] variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4[Formula: see text]mW power from 1[Formula: see text]V power supply.

Electromagnetic Fingerprinting of Memory Heartbeats

This paper presents MemScope, a system that fingerprints devices via electromagnetic sensing of their memory heartbeats, i.e., the clock signal that synchronizes memory and memory controller. MemScope leverages the enhanced resolution and security of memory heartbeat fingerprint, which has enriched spectral features thanks to the spread spectrum generation of memory clock, and cannot be concealed as long as the device accesses its memory during computing. MemScope employs signal processing algorithms that allow it to hear the memory heartbeats of devices from a distance, in the presence of noise, and in crowded environments where multiple devices coexist. It then fingerprints memory heartbeats using machine learning tools. Measurements on a set of 65 devices over a month validate the robustness of fingerprint against time variation, and show a high precision and recall. We then use the neural network to build a detector to defend against possible replay attacks. Finally, we further demonstrate the effectiveness of MemScope in two application scenarios, (i) detecting wireless identity spoofing and (ii) identifying and localizing unauthorized hidden cameras.