Clock Alignment Research Articles

Melanopsin's Newly Identified Functions Related to Behavioral Light Adaptation

The ability of behavior and physiology to adjust to variations in ambient light brightness is essential to survival. These adaptations include the circadian clock's alignment of physiology and behavior to the day-night cycle and the modulation of neuroendocrine activity by light. These non-image-forming (NIF) responses are dependent on ocular light receipt but can work independently of rod and cone photoreceptors, indicating the involvement of novel photoreceptors in the eye. A fascinating entrance point to understanding how mammals adjust to the light environment has been made possible by the discovery of melanopsin in intrinsically photosensitive retinal ganglion cells (ipRGCs) and genetic evidence for its significant role in major NIF responses. Here, we examine the most recent developments in our knowledge of the ipRGCs and melanopsin's newly emerging roles. These discoveries now open up new perspectives on how ambient light affects alertness, sleep, dependent physiologies, potential pharmacological intervention, and lifestyle changes to enhance quality of life.

Artepillin C Time−Dependently Alleviates Metabolic Syndrome in Obese Mice by Regulating CREB/CRTC2−BMAL1 Signaling

Artepillin C (APC), a cAMP-response element-binding (CREB)/CREB regulated transcription coactivator 2 (CRTC2) inhibitor isolated from Brazilian green propolis, can ameliorate metabolic syndrome in obese mice. Because the sensitivity and responsiveness of the body to the drug depend on the time of day and the circadian clock alignment, the optimal administration time of APC for desired efficacy in treating metabolic syndrome remains unclear. In this study, APC (20 mg/kg) or the vehicle was intraperitoneally injected into obese mice once daily for one or three weeks. The results of the insulin tolerance test, pyruvate tolerance test, and histological and biochemical assays showed that APC could improve whole-body glucose homeostasis and decrease hepatic lipid synthesis following a circadian rhythm. Further exploration of the underlying mechanism revealed that APC may disturb the diurnal oscillations of the expression of brain and muscle ARNT-like protein (BMAL1) in primary hepatocytes and the livers of the study subjects. Moreover, APC could inhibit hepatic BMAL1 expression by blocking the CREB/CRTC2 transcription complex. BMAL1 overexpression in primary hepatocytes or the livers of db/db mice antagonized the inhibitory effect of APC on hepatic lipid metabolism. In conclusion, the chronotherapy of APC may relieve metabolic syndrome in obese mice, and the mechanism behind APC-mediated time-of-day effects on metabolic syndrome were unveiled, thereby providing a foundation for optimized APC treatment from a mechanistic perspective.

Enhancing the metabolic benefits of exercise: Is timing the key?

Physical activity represents a potent, non-pharmacological intervention delaying the onset of over 40 chronic metabolic and cardiovascular diseases, including type 2 diabetes, coronary heart disease, and reducing all-cause mortality. Acute exercise improves glucose homeostasis, with regular participation in physical activity promoting long-term improvements in insulin sensitivity spanning healthy and disease population groups. At the skeletal muscle level, exercise promotes significant cellular reprogramming of metabolic pathways through the activation of mechano- and metabolic sensors, which coordinate downstream activation of transcription factors, augmenting target gene transcription associated with substrate metabolism and mitochondrial biogenesis. It is well established that frequency, intensity, duration, and modality of exercise play a critical role in the type and magnitude of adaptation; albeit, exercise is increasingly considered a vital lifestyle factor with a critical role in the entrainment of the biological clock. Recent research efforts revealed the time-of-day-dependent impact of exercise on metabolism, adaptation, performance, and subsequent health outcomes. The synchrony between external environmental and behavioural cues with internal molecular circadian clock activity is a crucial regulator of circadian homeostasis in physiology and metabolism, defining distinct metabolic and physiological responses to exercise unique to the time of day. Optimising exercise outcomes following when to exercise would be essential to establishing personalised exercise medicine depending on exercise objectives linked to disease states. We aim to provide an overview of the bimodal impact of exercise timing, i.e. the role of exercise as a time-giver (zeitgeber) to improve circadian clock alignment and the underpinning clock control of metabolism and the temporal impact of exercise timing on the metabolic and functional outcomes associated with exercise. We will propose research opportunities that may further our understanding of the metabolic rewiring induced by specific exercise timing.

THE DATA TO CLOCK ALIGNMENT METHOD IN QUARTER-RATE HIGH SPEED TRANSMITTERS

Modern hyperscale data centers are increasingly using DSP-based transceivers to compensate for high channel loss. Transceivers operating at a speed equal to or greater than 56 Gbps, prove to be a viable alternative to analog transceivers in terms of power and area requirements, delivering better overall performance. The design process of such trans-ce¬i¬v¬e¬r¬s is very challenging. The most sensitive parts are the transmitter and receiver which are the main building blocks for such systems. In addition, clocking architecture and data-to-clock alignment is critical for achieving optimal performance. This article provides a data and clock alignment method for high-speed quarter-rate transmitters.

Five-Direction Occlusion Filling with Five Layer Parallel Two-Stage Pipeline for Stereo Matching with Sub-Pixel Disparity Map Estimation.

Binocular stereoscopic matching is an essential method in computer vision, imitating human binocular technology to obtain distance information. Among plentiful stereo matching algorithms, Semi-Global Matching (SGM) is recognized as one of the most popular vision algorithms due to its relatively low power consumption and high accuracy, resulting in many excellent SGM-based hardware accelerators. However, vision algorithms, including SGM, are still somewhat inaccurate in actual long-range applications. Therefore, this paper proposes a disparity improvement strategy based on subpixel interpolation and disparity optimization post-processing using an area optimization strategy, hardware-friendly divider, split look-up table, and the clock alignment multi-directional disparity occlusion filling, and depth acquisition based on floating-point operations. The hardware architecture based on optimization algorithms is on the Stratix-IV platform. It consumes about 5.6 K LUTs, 12.8 K registers, and 2.5 M bits of on-chip memory. Meanwhile, the non-occlusion error rate of only 4.61% is about 1% better than the state-of-the-art works in the KITTI2015 dataset. The maximum working frequency can reach up to 98.28 MHz for the 640 × 480 resolution video and 128 disparity range with the power dissipation of 1.459 W and 320 frames per second processing speed.

Clock and data alignment scheme for readout electronics prototype of PandaX-nT

This work proposes a clock and data alignment scheme for the readout electronics system of the future PandaX-nT dark matter detection experiments. Since the waveform information of the photomultiplier signal is obtained by accumulating all acquisition channels of the front-end digitization module (FDM), it is required that each FDM acquisition channel should be synchronized. The readout electronics system is composed of a clock distribution module, 64 FDMs, and 4 data acquisition (DAQ) modules. The multi-board synchronous acquisition circuit can provide the same REF CLOCK and SYSREF signal for multiple FDMs boards to ensure the alignment of the sampled data collected by the analog-to-digital converter. The data aggregation circuit can ensure that the sampled data of multiple FDM boards are aligned with each other when they are aggregated to the DAQ board. The functional verification test results show that the synchronization between the prototype electronics channels is less than 80 ps, thus enabling to meet the requirements of the readout electronics prototype of PandaX-nT.

Annual variation in attentional response after methylphenidate treatment.

Prevalence rates of attention-deficit/hyperactivity disorder (ADHD) differ with geographical areas varying in sunlight intensity. Sun- or daylight reaching the retina establishes entrainment of the circadian clock to daylight. Changes herein, hence, alterations in clock alignment, could be reflected indirectly in inattention via sleep duration. We here studied (1) annual variation in inattention at treatment initiation; (2) annual variation in response to ADHD treatment [methylphenidate (MPH)] by day of treatment initiation; and (3) dose dependence. We predicted least baseline inattention during a period of high sunlight intensity implying more room for improvement (i.e., a better treatment response) when sunlight intensity is low. These hypotheses were not confirmed. High-dose treated patients, however, had significantly better attention after treatment than low-dosed treated patients, only when treated in the period from winter to summer solstice. Change in solar irradiance (SI) duringlow-dosed treatment period was negatively related to attentional improvement. The above described findings were primarily found in inattention ratings and replicated in omission errors on a continuous performance task. Daylight and inattention have been proposed to be related via mediation of the circadian system. One mechanism of MPH may be to enhance sensitivity to the diurnal entrainment to sunlight and the question can be raised whether appropriate lighting could potentiate the effects of stimulants.

Development of readout electronics for bunch arrival-time monitor system at SXFEL

A bunch arrival-time monitor (BAM) system, based on electro-optical intensity modulation scheme, is under study at Shanghai Soft X-ray Free Electron Laser. The aim of the study is to achieve high-precision time measurement for minimizing bunch fluctuations. A readout electronics is developed to fulfill the requirements of the BAM system. The readout electronics is mainly composed of a signal conditioning circuit, field-programmable gate array (FPGA), mezzanine card (FMC150), and powerful FPGA carrier board. The signal conditioning circuit converts the laser pulses into electrical pulse signals using a photodiode. Thereafter, it performs splitting and low-noise amplification to achieve the best voltage sampling performance of the dual-channel analog-to-digital converter (ADC) in FMC150. The FMC150 ADC daughter card includes a 14-bit 250 Msps dual-channel high-speed ADC, a clock configuration, and a management module. The powerful FPGA carrier board is a commercial high-performance Xilinx Kintex-7 FPGA evaluation board. To achieve clock and data alignment for ADC data capture at a high sampling rate, we used ISERDES, IDELAY, and dedicated carry-in resources in the Kintex-7 FPGA. This paper presents a detailed development of the readout electronics in the BAM system and its performance.

An Efficient Synchronization Circuit in Multi-Rate SDH Networks

Single-rate synchronous digital hierarchy (SDH) networks contain one master block and several slave blocks and the slaves will synchronize themselves by the master clock frequency. However, the clock frequencies of master and slaves are different in multi-rate SDH networks and hence, the slaves require a synchronization circuit to match their clock frequencies with the master clock frequency. This research presents an efficient synchronization circuit for such networks. The proposed circuit occupies smaller area than the prior circuit and requires no clock alignment for its implementation. The circuit constraints are described and the maximum clock frequencies of master and slaves are formulated. The synthetic benchmarks illustrate the circuit accuracy in various clock frequencies and show an average 51.7 % reduction on the area of synchronization circuit and an average 4.8 % reduction on the area of total system. The timing analyses of the circuit show maximum 277 and 126 MHz for master and slaves, respectively.

A Fast-Lock Low-Jitter DLL with Double Edge Synchronization in 0.18µm CMOS Technology

Aims : This paper describes a fast -lock, low-power, low-jitter and good duty -cycle correction capability delay locked loop with double edge synchronization which is mainly used in clock alignment process.A clock aligners task is to phase -align a chip internal clock with a reference clock. The main advantage of delay locked loop rather than phase locked loop is related to good jitter performance of it. Double edge synchronization method leads to more power consumption and it can increase rms and peak -to-peak jitter therefore, in this work rms jitter, peak -to-peak jitter and power consumption are implemented to

CMOS Oscillators for Clock Distribution and Injection-Locked Deskew

The distribution and alignment of high-frequency clocks across a wide bus of links is a significant challenge in modern computing systems. A low power clock source is demonstrated by incorporating a buffer into a cross-coupled oscillator. Because the load is isolated from the tank, the oscillator can directly drive 50-Ohm impedances or large capacitive loads with no additional buffering. Using this topology, a quadrature VCO (QVCO) is implemented in 0.13 mum digital CMOS. The QVCO oscillates at 20 GHz, consumes 20 mW and provides 12% tuning range. The measured phase noise is -101 dBc/Hz @ 1 MHz frequency offset. A clock alignment technique based upon injection-locked quadrature-LC or ring oscillators is then proposed. Although injection-locked oscillators (ILOs) are known to be capable of deskewing and jitter filtering clocks, a study of both LC and ring ILOs indicates significant variation in their jitter tracking bandwidth when used to provide large phase shifts. By selectively injecting different phases of a quadrature-LC or ring VCO, this problem is obviated resulting in reduced phase noise. The technique is demonstrated using a LC QVCO at 20 GHz while burning only 20 mW of power and providing an 8 dB improvement in phase noise. A ring oscillator deskews a 2 to 7 GHz clock while consuming 14 mW in 90 nm CMOS.

Clock aligner based on delay locked loop with double edge synchronization

In CMOS multistage clock buffer design, the duty-cycle of clock is liable to be changed when the clock passes through several buffer stages. The pulse-width may be changed due to unbalance of the p- and n-OS transistors in the long buffer. This paper describes a delay locked loop with double edge synchronization for use in a clock alignment process. Results of its SPICE simulation, that relate to 1.2 μm CMOS technology, shown that the duty-cycle of the multistage output pulses can be precisely adjusted to (50 ± 1)% within the operating frequency range, from 55 MHz up to 166 MHz.

A clock-tuning circuit for system-on-chip

System-on-chip (SoC) design depends heavily on effective reuse of semiconductor intellectual property (IP). Clock distribution has become a problem for integrating IP cores into a single synchronous SoC, because of different clock delays in the IP cores. We propose an on-chip clock-tuning circuit, which enhances design flexibility. Programmable delays are inserted in the clock distribution network, such that clock alignment and synchronization are achieved. Design iterations are eliminated with the use of the tuning circuit, saving design effort, and cost. The method is also applicable to compensating for unbalanced clock trees. Hierarchical clock tuning can be implemented and can take advantage of the hierarchical structure of the SoC. Skew analysis has shown that the added programming unit outperforms other clock design options. The method was implemented in a commercial chip, and demonstrated good functionality with high productivity of the design flow.

An integrated high resolution CMOS timing generator based on an array of delay locked loops

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for time-to-digital converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with subgate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing generator has been mapped into a 1.0 /spl mu/m CMOS process and an r.m.s. error of the time taps of 48 ps has been measured with a bin size of 0.15 ns. Used as a TDC device, an r.m.s. error of 76 ps has been obtained, A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives.

An integrated CMOS 0.15 ns digital timing generator for TDC's and clock distribution systems

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for Time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with sub-gate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing generator has been mapped into a 1.0 /spl mu/m CMOS process and a RMS error of the time taps of 48 ps has been measured with a bin size 0.15 ns. Used as a TDC device a RMS error of 76 ps has been obtained. A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>