class-F Power Amplifier Research Articles

Implementation of Electromagnetic Theory: Improved Analysis and Design for Class F Power Amplifier

ABSTRACTThe general electromagnetic (EM) theory has not yet been applied to the analysis of Class F (CF) power amplifier (PA). In this paper, an alternative approach for CF PA is presented based on the EM theory. Theoretical analysis shows that the CF PA can be divided into two broad categories, forward voltage gain, and reflected voltage gain PA. The existing CF PA belongs to the reflected voltage gain PA. Even though both the CF PAs have the same voltage gain, the PA with forward voltage gain provides higher fundamental power Ps,1@F and drain efficiency PAE@F than that CF PA with reflected voltage gain and Class B PA. This important conclusion is obtained as a result of this analysis, which cannot be explained by available theory in the literature. The theoretical analysis is validated at 2.2 GHz by fabrication and measurements. According to the results, Ps,1@B = 31.8 dBm and PAE@B = 53.27% in Class B PA. In CF PA with reflected voltage gain, Ps,1@F = 30.20 dBm and PAE@F = 48.6%. Both cases have lower power and PAE as compared to new category of CF PA. This new CF PA with forward voltage gain has, Ps,1@F = 33.04 dBm and PAE@F = 63.7%.

Investigation of class-F power amplifier in the presence of the second and fourth harmonics of input voltage

In this paper, a thorough theoretical investigation of high-efficiency class-F power amplifier (PA) is undertaken to drive, considering the second and fourth harmonics of input voltage. The precise analytical expressions of the gate-source voltage, drain current, output power, and efficiency are extracted. Maximum normalized output power and maximum drain efficiency from the initial phase and amplitude of the second and fourth harmonics of input gate-voltage can be achieved. The simulation of class-F PA using a GaN CGH40010F transistor has been done to validate the theoretical analysis. Addition of the fourth harmonic gate voltage along with the second harmonic improves the output power and efficiency of the PA by 0.7 dBm and 4.1%. Based on the simulation with realistic elements, a highly efficient PA operating from 1.8 to 2.2 GHz is implemented. The fabricated PA provides an efficiency of 72–87.6%, PAE of 65–80% and an output power of 39.3–41 dBm.

Reduced Complexity Sequential Digital Predistortion Technique for 5G Applications

Wireless communication infrastructure is a key enabling technology for smart cities. This paper investigates a novel technique to enhance the performance of 5G base stations by addressing the compensation of nonlinear distortions caused by radiofrequency power amplifiers. For this purpose, a sequential digital predistortion approach that uses twin nonlinear two-box structure along with reduced sampling rates in the feedback path is proposed to implement a linearization system. Such a system is shown to have a correction bandwidth that exceeds the bandwidth of the feedback path. This is achieved by synthesizing the predistortion function in two successive characterization iterations. Both characterizations use the same hardware, which has a reduced sampling rate in the feedback path. Hence, the proposed predistorter scheme does not require any additional hardware compared to standard schemes. Moreover, coarse delay alignment is performed while identifying the memory polynomial function in order to further reduce the computational complexity of the proposed system. Experimental results using an inverse Class-F power amplifier demonstrate the ability of the proposed predistorter to achieve a correction bandwidth of 100 MHz with a feedback sampling rate as low as 25 MSa/s.

Design of broadband power amplifier based on loop-shaped filter matching structure

A method for designing a broadband high-efficiency power amplifier (PA) based on a novel loop-shaped filter matching structure is proposed in this paper. By combining a power amplifier matching circuit and a loop-shaped filter structure, a broadband high-efficiency PA based on a new harmonic matching structure is realized. The novel loop-shaped filter can control the second and third harmonics in a wide frequency range and has a specific control effect on higher-order harmonics, which can further expand the bandwidth of class-F PA and improve efficiency. To verify its feasibility, a power amplifier with a bandwidth of 1.6 GHz-3.4 GHz, a saturated output power greater than 41 dBm, a drain efficiency of 65% -72% with a gain greater than 10dB is designed and fabricated using GaN HEMT CGH40010F transistor.

Analytical Approach to Improve the Performance of a Fully Integrated Class-F Power Amplifier with 0.13 µm BiCMOS Technology Using Drain–Bulk Capacitor Modulation

This article reports a novel technique based on drain–bulk capacitor modulation to improve the performance design of a class-F power amplifier (PA) used in low-power transceivers based on the I-Q amplitude modulation technique considering linearity–efficiency–miniaturization trade-offs. This idea is carried out by implementing a tuned capacitor in parallel with a cascode transistor on the output of the power stage to enhance the shape of the voltage–current amplitudes of the class-F PA by creating a new harmonic current component. Simulated results were obtained for the power back-off region of the proposed configuration, with an output power, power gain and power-added efficiency of 8 dBm (+ 5 dBm)B, 19 dB (+ 5 dB)B and 45% (+ 5% to 10%)B, respectively. In addition, post-layout simulations revealed a similar level of output power, a power gain of a 20 dB and a 28% power-added efficiency for an added capacitance equal to 1.3 pF. Class-F PA is implemented on a 732×605 μm2 chip’s surface. (B: indicates the improved values in the power back-off region).

Design of Class F Power Amplifier for Sub 6 GHz

Class F power amplifiers increasingly have widespread use cases in the modern portable mobile communications and higher efficiency operation due to base station. This paper focuses on the design of sub 6 GHz class-F Power Amplifiers (PA) to ensure maximum output power and gain using Gallium nitride– High Electron Mobility Transistor (GaN HEMT). The work also aims to analyze stability and Power Added Efficiency (PAE) using Advanced Design System (ADS) software. Simulations for DC characteristics of the GaN HEMT transistor are performed, stability circles are simulated, and stability factor values have been noted, using ADS software. Stability analysis involves measurements to examine the conditions that may lead to unstable behavior of the PA. The load pull analysis followed by impedance matching is done to transfer maximum power from amplifier stage to load. The input and output network has been designed using transmission lines and incorporated in the final circuit of the PA design. Using the LineCalc tool, the values of electrical parameters are used in the respective MLIN and TLIN circuits, and the respective matching networks are designed at the input side and output side. The amplifier stability factor is 2.276 and the maximum PAE is 65.75%. The maximum output is 39.83 dBm. The layout for the PA network using ADS software has been obtained.

High-efficiency class-F power amplifier based on double spiral defected ground structure

ABSTRACT In this paper, a high-efficiency class-F power amplifier with a harmonic control circuit is proposed. The harmonic control circuit is realised by loading microstrip branch lines to achieve a short-circuit state for the second harmonic. The double spiral defected ground units are loaded on the ground of the microstrip line of the drain bias circuit to produce a low-pass filtering and stopband suppression effect outside the passband, so as to suppress the third harmonic. Meanwhile, it would provide an open-circuit state for the third harmonic, and finally meet the harmonic impedance tuning demands of class-F power amplifier. Through theoretical analysis and simulation, a high-efficiency class-F power amplifier operating at 2.5 GHz ~2.7 GHz is designed. The measured results show that in the working frequency band, the drain efficiency is 66.3%~71.1%, the output power is 40.9 dBm ~42.1 dBm and the gain is 10.9 dB ~11.8 dB.

Highly efficient broadband continuous Class-F power amplifier with a novel harmonic matching network

In this letter, we propose a methodology for designing high efficiency broadband harmonic-controlled power amplifiers (PAs) with a novel harmonic matching network. This network consists of three second-harmonic open circuit microwave lines and three third-harmonic short circuit microwave lines, each corresponding to different wavelengths for different frequencies. It can improve the efficiency and bandwidth of PAs by controlling harmonic match impedance. Through the proposed network, we design and fabricate a highly efficient broadband continuous Class-F PA using a CGH40010F GaN HEMT device. The measurement results show that the drain efficiency of 71.4% to 82.4% (the average efficiency of 76.9%) and output power of 40.4dBm to 42.6dBm are achieved at 1.3GHz-2.5GHz, respectively.

Analysis of Efficiency-Limiting Factors Resulting from Transistor Current Source on Class-F and Inverse Class-F Power Amplifiers

Analysis of Efficiency-Limiting Factors Resulting from Transistor Current Source on Class-F and Inverse Class-F Power Amplifiers

Optimization design of fragment-type filtering matching network for continuous inverse class-F power amplifier

Optimization design of fragment-type filtering matching network for continuous inverse class-F power amplifier

Design and optimisation of high‐efficient class‐F ULP‐PA using envelope tracking supply bias control for long‐range low power wireless local area network IEEE 802.11ah standard using 65 nm CMOS technology

This article presents the design and optimisation of a sub-1 GHz class-F ultra-low power (ULP) power amplifier (PA) in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. An envelope tracking (ET) supply biasing technique is adopted to improve the efficiency of class-F PA. The ET consist of a pre-amp right before the detector in order to enhance the efficiency and save adequate amount of dc power consumption. The PA consists of two cascode cells terminated as class-F with gate-to-drain feedback in order to enhance linearity and limit any harmonic component from the input signal. The novel design consumes a dc power of 3.75 mW, power added efficiency of 37.1%, operating at 915–925 MHz unlicensed band and total saturated output power of 22 dBm including 14 dBm power gain at PA, which qualifies under long-range low power wireless personal area network IEEE 802.11ah standard. The inductor-less design for ET supply bias reduces the chip layout size to 0.13 mm2 only.

Design of Continuous Class-F Mode Power Amplifier with High Gain Flatness

In this letter, a novel RF power amplifier (PA) with high gain flatness and high efficiency operating in continuous Class-F mode is introduced. Since most continuous Class-F PAs can’t meet the requirement of high gain flatness, a new structure which can achieve high gain flatness is presented. A 1.7-2.5GHz PA is designed, which uses CGH40010F GaN device. Simulation results show that the drain efficiency (DE) of the continuous Class-F PA is between 69% and 79%, output power is more than 41dBm across the whole bandwidth. Gain is between 11dB and 11.8dB, and gain flatness is 0.8dB.

High-efficiency Class-F Power Amplifier with a New Design of Input Matching Network

This paper presents a novel access to develop a class-F power amplifier with high power-added efficiency (PAE). The main goal of the proposed PA is to obtain high PAE. The proposed HCC consists a design of output matching circuit (OMN) and input matching combined with a symmetric low-pass filter (LPF) reported. To accomplish a high-efficiency performance, a low-voltage pHEMT in the circuit was executed to supply the required dc-supply voltage. It yielded nth harmonic suppression and high-power added efficiency (PAE). The simulation was carried out using harmonic balance analysis. The power amplifier proposed in this study was fabricated at fundamental frequency of 1 GHz with PAE of 80% and DE of 86% under 12.3dBm input power and very low drain voltage of 2 V. This class-F PA manufactured with such features can be utilized for power amplification in wireless transmitter communication systems.

Design of Wideband Continuous Class-F Power Amplifier Using Low Pass Matching Technique and Harmonic Tuning Network

Many countries have allocated new frequency bands for fifth generation (5G) communication systems. In this paper, a wideband continuous class-F (CCF) radio frequency power amplifier (RFPA) is presented for the new 5G frequency band, from 3.3 GHz to 4.3 GHz using a 10 W Cree CGH40100F device. A unique wideband RFPA design approach for the output matching network (OMN) is also presented by applying a harmonic tuning network (HTN) for the harmonics and a low pass matching technique (LPMT) for the fundamental frequency. The RFPA is fabricated, and promising measurement results show a drain efficiency of 55.9% to 65.3% is achieved at an output power of 40 dBm (± 0.3 dBm) over a frequency range of 3.3 GHz to 4.3 GHz. A two-tone signal with a 10 MHz spacing was also applied to investigate the linearity of the RFPA.

High‐efficiency hybrid continuous mode power amplifier with input and output harmonic engineering

This paper intensely studies the impact of the input nonlinearity caused by the transistor's feedback on the hybrid continuous class-F power amplifier. The research extends the influence of input harmonics on class-F power amplifiers to a more general form. Through waveform engineering, the impact of feedback is analyzed. By analyzing the change in cutoff angle caused by input nonlinearity, the change of the drain voltage and current waveforms of the hybrid continuous class-F power amplifier can be obtained. The new drain voltage and current waveforms obtained from the analysis redefine the design space of source impedance and load impedance for the hybrid continuous class-F power amplifier. By designing the corresponding input and output matching network, the second harmonic is suppressed, and finally, the hybrid continuous class-F power amplifier achieves a high-efficiency state. The research reveals that input harmonics also play an essential role in the design process of power amplifiers. A comparative experiment is designed to verify the theory. Simultaneously, a 1.6–2.8 GHz broadband hybrid continuous class-F power amplifier is designed using this theory, with a saturation efficiency of more than 61.2% and a saturation power of more than 40.4 dBm.

Substrate integrated waveguide based class‐F power amplifier

This work outlines the design, implementation, and experimental results of a Class-F power amplifier (PA) with a novel output matching topology by utilizing substrate integrated waveguide (SIW). The design methodology is first proposed with one highly integrated SIW matching structure. The impedances at fundamental, second harmonic and third harmonic frequencies are analysed to explain good impedance matching for the PA as well as the isolation mechanism of the direct current (DC) and radio frequency (RF). For demonstration, an S-band 10-W Class-F PA is fabricated and tested. The simulation and measurement results agree very well with each other, which verifies the proposed technology of SIW output matching. To the authors’ knowledge, this is the first time to use a highly integrated SIW matching in Class-F PA, which simplifies the output matching for third-order harmonics and DC/RF isolation structures.

A novel design methodology for extended continuous class-F power amplifiers in wireless applications

A novel design methodology for extended continuous class-F power amplifiers in wireless applications

Dual-Band Class-F Power Amplifier With Bandwidth Expansion Based on Sector Microstrip Branch for 5G Applications

This letter presents a dual-band class-F power amplifier (PA) design with an extended bandwidth for 5G communication applications. A bandwidth expansion structure is established based on the sector microstrip, then combined with a dual-frequency harmonic control network to reach dual-frequency bandwidth of 2*200 MHz while maintaining high efficiency. The saturated output power of the proposed device is between 41.5 and 41.8 dBm, the gain is from 11.6 to 11.9 dB, the drain efficiency (DE) is 71% to 75%, and the power added efficiency (PAE) is 65% to 70% at 3.3-3.5 GHz. The saturated power and the DE at 4.8-5.0 GHz are over 39.5 dBm and 61%, respectively. The gain ranges from 9.7 to 10.1 dB and the minimum PAE is 58%.

A design scheme for harmonic suppression network of high efficiency class-F power amplifier

This paper presents a design scheme of class-F PA harmonic suppression network. This scheme combines the advantages of lumped parameter elements and distributed parameter elements, and makes use of the characteristics of high Q value (quality factor), large adjustability of capacitance and high reusability of the microstrip line, so that the harmonic suppression network has the advantages of them. Based on the proposed scheme, a class-F PA with a frequency of 2.4GHz and a maximum PAE of 68.86% is designed, the output power of which can reach 17.5W (42.42dBm), so as to verify the feasibility of the proposed scheme. This scheme can improve the output power of UHF (300 ~ 3000MHz) class-F PA and reduce the difficulty of circuit design under the condition of high PAE.

2.4 GHz GaN HEMT Class-F Synchronous Rectifier Using an Independent Second Harmonic Tuning Circuit.

This paper proposes a class-F synchronous rectifier using an independent second harmonic tuning circuit for the power receiver of 2.4 GHz wireless power transmission systems. The synchronous rectifier can be designed by inverting the RF output port to the RF input port of the pre-designed class-F power amplifier based on time reversal duality. The design of the class-F power amplifier deploys an independent second harmonic tuning circuit in the matching networks to individually optimize the impedances of the fundamental and the second harmonic. The synchronous rectifier at the 2.4 GHz frequency is designed and implemented using a 6 W gallium nitride high electron mobility transistor (GaN HEMT). Peak RF-dc conversion efficiency of the rectifier of 69.6% is achieved with a dc output power of about 7.8 W, while the peak drain efficiency of the class-F power amplifier is 72.8%.