Circuit-level Simulation Research Articles

New approach for digital calibration of pipelined analog to digital converters based on secant method

This paper presents a new method for linear and nonlinear errors of pipelined analog to digital converters (ADCs) based on numerical analysis. The main contribution of this work is to use secant method for solving nonlinear equations. The proposed method is not required the derivative of function, compared to the previously Newton Raphson algorithm. To validate the effectiveness of the proposed method, circuit level simulations in the circumstance of the 12-bit 100 MS/s pipelined ADC in 90-nm CMOS technology are provided. Simulation results show that the signal-to-noise and distortion ratio (SNDR) and the spurious free dynamic range (SFDR) improved from 22dB/25 dB–68dB/74 dB, respectively, after applying secant method. The convergence time of the algorithm is approximately 1000 clock cycles which is faster than Newton Raphson. By using accurate analysis, the estimated power and area in the digital domain are 2.4 mW and 0.06 mm2, respectively. The corresponding figure of merit is 40 fJ/conversion-step.

Optimization of Charge Pump Based on Piecewise Modeling of Output-Voltage Ripple

This work proposes a piecewise modeling of output-voltage ripple for linear charge pumps. The proposed modeling can obtain a more accurate design expression of power-conversion efficiency. The relationship between flying and output capacitance, as well as switching frequency and optimize power-conversion efficiency can be calculated. The proposed modeling is applied to three charge-pump circuits: 1-stage linear charge pump, dual-branch 1-stage linear charge pump and 4× cross-coupled charge pump. Circuit-level simulation is used to verify the accuracy of proposed modeling.

Hardware Implementation of Differential Oscillatory Neural Networks Using VO 2-Based Oscillators and Memristor-Bridge Circuits.

Oscillatory Neural Networks (ONNs) are currently arousing interest in the research community for their potential to implement very fast, ultra-low-power computing tasks by exploiting specific emerging technologies. From the architectural point of view, ONNs are based on the synchronization of oscillatory neurons in cognitive processing, as occurs in the human brain. As emerging technologies, VO2 and memristive devices show promising potential for the efficient implementation of ONNs. Abundant literature is now becoming available pertaining to the study and building of ONNs based on VO2 devices and resistive coupling, such as memristors. One drawback of direct resistive coupling is that physical resistances cannot be negative, but from the architectural and computational perspective this would be a powerful advantage when interconnecting weights in ONNs. Here we solve the problem by proposing a hardware implementation technique based on differential oscillatory neurons for ONNs (DONNs) with VO2-based oscillators and memristor-bridge circuits. Each differential oscillatory neuron is made of a pair of VO2 oscillators operating in anti-phase. This way, the neurons provide a pair of differential output signals in opposite phase. The memristor-bridge circuit is used as an adjustable coupling function that is compatible with differential structures and capable of providing both positive and negative weights. By combining differential oscillatory neurons and memristor-bridge circuits, we propose the hardware implementation of a fully connected differential ONN (DONN) and use it as an associative memory. The standard Hebbian rule is used for training, and the weights are then mapped to the memristor-bridge circuit through a proposed mapping rule. The paper also introduces some functional and hardware specifications to evaluate the design. Evaluation is performed by circuit-level electrical simulations and shows that the retrieval accuracy of the proposed design is comparable to that of classic Hopfield Neural Networks.

A SPICE Compact Model for Ambipolar 2-D-Material FETs Aiming at Circuit Design

We report a charge-based analytic and explicit compact model for field-effect transistors (FETs) based on 2-D materials (2DMs), for the simulation of 2DM-based analog and digital circuits. The device electrostatics is handled by invoking 2-D density of states and Fermi-Dirac statistics that are later combined with the Lambert-W function and Halley's correction to eventually obtain explicit expressions for the electron and hole charges, which are exploited in the calculation of drift-diffusion currents for both carriers. Furthermore, the charge model is extended to obtain characteristics of 2DM-based negative capacitance FETs. The model is benchmarked against experimental MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FET measurements and experimental ambipolar characteristics of narrowband-gap materials, such as black phosphorus. Its soundness for SPICE circuit-level simulations is also demonstrated.

Theory and Sensitivity Optimization of Plasmo-photonic Mach-Zehnder Interferometric Sensors

We demonstrate a novel theoretical framework for refractive index Mach-Zehnder interferometric (MZI) sensors that can accurately calculate the sensor FSR and sensitivity while taking into account waveguide effective index dispersion and dip splitting effects. In contrast to the state-of-the-art mathematical equation that relates sensitivity with FSR, our analysis concludes to a mathematical expression that retains its validity and accuracy both in low and large FSR sensor layouts, suggesting its suitability for use in optimizing sensor performance even in the high-sensitivity, high-FSR configurations. This is validated by applying our theory to integrated plasmo-photonic MZI sensors with FSR values up to hundreds of nm, confirming our theoretical results through accurate numerical and circuit-level simulations and demonstrating how sensitivity can be boosted to >10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> nm/RIU values exploiting dispersion engineering of the waveguides. To this end, our analytical formula that relates sensitivity with FSR and waveguide effective index dispersion can lead to reliable designs and well-matched fabricated modules when targeting high FSRs and high sensitivity MZI photonic integrated sensors.

LET-dependent model of single-event effects in MOSFETs

In this paper, we simulate the electrical characteristics of the n-type metal-oxide-semiconductor (NMOS) transistor in a 65-nm complementary metal-oxide-semiconductor (CMOS) inverter under the actions of heavy ions with different linear energy transfers (LET). We analyze the influence of incident ions with different LETs on a device using technology computer-aided design (TCAD) software, and aim to establish an HSPICE sub-circuit model containing the relationship between the electrical properties of a device and the LET of an incident ion for circuit-level HSPICE simulation. Based on the SEE funnel mechanism, we propose an analytical model to describe the relationship between the charge collected by the NMOS drain and the LET of the incident ion, and build an HSPICE model based on this analytical model. With such a model, the influence of incident ions with different circuit-level LETs can be determined from HSPICE simulation. In addition, good agreement with simulation results is reached, proving the reasonableness of the proposed model.

Impact of Thermal Effects on the Performance of the Power Gating Circuits Using NEMS, FinFETs, and NWFETs

In this article, the power gating (PG) technique is analyzed using nano-electro-mechanical switches (NEMS), FinFETs, and nanowire field-effect transistors (NWFETs). We have used detailed circuit level simulations using well-calibrated models to obtain the conditions for net energy saving with thermal effects. We demonstrate that for a benchmark 17-stage buffer chain circuit, the NEMS PG will be superior to sub-10-nm FinFETs and NWFETs-based gating when the T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> on</sub> / T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> off</sub> ratio is less than 0.1 at room temperature. The ratio increases as temperature increases. Circuit simulations show that the energy gain ( T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> off</sub> = 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> ) due to NEMS gating increases by 3.6 times with reference to NWFETs and 7.3 times as compared to FinFETs-based gating when the temperature increases from 30 °C to 80 °C. NWFETs require a longer breakeven cycle for PG to become more energy-efficient than FinFETs due to its better gate control over the channel.

A Novel Dynamic Time Method for Organic Light-Emitting Diode Degradation Estimation in Display Application

This work presents a time discretization strategy to estimate the current degradation of OLED devices in circuit-level simulation. An equivalent time point method is used to calculate degradation rate appropriately under dynamic bias conditions, and temperature effect due to ambient or device self-heating during operation is also included. Groups of OLEDs with various aging conditions are measured more than 1000 hours and the current attenuation (ΔI) of OLED is compared by the proposed methodology to verify the accuracy. Furthermore, the simulation results indicate our method could properly describe the current degradation and the bias voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OLED</sub> ) shift in pixel circuit under pulse amplitude modulation (PAM) or pulse width modulation (PWM) driving method, which is nearly impossible to be calculated with analytic solutions.

Modelling and Analysis of a Plus-Shaped PN Junction Phase Shifter for Data Centre Applications

Scaling up of photonic devices is the current research of interest to meet the alarming demand growth in the data centres. The efficiency of the modulator is determined by the performance of the phase shifter. In this paper, a plus-shaped PN junction phase shifter is designed and analysed. This design improved the modulation efficiency and reduced optical loss for high-speed data operation. The width of the P doped region and thickness of thedoped regions in the slabs are varied to obtain high modulation efficiency. The circuit-level simulation analysis was performed on the proposed phase shifterimported in a travelling wave electrode silicon Mach Zehnder modulator. At 80 Gbps, a maximum extinction ratio of 12.39 dB with a bit error rate of 8.67×10-8 was obtained at VπLπ of 1.05 V.cm for the length of the phase shifter of 3.5 mm. The calculated intrinsic 3 dB bandwidth is ~38 GHz and the energy per bit transmission is 1.71pJ/bit.Further analysis was performed to identify the maximum communication distance supported by this proposed phase shifter design in the silicon Mach Zehnder modulator for the data centre requirements.

Nonlinear Analysis of Cross-Coupled Super-Regenerative Oscillators

In this paper, a nonlinear analysis of cross- coupled super-regenerative oscillators (SROs) is presented. The start-up and decay envelopes of the oscillator output are studied in relation to the input. The SRO start-up time and the maximal achievable quenching frequency are investigated. For phase modulation purposes, the relation between the initial phases of the input and output signals is investigated. In addition, a frequency-domain analysis is performed to ease the characterization of circuit prototypes at frequencies where time-domain measurements are not possible. The analytical results are verified by circuit-level simulations and measurements of a 2.4-GHz SRO. This study provides design guidelines for the design of SROs in cross-coupled architectures and helps in determining the optimal system parameters when targeting both amplitude and phase modulations. To the authors' best knowledge, this is the first study investigating analytically the phase relation between the SRO input and output signals and the nonlinear large-signal behavior of SROs.

Modelling and Analysis of a Corrugated PN Junction Phase Shifter in Silicon MZM

The essential requirement for an efficient optical modulator is to have high modulation efficiency at a high data rate. The performance of the phase shifter determines the efficiency of the modulator. In this paper, a corrugated PN junction phase shifter on a silicon waveguide is designed and analysed. Doped horizontal slabs of corrugated structure are designed to produce multiple PN junctions to maximise the index change that influences the optical modulation. With the travelling wave electrode, the optical group and RF effective index are matched to obtain high-speed modulation. The optimised design is imported in a silicon Mach Zehnder modulator, and circuit-level simulation analysis is performed. At 70Gbps, a maximum extinction ratio of 10.57dB with a bit error rate of 1.94 × 10− 6 is obtained at Vπ L of 0.75V.cm for the phase shifter length of 1.5mm. The energy per bit transmission is calculated to be 3.3pJ/bit. Further analysis is performed to identify the maximum communication distance supported by this proposed phase shifter design in the silicon Mach Zehnder modulator for the data centre requirements.

Nano-Crossbar Weighted Memristor-Based Convolution Neural Network Architecture for High-Performance Artificial Intelligence Applications.

Nano memristor crossbar arrays, which can represent analog signals with smaller silicon areas, are popularly used to describe the node weights of the neural networks. The crossbar arrays provide high computational efficiency, as they can perform additions and multiplications at the same time at a cross-point. In this study, we propose a new approach for the memristor crossbar array architecture consisting of multi-weight nano memristors on each cross-point. As the proposed architecture can represent multiple integer-valued weights, it can enhance the precision of the weight coefficients in comparison with the existing memristor-based neural networks. This study presents a Radix-11 nano memristor crossbar array with weighted memristors; it validates the operations of the circuits, which use the arrays through circuit-level simulation. With the proposed Radix-11 approach, it is possible to represent eleven integer-valued weights. In addition, this study presents a neural network designed using the proposed Radix-11 weights, as an example of high-performance AI applications. The neural network implements a speech-keyword detection algorithm, and it was designed on a TensorFlow platform. The implemented keyword detection algorithm can recognize 35 Korean words with an inferencing accuracy of 95.45%, reducing the inferencing accuracy only by 2% when compared to the 97.53% accuracy of the real-valued weight case.

Jitter Modeling in Digital CDR with Quantization Noise Analysis

Phase rotator-based digital clock and data recovery (CDR) using multi-level bang-bang phase detector (ML-BBPD) and time to digital converter (TDC) is analyzed at system and circuit level. A model is proposed for calculating the quantization noise and bit error rate (BER), in order to evaluate the important parameters in CDR design. The jitter analysis is done based on the probability density function achieved from the quantization noise error of the BBPD and TDC. The analysis of ML-BBPD is shown that by increasing the number of sampling clocks, the quantization noise and consequently the jitter and BER are significantly reduced. Also, it is shown that by improving the resolution of the TDC and increasing number of delay cells for the purpose of keeping fixed the dynamic range, the output jitter of TDC is decreased. In the proposed model and also simulation, it is approved that by increasing the ratio of RMS input Gaussian jitter to the quantization step, the output jitter reaches to its saturated value. To prove the jitter model, the goodness of fit test based on Kolmogorov–Smirnov test is used and in addition, the simulation is provided for circuit level CDR. The circuit level simulation is done in TSMC 65 nm CMOS technology. The CDR is worked under 1 V supply voltage at 480Mbit/s bit rate useful for USB2 applications. The CDR dissipates 913 µW power and generates 0.258 ps RMS jitter, while it occupies 166 µm × 104 µm chip area.

Obtaining an Operating Point Solution of a Traveling Wave Laser Model

This paper presents a method of obtaining an operating point configuration for a laser model based on a traveling wave model (TWM), which can then be used in a circuit-level simulator. The method first finds an approximate distributed single-mode stationary solution, this solution is then iterated using the traveling wave equations to an accurate single-mode solution, and finally a short pre-simulation is used to add harmonic content to create a multi-mode configuration of the laser approximating its behavior at an operating point. The effectiveness of this approximation is tested by initiating transient simulations from this operating point and comparing them to the output of the model started from an off state. The stochastic variation in the operating point for a particular configuration is also well predicted. Included in the formulation are gain compression and dispersion effects, laser chirp due to variation in the effective index of the laser mode, and spontaneous emission. Finally, the use of the three-stage process of finding the operating point in a circuit-level simulator is discussed. Not only does the three-stage method provide a quick, accurate operating point for the circuit simulator, but the ability to provide an orders of magnitude faster estimate for the initial circuit-level operating point is critical to the practicality of its use in the simulator. The first stage of the three-stage method does just this.

Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation

In this study, we propose an analog CMOS integrate-and-fire (I & F) neuron circuit with a synaptic off-state current blocking operation. The proposed circuit prevents unintended potential changes in the membrane capacitor owing to the off-state current of synaptic devices, thereby preventing a decrease in the accuracy of the spiking neural network (SNN) inference system. Compared to the conventional I & F neuron circuit, the basic I & F and synaptic off-current blocking operations of the proposed I & F neuron circuit were confirmed in a circuit-level simulation. Furthermore, to verify the effect of the proposed circuit on the neural network, a multi-layer SNN simulation was performed, and the accuracy of the inference system was compared for the conventional and proposed I & F neuron circuits. The simulation and analysis results demonstrate the robustness of the I & F neuron circuit to the drop in accuracy of inference systems due to off-state currents in synaptic devices.

Analysis of the Usefulness Range of the Averaged Electrothermal Model of a Diode–Transistor Switch to Compute the Characteristics of the Boost Converter

In the design of modern power electronics converters, especially DC-DC converters, circuit-level computer simulations play an important role. This article analyses the accuracy of computations of the boost converter characteristics in the steady state using an electrothermal averaged model of a diode–transistor switch containing an Insulated Gate Bipolar Transistor (IGBT) and a rapid switching diode. This model has a form of a subcircuit for SPICE (Simulation Program with Integrated Circuit Emphasis). The influence of such factors as the switching frequency of the transistor, the duty cycle of the signal controlling the transistor, the input voltage, and the output current of the boost converter on the accuracy of computing the converter output voltage and junction temperature of the IGBT and the diode were analysed. The correctness of the computation results was verified experimentally. Based on the performed computations and measurements, the usefulness range of the model under consideration was determined, and a method of solving selected problems limiting the accuracy of computations of the characteristics of this converter was proposed.

Efficient IR Drop Analysis and Alleviation Methodologies Using Dual Threshold Voltages with Gate Resizing Techniques

IR drop impacts circuit delay time and reliability. The IR drop comes from unexpected peak current (Ipeak) consumption. This paper proposes an efficient methodology with an in-house EDA tool named IPR to analyze and reduce the Ipeak. IPR adopts dual threshold voltages (Vth) and gate resizing technique; it also lowers the short, dynamic, and static leakage current consumption without degrading the system performance. IPR consists of two parts: Ipeak analysis and Ipeak alleviation processes. Nonlinear static/dynamic timing analysis techniques, in cooperation with dual Vth cell library, provides two kinds of accurate Ipeak calculation methods used in IPR. Using the incremental timing analysis, the Ipeak processing time can be accelerated. Demonstration of the ISCAS89 benchmark circuits shows that IPR can reduce Ipeak by 39%, power consumption by 14%, and delay time by 19%. In addition, it provides 334 times faster computation with 2% and 10% estimation errors of the Ipeak and power in gate-level, respectively, as compared to circuit level simulation results.

Modeling of Dirac voltage for highly p-doped graphene field-effect transistor measured at atmospheric pressure

In this paper, the modeling approach of Dirac voltage extraction of highly p-doped graphene field-effect transistor (GFET) measured at atmospheric pressure is presented. The difference of measurement results between atmospheric and vacuum pressures was analyzed. This work was started with actual wafer-scale fabrication of GFET with the purposes of getting functional device and good contact of metal/graphene interface. The output and transfer characteristic curves were measured accordingly to support on GFET functionality and suitability of presented wafer fabrication flow. The Dirac voltage was derived based on the measured output characteristic curve using ambipolar virtual source model parameter extraction methodology. The circuit-level simulation using frequency doubler circuit shows the importance of accurate Dirac voltage value to the device practicality towards design integration.

Field-Free 3T2SOT MRAM for Non-Volatile Cache Memories

Continued scaling of Complementary Metal Oxide Semiconductor (CMOS) integrated circuit technology is slowing down due to physical limitations, while the static power of CMOS based memory is increasing as the transistors shrink. As an alternative memory technology, the Spin Transfer Torque Magnetic RAM (STT-MRAM) remains limited to low-level, high-capacity caches because of the high write power and still unsatisfactory write access speed. Spin Orbit Torque MRAM (SOT-MRAM), which has been proposed to tackle this issue, still faces some issues including the poor read margin due to low Tunnel Magnetoresistance (TMR) and undesirable use of a magnetic field for deterministic switching. This article proposes a novel 3T2SOT (three Transistors and two SOT magnetic tunnel junctions) based field-free MRAM, which can achieve higher read speed and reliability by adopting a self-referencing scheme, and lower write power benefiting from an advanced switching mechanism. Detailed circuit-level simulation results show that the write latency of the proposed design can be reduced to 0.3 ns, and the write power is two orders of magnitude lower than STT-MRAM. Additionally, compared to SRAM, for 8 MB cache memory, the read speed of 3T2SOT MRAM is enhanced by 38.9%. Compared to conventional 2T1SOT MRAM, the read performance is similar and the read error rate is dropped by 96.1% at least.

On the usage of a time-frequency switch mode algorithm to efficiently simulate RF circuits

Wireless devices integrating more and more features in ever-smaller packages have become integral part of everyone’s daily life. These systems have seen a continuous push to profit from digital signal processing techniques, in which signals are no longer traditional continuous amplitude and/or phase-modulated carriers, but became pulsed waveforms where the amplitude and/or phase are coded in some on–off digital scheme. This on–off scenario has been addressing new challenges to the circuit-level simulation of such systems. Having this in mind this paper aims to propose an innovative time–frequency simulation technique based on a switch mode algorithm, which is specially conceived for the efficient numerical simulation of RF circuits whose stimuli are intermittently turned on and off for unknown periods of time. At present, to simulate this category of circuits commercial tools have no choice than to make use of full conventional SPICE algorithms. This paper suggests an alternative way, which can result in significant speedups, without perceptible loss in accuracy.