Chuck Temperature Research Articles

Necking Reduction at Low Temperature in Aspect Ratio Etching of SiO2 at CF4/H2/Ar Plasma.

This study investigated the effect of temperature on the aspect-ratio etching of SiO2 in CF4/H2/Ar plasma using patterned samples of a 200 nm trench in a low-temperature reactive-ion etching system. Lower temperatures resulted in higher etch rates and aspect ratios for SiO2. However, the plasma property was constant with the chuck temperature, indicated by the line intensity ratio from optical emission spectroscopy monitoring of the plasma. The variables obtained from the characterization of the etched profile for the 200 nm trench after etching were analyzed as a function of temperature. A reduction in the necking ratio affected the etch rate and aspect ratio of SiO2. The etching mechanism of the aspect ratio etching of SiO2 was discussed based on the results of the surface composition at necking via energy-dispersive X-ray spectroscopy with temperature. The results suggested that the neutral species reaching the etch front of SiO2 had a low sticking coefficient. The bowing ratio decreased with lowering temperature, indicating the presence of directional ions during etching. Therefore, a lower temperature for the aspect ratio etching of SiO2 could achieve a faster etch rate and a higher aspect ratio of SiO2 via the reduction of necking than higher temperatures.

Investigation of Temperature Dependence of mmWave Power Amplifier Large-Signal Reliability Performance

This work aims to study the temperature dependence on the long-term reliability of a power amplifier (PA) cell fabricated using 40-nm partially depleted-silicon on insulator (PD-SOI) nFET under dc and large-signal RF stress. Voltage swing caused by large RF signals complicates the stress mechanism due to frequent switching of stress from conducting to nonconducting. The impact of temperature on the time slope exponent ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> ) is also analyzed to understand the degradation mechanism at different temperatures. The values of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> are found to increase with the temperature pointing to the generation of new defects at the interface. A comparative reliability analysis is presented for dc, small-, and large-signal performance under varied accelerated dc and large-signal stress at drain and gate for different temperatures. Unity gain frequencies are also temperature sensitive and show high degradation at elevated temperatures. In our study, we have investigated the lifetime as a function of temperature of the PA operating in compression. It is observed that the lifetime is more than ten years when the PA operates at room temperature, which deteriorates as the measurement chuck temperature rises.

Cryogenic etching of porous material

With the shrinkage of chip feature sizes, porous materials are widely used in microelectronics. However, they are facing severe challenges in plasma etching, as the reactive radicals can diffuse into the interior of material and damage the material, which is called plasma induced damage. In this paper, we review two kinds of etching processes based on low chuck temperature, i.e. cryogenic etching. By lowering the chuck temperature, either the etching by-products or the precursor gas can condense in the porous material, and thus preventing the radicals from diffusing and protect the material from being damaged by plasma. The technology of cryogenic filling inside the porous material is simple but effective, which allows it to have a good application prospect.

Isotropic dry etching of Si selectively to Si0.7Ge0.3 for CMOS sub-10 nm applications

The fabrication of Si0.7Ge0.3 sub-10 nm nanochannels in gate-all-around devices requires a highly selective Si isotropic etching process. The etching of Si selectively to Si0.7Ge0.3 with CF4/N2/O2 downstream plasma has been investigated using various morphological and surface characterization techniques. Conditions such as 400 W microwave power, 700 mTorr pressure, 25 °C chuck temperature, and 22% CF4:22% N2:56% O2 feed gas mixture were found to be optimum for selectivity and etch rates. X-ray photoelectron spectroscopy showed that, during the etching process, a highly reactive 8 nm thick SiOxFy layer is formed on Si. Meanwhile, a 2 nm thick passivation layer is observed on SiGe. The latter is a mixture of SiOxFy and GeOxFy species that protected the alloy from etching. The process selectivity was improved by investigating different wet and dry oxidant treatments prior to etching. The dry oxidant treatment gives the best results in terms of selectivity. These results obtained on blanket wafers have been validated on pattern wafers. Scanning electron microscopy demonstrated that SiGe nanowires were fully released with a high selectivity after dry oxidation followed by the etching process.

Electrothermal Characteristics of Electroplated Ni-Based Tunable MEMS Inductor on High-Resistivity Substrate With Displacement Actuator

In this letter, the design and characterization of an electroplated Ni-based tunable microelectromechanical inductor is presented. The inductor was fabricated on high-resistivity substrate (ρ ~ 5 kΩ·cm) to minimize eddy currents and displaced current-induced substrate related losses. The inductor loop had a nitride-encapsulated polysilicon-based vertical electrothermal displacement actuator attached to the backside, and also two fixed lateral metal shields from the same Ni layer. Inductance tunability is achieved by changing the magnetic flux distribution associated with the loops by causing an out-of-plane movement of the spirals when the electrothermal actuation voltage or ambient temperature is changed. Mechanical and radio-frequency characterization of the inductor was carried out for both electrothermal and thermal actuation, with actuation voltage and chuck temperature ranging from 0 to 8V and 30 °C to 200 °C, respectively. In both cases, the inductance tuning ratio was 53.1% and 15.6%, with self-resonance frequency greater than 10 GHz.

Study on processing step uniformity tuning during FET fabrication and sensor wafer response as a function of chuck temperature adjustment

The effect of chuck temperature adjustment on critical dimension uniformity was studied for the shallow trench isolation etch process by introducing a temperature gradient in a multi-temperature-zone electrostatic chuck. It is shown that the initial radial critical dimension non-uniformity can be improved by a gradual temperature adjustment of the electrostatic chuck and results in the target specification values of uniformity, 3σ ≤ 1.5 nm, for a critical dimension of about 35 nm. Both temperature and RF sensor wafers were used to analyze the impact of an electrostatic chuck temperature gradient on process uniformity by utilizing their unique in situ spatial and temporal mapping capabilities. Thus, the across-wafer thermal sensitivity of the critical dimension was estimated for dense structures: a temperature change of 1 °C leads to a critical dimension change of ∼0.7 nm. The RF sensor wafer was also shown to have a clear response of RF current uniformity to the electrostatic chuck temperature gradient that suggests there could be other phenomena affecting critical dimension uniformity besides temperature itself. The pure temperature contribution to critical dimension change was found to be less than 0.3 nm/°C for the temperature range studied. Finally, a possible mechanism of critical dimension tuning is discussed and an assessment of each separate etch step’s sensitivity to the electrostatic chuck temperature gradient is performed.

Pattern transfer of directed self-assembly patterns for CMOS device applications

A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant patterning in the sub-30-nm pitch regime using directed self-assembly (DSA) line–space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck temperature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal–oxide–semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node.

Patterning Aspects of SiGe/Ge BFFT Fabrication

The sub20-nm wide SiGe bulk FinFET (BFFT) transistor structures have been fabricated by top-down direct patterning of the blanket strain-relaxed buffer (SRB) SiGe layer. The results of both the SiGe FIN patterning and the offset spacer etch stopping on a strained Ge channel are presented in this paper. The SiGe FIN geometry has been adapted starting from 300-nm deep (used for Si BFFT) to a 100-nm shallow but tapered FIN structure by using a newly-developed HBr/Cl2/O2/CH2F2 etch chemistry. Following standard replacement metal gate (RMG) flow, an offset spacer etch has been performed by using the low-bias CH3F/O2-based chemistry applied either with or without a SiCl4 additive. The best spacer-etch selectivity of 20 towards both the SiO2 and the Ge layers has been achieved at 200V bias and 75oC chuck temperature for the recipe selected. The final validation of the process has come from the following step of successful low-thermal-budget epitaxial growth of SiGe in the source-drain region (used for silicidation), which would not happen if there was complete consumption of the 20-nm thick strained Ge channel.

Aerosol jet printed grid for ITO-free inverted organic solar cells

Aerosol jet printing is investigated as a new deposition method for a current collecting grid in indium tin oxide (ITO) free organic solar cells with an inverted layer sequence. In this device configuration, the ITO layer which usually serves as the hole contact is replaced by a transparent highly conductive poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) layer in combination with a silver grid deposited by aerosol jet printing. Since the cells are illuminated from the grid side, the optimisation of the grid design is a trade-off between area coverage and conductivity of the grid lines. These factors have been controlled by the printing parameters such as chuck temperature, printing speed and the number of printing passes. In this paper, we demonstrate that continuous, conductive grid lines with a minimum line width of 58μm can be processed on the top of the PEDOT:PSS layer. For single pass printing the area coverage varied from 5.8% to 11.9% with corresponding effective sheet resistances ranging from 8.9Ω to 1.5Ω. The ITO-free inverted devices with aerosol jet printed grid (an active area of 1.1cm2) show comparable performance to the cells with an evaporated gold grid. The effective sheet resistance can be further decreased by multiple printing passes without increasing the area coverage proportionally due to an improved aspect ratio. By increasing the conductivity and aspect ratio by multiple line printing, the cell length in the module structures can be significantly extended.

Scatterometry analysis of sequentially imprinted patterns: Influence of thermal parameters

Graphical abstractDisplay Omitted Highlights? Thermal Step and Repeat NIL processes characterized by scatterometry. ? Scatterometry demonstrates high accuracy to quantify imprinted lines on silicon. ? Polymer reflow due to heat diffusion has been studied as a function of printing parameters. Scatterometry technique has been used to characterize Thermal Step and Repeat NIL processes in the framework of NAPANIL project. Two hundred and fifty nanometers dense lines were imprinted in mr-7030 polymer and their profiles have been analyzed and compared to the mold one. It has been demonstrated that scatterometry on silicon exhibits a very high accuracy and that a change of the sidewall verticality of only few degrees can been measured. The results show that some reflow occurs in lines during the imprint of neighboring dies due to heat diffusion. This phenomenon has been studied as a function of printing temperature, demolding temperature, and space between adjacent dies. The conclusion is that a trade off has to be made between imprint temperature and chuck temperature to be able to fill mold cavities with a limitation of the reflow.

Influence of Platinum Bottom Electrodes on the Piezoelectric Performance of PZT Thin Films Hot Sputtered in a High Volume Production Tool

ABSTRACTIn this work high quality ferroelectric PZT films have been prepared in-situ by hot RF magnetron sputtering. 200 mm wafer were coated with PZT films of 1 μm and 2 μm thickness at sputter rates of 45 nm/min in a high volume production sputtering tool. The films were grown on oxidized Si substrates prepared either with sputtered Ti/TiO2/Pt, sputtered Ti/TiO2/Pt/TiO2 or evaporated Ti/Pt bottom electrodes at substrate holder temperatures in the range from 550 °C to 700 °C. At these temperatures, the material nucleates in the requisite piezoelectric perovskite phase without need of an additional post annealing treatment.The films were investigated with respect to their chemical composition and their crystallographic, piezoelectric and dielectric properties. At an intermediate chuck temperature of 600 °C the PZT thin films were characterized by a minimum volume fraction of secondary nonpiezoelectric phases. A Zr/(Zr+Ti) ratio of 0.53 has been achieved matching the morphotropic phase boundary. By improving the deposition process and poling procedure, a notable high e31,f coefficient of -17.3 C/m2 has been obtained. The corresponding longitudinal piezoelectric constant was determined to have an effective longitudinal piezoelectric coefficient d33,f of 160 pm/V.

SUEX Laminates for Fan-In, Fan-Out and eWLB Development

The focus of this presentation is on the use of SUEX epoxy Thick Dry Film Sheets (TDFS) as a photoimagable dielectric layer in fan-in, fan-out and e-WLP applications. The sheets can be laminated over severe topography from under 2 μm to over 200 μm in height yielding void free coatings with 100% planarization over the entire substrate. The TDFS are available in a range of thicknesses and wafer or panel sizes. This new material is prepared under a highly controlled solvent-less process, which provides uniform coatings between two throw-away layers of protective polyester film. SUEX sheets of 100 μm thickness have been vacuum laminated in an isothermal process at 60–80°C over 180 μm high, 2mm X 2mm device chips mounted onto a silicon carrier wafer. Process optimization studies were run to determine the desired chamber vacuum, chuck temperature, lamination pressure and lamination time for optimal performance. The entire lamination process has a cycle time of about 10min. Using a vacuum laminator we have been able to obtain totally void-free coatings over 2 to 5 μm high bonding pads and buss lines at the silicon surface with a resist thickness of 205 μm over the trench and 25 μm thickness over the back of the chip with 100% planarization over the surface interface. Exposures on a contact aligner have yielded nominal 50 μm diameter via holes through the resist film to the contact pads at the bottom of the trench. Excellent adhesion to all surfaces on both the carrier wafer and the device chip has been obtained without any delamination or crack formation. Additional work to be presented will demonstrate the filling of the vias with electroplated copper to form interconnects the interconnects to for connection to bonding pads on the fan-out package surface.

Photoresist removal using an O2∕N2 medium pressure plasma jet with high speed wafer scanning: Unimplanted resist studies

The authors describe a plasma ashing system where a stationary jet of hot, activated gases removes photoresist from a scanning wafer. The jet is created by a reactant stream flowing through a 2.45GHz surface wave discharge in a 6mm quartz tube. For O2∕N2 plasmas in the medium pressure range from 20to100Torr, a luminous plasma jet emerges from the end of the discharge tube that transports both heat and reactive species to the wafer. A single scan results in a Gaussian track profile with a standard deviation of 7mm for the source-to-substrate distance of 9mm. A simple model of the ashing process, which assumes a thermally activated ash rate and Gaussian distributions for both power density and reactant flux, unifies the dependence of effective ash rate on the substrate temperature and scan speed at a constant power. The best fit activation energy at 2.5kW is 0.23eV, about half of the value found in conventional downstream ashing, implying that diffusion plays a significant role in limiting the ash rate. The peak thermal power density in a 2.5kW jet at 80Torr is 160W∕cm2, resulting in an effective instantaneous ash rate of 2.5mm∕min for a scan speed of 70cm∕s and 200°C chuck temperature. This implies that the time to clear a 1.2μm thick resist coating from a 300mm wafer is 18s.

Deactivation Induced Within Wafer Nonuniformity During Nonmelt Laser Annealing of Arsenic and Phosphorus Implanted Silicon

In the setup for nonmelt laser spike anneal (LSA), the wafer is mounted with the front-side facing the laser beam and backside facing the heated hotplate. When arsenic or phosphorus-implanted silicon is subjected to LSA, sheet resistance degradation, indicative of dopant deactivation, is observed when the post-LSA thermal budget provided by the heated chuck (hotplate) is increased. This additional thermal budget is associated with the chuck temperature and duration a wafer is left on the chuck after LSA. The deactivation is believed to occur due to the ineffective removal of implantation damage by LSA, giving rise to the release of point defects during the post-LSA thermal cycle that aids inactive clusters formation. The observed phenomena severely degrades the within wafer uniformity since LSA is a localized heating process that relies on scanning the laser beam across the whole wafer. As such, different portions of the implanted silicon wafer will remain on the hotplate for varying durations depending on when the laser beam scans through a particular spot. By adopting a dual step source/drain anneal scheme that incorporates a spike rapid thermal annealing condition sufficient to anneal out the implantation damage prior to LSA, the within wafer nonuniformity issue can be rectified.

Patterning of narrow porous SiOCH trenches using a TiN hard mask

For the next technological generations of integrated circuits, the traditional challenges faced by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects, …) become more and more difficult, intensified by the use of new materials, the limitations of lithography, and the recent introduction of new device structures and integration schemes. Particularly in the field of the interconnect fabrication, where dual-damascene patterning is performed by etching trenches and vias in porous low-k dielectrics, the main challenges are in controlling the profile of the etched structures, minimizing plasma-induced damage, and controlling the impact of various types of etch stops and hard mask materials. Metallic hard masks can help thanks to their high selectivity toward low-k materials, and by avoiding low-k exposure to potentially degrading ashing plasmas. In this paper, we will present some key issues related to the patterning of narrow porous SiOCH trenches with a metallic (TiN) hard mask. Narrow trenches (down to 40 nm width) can be opened into TiN with a critical dimensions bias (around 10 nm) attributed to carbon and silicon containing deposits on the photoresist and TiN sidewalls during the etching. Porous SiOCH etching using a TiN hard mask instead of the conventional SiO 2 hard mask may lead to severe profile distortions, attributed to TiF x compounds which settle on the trenches sidewalls. A chuck temperature of 60 °C and fluorine-rich plasmas are required to minimize those distortions. An etching process leading to almost straight porous SiOCH profiles presenting a slight bow has been developed. However a wiggling phenomenon has been evidenced for the etching of narrow and deep trenches. This phenomenon is attributed to the highly compressive residual stress in the TiN hard mask, which is released when the dielectric is not mechanically strong enough to withstand it.

Stacked Boron Doped Poly-Crystalline Silicon-Germanium Layers: an Excellent MEMS Structural Material

ABSTRACTIn this work stacked boron doped poly-crystalline Silicon-Germanium (poly-SiGe) layers, which can be applied as structural MEMS layers, were studied. A standard 1 µm base layer, deposited at 480 ºC chuck temperature, is stacked until the required thickness (e.g. 10 x for a 10 µm thick layer). This 1 µm base layer consists of a PECVD seed layer (+/− 75 nm), a CVD crystallization layer (+/− 135 nm) and a PECVD layer to achieve the required thickness with a high growth-rate. The top part of this PECVD layer can optionally be used for optimizing the stress gradient by a stress compensation layer. This approach resulted in 4 µm thick poly-SiGe MEMS structural layers with low tensile stress (50 MPa), low resistivity (2 mΩcm) and a low strain gradient (&lt; 1*10−5/µm).

Effect of Clamping Ring Materials and Chuck Temperature on the Formation of Silicon Nanograss in Deep RIE

In this paper, we report the effect of clamping ring materials and the chuck temperature on the formation of silicon grass in deep reactive ion etching (RIE), carried out with an Alcatel A601E etching tool. In the beginning, rectangular trenches of varying widths were etched with conventionally used aluminum clamping rings and later with ceramic rings, keeping other parameters unchanged. Scanning electron microscope images of etched trenches reveal that needle-shaped silicon grass structures were formed on the bottom of the trenches etched with an aluminum ring. Formation of silicon grass was more severe in wider trenches and near the wafer edges; however, the bottom silicon grass was eliminated when trenches were etched with a ceramic ring. Formation of silicon grass is mainly due to “micromasking” caused by sputtered aluminum particles. Due to continuous bombardment of highly reactive radicals (, , and other neutral atoms) on the wafer and surrounding aluminum ring, some aluminum atoms are physically displaced and deposited on the wafer. These micrometer-size aluminum particles deposited on the silicon wafer start acting as a mask layer and prevent the etching of the silicon area beneath them. Due to this aluminum mask, the local silicon etching rate is reduced drastically compared to other silicon areas, hence gradually vertical-grass-type silicon structures start forming. Because more aluminum atoms are deposited near the wafer edges, the amount of silicon grass is nearer the edges than in the center. As the ceramic ring is an insulator, it is not polarized by radio frequency power; hence, there is no ion-bombardment phenomenon and no sputtering of foreign particles. Due to the absence of such micromasking, the silicon grass formation is completely eliminated.

Sub-100 nm MOSFET fabrication with low temperature resist trimming process

A low temperature resist trimming process with low trimming rate and good uniformity was developed. Wafer chuck temperature in the ashing chamber was adjusted to be 6 °C to achieve low trimming rate and improve process uniformity. Low power oxygen and argon plasma was used for ashing the resist. Resist lines (0.5 μm wide) patterned with a g-line stepper was trimmed down to sub-100 nm widths. The trimming rate was found to be independent of the initial line width and trimming time. A 0.6 μm CMOS process flow with LOCOS and nitride spacer was suitably modified incorporating resist trimming to fabricate NMOSFETs with gate length as small as 95 nm. Since most polymer-based photoresists can be etched in oxygen plasma, the basic technique could be extended to supplement other lithographic processes for channel length scaling.

Inductively coupled plasma etching of GaAs low loss waveguides for a traveling waveguide polarization converter, using chlorine chemistry

A traveling waveguide polarization converter [M. Poirier et al.] has been developed, which involves long, low loss, weakly confined waveguides etched in GaAs (epitaxially grown by molecular beam epitaxy), with electroplated “T electrodes” distributed along the etched floor adjacent to the ridge walls, and airbridge interconnect metallization. This article describes the development of the waveguide fabrication, based on inductively coupled plasma (ICP) etching of GaAs using Cl2 chemistry; the special processes required to fabricate the electrodes and metallization [X. Meng et al.], and the device characteristics [M. Poirier et al.], are described elsewhere. The required waveguide has dimensions nominally 4 μm wide and 2.1 μm deep, with dimensional tolerances ∼0.1 μm across the wafer and wafer to wafer. A vertical etch profile with very smooth sidewalls and floors is required to enable the plated metal electrodes to be fabricated within 0.1 μm of the ridge. The ridges were fabricated using Cl2 ICP etching and a photoresist mask patterned with an I-line stepper; He backside cooling, combined with an electrostatic chuck, was employed to ensure good heat transfer to prevent resist reticulation. The experimental results showed that the ridge profile is very sensitive to ICP power and platen rf power. High ICP power and low platen power tend to result in more isotropic etching, whereas increasing platen power increases the photoresist etch rate, which causes rougher ridge sidewalls. No strong dependence of GaAs etch rate and ridge profile were observed with small changes in process temperature (chuck temperature). However, when the chuck temperature was decreased from 25 to 0 °C, etch uniformity across a 3 in. wafer improved from 6% to 3%. Photoresist and polymer residues present after the ICP etch were removed using a combination of wet and dry processes.

GaInNAs(Sb) vertical-cavity surface-emitting lasers at 1.460 μm

We demonstrate a top emitting, electrically pumped, GaInNAsSb vertical-cavity surface-emitting laser (VCSEL) grown monolithically on GaAs, lasing pulsed at a wavelength of 1.460 μm, at a chuck temperature of −10 °C, with a threshold current of 550 mA (16 kA/cm2) and a duty cycle of 0.1% for large mesas. Dilute nitrides, such as GaInNAs, have proven effective for lasers operating at 1.31 μm, but reaching longer wavelengths has proven difficult due to defects from low-temperature growth, surface roughening, and nitrogen-related defects. Reduction of oxygen contamination and careful attention to plasma conditions allow a similar extension to laser wavelength, by minimizing crystal defects introduced during growth. This is the first VCSEL on GaAs beyond 1.31 μm to date.