Chip Package Research Articles

Transforming the preservation of tomato derivatives: Innovations in packaging and storage

The production and consumption of vegetables, such as tomatoes, have been growing in recent years, due to the combination of several factors, such as market demand, investment in research, education and awareness about health benefits, as well as government incentives and improvements in cultivation technology. The combination of these factors results in an increasing demand for products that offer health benefits, such as tomatoes rich in antioxidants, which help combat free radicals in cells. To maintain most of the nutritional and sensory properties characteristic of the fresh product, it is important to identify the parameters that will help in maintenance. Thus, the study aims to characterize the influence of different packages and storage times with the variables of tomato. The experiment examined the storage of two tomato derivatives (atomized tomato and chips) using various packaging types and storage durations. It utilized a factorial design (2 × 4) with an extra control treatment, comprising 3 replications. Packaging options included low-density polyethylene plastic bags and laminated plastic bags with aluminum foil, while storage durations ranged from 10 to 40 days. Parameters related to color (°Hue and chroma), flavor (pH, titratable acidity, soluble solids, and maturation index), and bioactive compounds (lycopene and β-carotene) of two tomato derivatives (atomized tomato and chips) were analyzed. After the analyzes, it was observed that the transparent package was the one that allowed the best conservation among the studied variables of the atomized tomato derivative, the same happened for the laminated packaging for the derivative chips. Regarding storage time, 20 days showed the best results regarding the conservation of flavor and bioactive compounds.

Reactive cold sintering of dense barium sulfate ceramics for high-reliability chip packaging in integrated circuits

Reactive cold sintering (RCS) is an innovative ceramic consolidation technique that combines a low-temperature reaction with the cold sintering process. In this work, equimolar (CH3COO)2Ba and (NH4)2SO4 were homogeneously mixed to obtain a reactive activator abbreviated as RA and then added to barium sulfate (BaSO4) powder obtaining BaSO4–xwt%RA (x = 5, 7.5, 10, 12.5, and 15). Dense (>96 % theoretical) BaSO4 ceramics were successfully fabricated via RCS of BaSO4–xwt%RA at 200℃ with a constantly applied pressure of 250 MPa. The Woolfrey-Bannister method provided quantitative insights into the activation energy, indicating that RA effectively reduced the energy required for densification. The Vickers hardness (1.76 GPa) and coefficient of thermal expansion (CTE, 18.8 ppm/°C) of the RCSed BaSO4 ceramics were comparable to the high-temperature (850 °C) sintered counterparts. Moreover, finite element analyses confirmed the high CTE value of the RCSed BaSO4 ceramics holds great promise for high-reliability chip packaging applications.

Investigation on memory package crack and prevention under temperature cycling test

Memory package with multiple die stacking in one package faced package crack issue during package level temperature cycling test (TCT) and the failure cycle cannot meet reliability requirement. Failure analysis showed epoxy molding compound (EMC) cracking located at the center area of package surface. Finite element modeling and simulation was conducted to study package stress and failure mechanism under cyclic temperature loading condition. Simulation results showed that the center of package surface is subjected to higher stress and stress variation during stringent TCT test due to high and tight die stacking structure. Several parametric studies were conducted to further understand failure mechanism and provide solution for crack prevention. Design guideline was proposed to eliminate or reduce package crack risk for multi-chip package (MCP) in memory chip package.

Additive Manufacturing Based Dissolvable Chip Packaging for Sustainable E‐Waste Reduction

Additive Manufacturing Based Dissolvable Chip Packaging for Sustainable E‐Waste Reduction

Influence of exposure to novel food packaging on consumers’ adoption of innovative products

Innovation is a crucial element for achieving success in the food industry. Previous research has shown that color-flavor incongruent packaging designs possess the capacity to violate consumers’ expectations, thus signifying the innovativeness of a brand without necessitating alterations to the properties of the food products themselves. Here we report two experiments designed to examine whether exposure to such color-flavor incongruent packaging designs could influence consumers’ intentions to adopt innovative products. The results of Experiment 1 revealed that exposure to color-flavor incongruent packaging of potato chips with popular flavors increased the likelihood of participants to purchase the same food products with novel flavors. As for the participants with a relatively higher level of cognitive flexibility, the results of Experiment 2 revealed that such exposure to the novel packaging designs of familiar foods not only heightened their interest in buying but also amplified their likelihood to purchase certain innovative non-food products. Collectively, these findings suggest that exposure to novel packaging designs for familiar food products may enhance certain consumers’ intentions to adopt certain innovative products. Our findings highlight the role of unexpected and surprising experiences with food packaging in consumer behavior, offering valuable insights into possible strategies for promoting innovative products in the market.

Research on Low-Insertion-Loss Packaging Materials for DC-6 GHz Attenuation Chips

Research on Low-Insertion-Loss Packaging Materials for DC-6 GHz Attenuation Chips

ANALISIS PENGARUH MATERIAL KEMASAN, TAMPILAN KEMASAN, BENTUK KEMASAN, DAN INFORMASI PADA KEMASAN TERHADAP MINAT BELI MAKANAN KHAS LAMPUNG KERIPIK PISANG

The aim of this research is to investigate the influence of packaging material, packaging appearance, packaging shape, and information on the packaging on consumer purchasing interest in Asa Cipto Roso MSMEs, Siger Keripik MSMEs, and Lampung Chips MSMEs. The method applied in this research is the PLS-SEM method with the help of software in the form of SmartPLS 3.0. Research data was collected from 120 respondents who were banana chips consumers at Asa Cipto Roso MSMEs, Siger Keripik MSMEs, and Lampung Chips MSMEs which were distributed via an online Google form. The findings from this research illustrate that packaging elements which include packaging material, packaging appearance, packaging shape, and information on the packaging can trigger consumer buying interest in Asa Cipto Roso MSMEs, Siger Keripik MSMEs, and Lampung Chips MSMEs. The findings from this research can provide implications for designing banana chip packaging that suits consumer tastes so that it can trigger consumer buying interest in Asa Cipto Roso MSMEs, Siger Keripik MSMEs, and Lampung Chips MSMEs.

Impact of Hydrogen Voiding in Chip-to-Chip Electroless All-Copper Interconnections.

Three-dimensional (3D) integration has become a leading approach in chip packaging. The interconnection density and reliability of micro-bumps in chip stacking are often threatened by high bonding temperatures. The method of building chip-to-chip interconnections by electroless deposition of metal has its distinct merit, while the interfacial defect issue, especially that related to voiding during the merging of opposite sides, remains largely unsolved. In this study, to trace the influencing factors in the voiding, the growth characteristics of the electroless all-copper interconnections were examined by carrying out deposition experiments in a microfluidic channel device. The results show that when the gap between the opposite copper bumps to be electrolessly merged is as low as 10 μm, significant voids appear at the inflow side and the top of the copper bumps because the hydrogen cannot be expelled in time. A finite-element flow model of the plating solution between the chips was established, which showed that the flow rate of the plating solution around the copper bumps was much higher than in the merging gap, causing an uneven supply of reactants. Based on these findings, we proposed two potential solutions, one is to improve the flow mode of the plating solution, and the other is to add the reaction inhibitor, 2,2'-bipyridine. Finally, the combination of these two approaches successfully achieved an improved merging quality of the copper joints.

Systematic analysis of microelectronic chip packaging materials

Microelectronics is a recent hot field, and packaging is an indispensable part of making microelectronic chips. This article introduces the commonly used materials in the field of microelectronic chip packaging. It first presents two complex polymer raw materials recently becoming hot topics, namely epoxy resin and silicone. Then the article presents these two materials from the perspectives of their characteristics, advantages in packaging, and further research directions, allowing readers to have a basic understanding of them while also gaining a general understanding of their research progress. Afterward, the article introduces three crucial types of functional materials in packaging. The article not only presents their respective uses, but also classifies them from the main material types. The article not only analyzes the characteristics and application fields of each material, but also provides some existing in-depth research directions for reference. This article helps readers quickly understand the relevant knowledge of some microelectronic chip packaging materials, especially in determining their future research direction.

Correlation Study on Voiding in Underfill of Large Quantity Ball Grid Array Chip Using Machine Learning

Abstract This paper investigates voiding issues in the underfilling process of ball grid array (BGA) chip packages under various parameter settings such as chip conveyor speed, valve pressure, temperature, and dispense pattern complicate. The study identifies valve pressure as the primary cause of voiding in large quantity BGA chips, achieving 88.9% in accuracy, supported with the deformation of the valve nozzle. Additionally, the findings reveal that racing effects occurs due to asymmetry of the solder ball array arrangement with percentage difference between the TSAM BGA chips experiments and its simulation counterparts in the range of 0.089–3.65%.

A High Copper Concentration Copper-Quadrol Complex Electroless Solution for Chip Bonding Applications.

This article presents a novel bonding method for chip packaging applications in the semiconductor industry, with a focus on downsizing high-density and 3D-stacked interconnections to improve efficiency and performance. Microfluidic electroless interconnections have been identified as a potential solution for bonding pillar joints at low temperatures and pressures. However, the complex and time-consuming nature of their production process hinders their suitability for mass production. To overcome these challenges, we propose a tailored plating solution using an enhanced copper concentration and plating rate. By eliminating the need for fluid motion and reducing the process time, this method can be used for mass production. The Taguchi approach is first used to optimize the copper-quadrol complex solution with the plating rate and decomposition time. This solution exhibits a copper concentration that is over five times higher than that of conventional solutions, a plating rate of 22.2 μm/h, and a decomposition time of 8 min on a Cu layer substrate. This technique enables Cu pillars to be successfully bonded within 7 min at 35 °C. Planarizing the pillar surface yields a high bonding percentage of 99%. Mechanical shear testing shows a significant fracture strength of 76 MPa.

Review of RF microsystem packaging process technology

The 3-D heterogeneous integration technology of microsystem is the best technical means to achieve higher integration, higher performance and higher working frequency of radio frequency (RF) electronic system. RF microsystem integration technology is categorized into three main types based on the packaging substrate: silicon-based, ceramic-based, and resin-based. In this work, the principle of RF microsystem integration technology is demonstrated in detail, and the process routes and characteristics of different packaging structures are clarified. Moreover, through the multi-dimensional comparison of different packaging structures, the application conditions of specific packaging structures are obtained. According to the comprehensive evaluation, the resin-based embedded chip package shows outstanding potentials in RF performance, integration capability, batch production capability and process cost. However, there are three shortcomings that limit its application in RF microsystems: Firstly, in terms of the universality of RF chips, metal grounding on the back of RF chips cannot be realized by this packaging, and special design of RF chips is required. At present, however, the universal chip with gold back grounding on the market cannot meet the requirements of the packaging process. Secondly, because of the high cost of customized chips, this packaging process is not suitable for small-scale production. Thirdly, the resin-based package does not have the sealing function, thus reliability of the product still needs to be verified. Ceramic-based RF microsystems do not require customized chips and have advantages in chip versatility compared to resin-based systems, with integration capabilities comparable to resin-based systems. However, its batch production capacity is much lower than resin based. In contrast, the silicon-based embedded chip package is as excellent as the resin-based products in chip versatility, RF performance, integration capability, batch production capability, etc., except that the manufacturing cost is high, and the yield should be effectively guaranteed in the manufacturing process. The conclusion provides a guidance for the future research of RF microsystem integration technology.

Polyimide Films Based on β-Cyclodextrin Polyrotaxane with Low Dielectric and Excellent Comprehensive Performance.

In order to prepare polyimide (PI) films with a low dielectric constant and excellent comprehensive performance, a two-step method was employed in this study to integrate β-cyclodextrin into a semi-aromatic fluorine-containing polyimide ternary system. By introducing trifluoromethyl groups to reduce the dielectric constant, the dielectric constant was further reduced to 2.55 at 10 MHz. Simultaneously, the film exhibited noteworthy thermal stability (a glass transition temperature exceeding 300 °C) and a high coefficient of thermal expansion. The material also demonstrated outstanding mechanical properties, boasting a strength of 122 MPa and a modulus of 2.2 GPa, along with high optical transparency (transmittance reaching up to 89% at 450 nm). Moreover, the inherent high transparency of colorless polyimide (CPI) combined with good stretchability contributed to the attainment of a low dielectric constant. This strategic approach not only opens up new opportunities for novel electroactive polymers but also holds potential applications in flexible displays, circuit printing, and chip packaging.

A modified Qian-Liu constitutive model based on advanced packaging underfill materials

—The high integration and multifunctionality of microsystem packaging have led to a gradual reduction in packaging size, bringing changes in materials, structures, and processes. This has resulted in numerous issues related to structural reliability and signal integrity. To address the problems of stress concentration during chip packaging, underfill materials are typically introduced beneath the chip. Therefore, the appropriate underfill selection significantly impacts chip reliability. In this work, a modified Qian-Liu constitutive model is proposed to describe the viscoplastic deformation of underfill. The new model accurately predicted the overall trend of stress-strain behavior for the temperature range from 298K to 398K and the strain rate range from 0.0001s−1 to 0.00ls-1. Constitutive parameters of the underfill over a wide temperature range based on the modified Qian-Liu model were obtained. A comparison between the experiment and simulation verified that the modified Qian-Liu model reasonably simulated the viscoplastic stress-strain relationships for underfill materials.

Effect of Dispensing Type On Void Formation Using Convolutional Neural Network

Abstract Underfilling in flip chip packages is a critical component of reliability. This study utilized I-type, L-type, and U-type dispensing methods to address the issue namely voiding that creates empty spaces which compromises reliability. An automated solution using Convolutional Neural Network (CNN) is propose for void detection in chip images to replace the conventional manual inspection approach. The CNN model built on MobileNetV2, attains a mean average precision of 0.533. This method calculates void percentage, adhering to IPC standards, to determine product acceptance or rejection, offering an efficient solution for quality control in flip-chip package manufacturing.

Surface wave communication-based wave guide design concerns for flip chip package-based integrated circuits with bump pitch sizes of 1.2 mm and above

ABSTRACT The flip chip package (FCP) based integrated circuits supports millimetre wave frequency range (30 - 300 GHz), analysing the conditions for optimal signal transmission between the integrated circuits for FCP type being the primary essence of this article. The effective signal transmission occurs through a dielectric-coated conductor structure based on the surface wave communication phenomenon, known as a surface wave communication-based wave guide (SWW). The article focuses primarily on design considerations to build SWW for FCP applications at millimetre wave frequency ranges. The efficiency of the proposed waveguide was investigated in terms of power transmission capacity, voltage standing wave ratio (VSWR) and signal attenuation. The analysis comprises examining these parameters at the frequency range of 50 GHz to 150 GHz while taking into account varied degrees of waveguide dimensions and surface reactance. The measured results show that at the signal frequency of 100 GHz with dielectric and conductor thickness of 0.2 mm and surface reactance of 100 Ω, the suggested waveguide provides efficient signal transmission with approximately 0 dB signal attenuation, ideal high-power flow of 41,000 VA m 2 and VSWR of 1.2. Overall, this article provides insights on the design and performance of SWW for FCP applications at millimetre wave frequency band.

In situ monitoring of flip chip package process using thermal resistance network method and active thermography

Flip chip technology has been used extensively in microelectronic packaging due to the high density, fine spacing, smaller size. However, the size and spacing of the solder bumps are decreasing gradually, defect detection is getting more and more difficult. Thus, the growing demand for high reliability has generated considerable attention on the importance of defect inspection. This paper proposes an in-situ infrared thermography monitoring method with in situ monitoring system bases on modified thermal resistance network model that added the phase transition for the non-destructive analysis of packaging process. The different defects, such as missing bump and pad, missing bump, and bridge are inspected with an accuracy of up to 90 % based on in situ monitoring system. The maximum error between the model and the experiment is 27.6 %, while the minimum error is 13.6 %. The experiment results show that the max temperature of missing bump and pad, missing bump is 35.43 °C and 6.13 °C higher than normal, and the bridge is 0.44 °C lower than normal, respectively. The maximum amplitude by the Fourier transform is used to inspect due to the max temperature of normal and bridge are indiscernible, the results show that the bridge is 4 lower than normal. The model and experimental results show that the in-situ infrared thermography monitoring method is effective for detecting defects in high density electronic devices. The proposed method of in situ monitoring is expected to provide a new strategy for next generation of three-dimensional heterogeneous integrated chips defect inspection.

Pelatihan Pengemasan Produk Keripik Pisang Dan Stik Kulit Pisang Kepada Kelompok Tani Desa Lomaer, Sampang

Lomaer Village is one of the villages in Bangkalan Regency which has superior banana products. Bananas are processed into banana chips and banana peel sticks. However, the products that have been produced have not been packaged and labeled properly. Therefore, packaging training was carried out on banana chips and banana peel sticks for the Lomaer Village Farmers Group. Activities are carried out in two stages, namely, preparation and training. The training was held on Sunday, September, 12th 2021. The training participants were 30 members of the Lomaer Farmers Group, starting at 08.00-14.00 at the Lomaer Village Hall. Packaging training begins with a presentation of material about the function, purpose and appropriate packaging methods for food products. Next, the practice of packaging banana chips and banana peel sticks was carried out, then continued with labeling the packaging. The results of this training were able to increase participants' knowledge about the purpose, types and benefits of packaging and were able to practice packaging for banana chips and banana peel sticks

Characterizations for eWLB (Embedded Wafer Level Ball Grid Array) Antenna in Molded Package Integrations in 77GHz Automotive Applications

The worldwide IC market has had a significant growth rate in recent years, driving diversified package solutions in the segments of communication, computing, consumer, automotive, industrial, etc. Among these market segments, the automotive market is forecast to have the strongest CAGR (Compound Annual Growth Rate) of any of the end-use segments in the next 5 years, which results in more IC packages and components being designed into automotive vehicle systems such as infotainment, ADAS (Advance Driving Assistance System), instrumentation, body systems, battery control systems and so on. In these applications, the 77GHz short-range radar sensor application that can enable higher EIRP (Effective Isotropic Radiated Power) and adaptive cruise control performance has become more attractive to be commercialized. Due to the benefits of shorter interconnection length, lower conductive loss with smooth Cu surface as well as a lower dielectric constant and dielectric loss of materials in a fan-out wafer level package (FOWLP) technology, the FOWLP is proven as a suitable packaging solution to achieve the high speed and frequency requirements in 5G and mmWave applications. The eWLB Embedded Wafer Level Ball Grid Array) is a versatile FOWLP technology, providing a robust package platform in a space-efficient design with the very dense interconnection and routing of multiple dies as well as a smaller footprint and lower package profile providing a reliable package solution. Meanwhile, since the utilization of an antenna that is integrated into the packages has been studied as a lowcost solution because the packages can be tested in normal FR4 printed circuit board (PCB) instead of the RF function integrated PCB, the eWLB integrated with molded antenna chip packages (called eWLB antenna in molded package) technology is introduced in this paper. The characterizations for assembly process challenges are evaluated and illustrate the process optimizations of equipment handling, antenna molded chip package fabrication, reconstitution process control and warpage characterization of the molded wafer. In addition, the radio frequency (RF) test validation is performed to verify the performance of scattering parameter (S-parameter), radiation pattern, impedance and detection range of the antenna. In order to prove the reliable quality and yield of the evaluated eWLB antenna in molded packages, package-level reliability tests are studied. Through these results, it will show that this eWLB antenna in molded package integration is a robust and costeffective solution for 77GHz automotive applications.

Practical Study to Demonstrate an Increase in the Reliability of Flip Chip Connections by Adding Nanoparticles to Solder

The aims of the research are to improve the reliability and lifetimes of solder joints to contribute to the green economy, by reducing waste and extending recycling times. The objectives of the work are; to improve the materials properties of various solders used for attaching die/flip chip packages to PCBs by adding nanoparticles to the mix, to fabricate industrial test samples using flip chips soldered to PCBs, to test the reliability of the solder through accelerated testing, to examine failure modes and lifetime extensions.