Chip-level Reliability Research Articles

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Solid-state lightings (SSL) rapidly penetrate the global illumination market because of the energy efficiency and the reliability. The energy efficiency can be easily evaluated but the reliability is not convenient to be estimated. Among several reliability issues, a LED chip level's reliability could be a difficult problem because chip failures related to electromigration phenomenon are hard to be detected in the early stages. In order to remove potential leakage LEDs in modules, additional screening method is necessary to be performed occasionally. In this study, chip package interaction (CPI) for LED packages was investigated in order to estimate stresses of the LED chip in the module level. This methodology would help LED manufacturers to perform a robust design of LED packages in terms of the LED chip reliability. The electromigration is related to metal diffusion, which belongs to a creep phenomenon. As the creep strain is a function of temperature, stress and time, quantifying stresses in the metal layers of the LED die can be useful information for LED manufacturers to make an engineering decision in the early stages of manufacturing.

Chip package interaction for LED packages

Solid-state lightings (SSL) rapidly penetrate the global illumination market because of the energy efficiency and the reliability. The energy efficiency can be easily evaluated but the reliability is not convenient to be estimated. Among several reliability issues, a LED chip level's reliability could be a difficult problem because chip failures related to electromigration phenomenon are hard to be detected in the early stages. In order to remove potential leakage LEDs in modules, additional screening method is necessary to be performed occasionally. In this study, chip package interaction (CPI) for LED packages was investigated in order to estimate stresses of the LED chip in the module level. This methodology would help LED manufacturers to perform a robust design of LED packages in terms of the LED chip reliability. The electromigration is related to metal diffusion, which belongs to a creep phenomenon. As the creep strain is a function of temperature, stress and time, quantifying stresses in the metal layers of the LED die can be useful information for LED manufacturers to make an engineering decision in the early stages of manufacturing.

A Large-Scale Study of Flash Memory Failures in the Field

Servers use flash memory based solid state drives (SSDs) as a high-performance alternative to hard disk drives to store persistent data. Unfortunately, recent increases in flash density have also brought about decreases in chip-level reliability. In a data center environment, flash-based SSD failures can lead to downtime and, in the worst case, data loss. As a result, it is important to understand flash memory reliability characteristics over flash lifetime in a realistic production data center environment running modern applications and system software. This paper presents the first large-scale study of flash-based SSD reliability in the field. We analyze data collected across a majority of flash-based solid state drives at Facebook data centers over nearly four years and many millions of operational hours in order to understand failure properties and trends of flash-based SSDs. Our study considers a variety of SSD characteristics, including: the amount of data written to and read from flash chips; how data is mapped within the SSD address space; the amount of data copied, erased, and discarded by the flash controller; and flash board temperature and bus power. Based on our field analysis of how flash memory errors manifest when running modern workloads on modern SSDs, this paper is the first to make several major observations: (1) SSD failure rates do not increase monotonically with flash chip wear; instead they go through several distinct periods corresponding to how failures emerge and are subsequently detected, (2) the effects of read disturbance errors are not prevalent in the field, (3) sparse logical data layout across an SSD's physical address space (e.g., non-contiguous data), as measured by the amount of metadata required to track logical address translations stored in an SSD-internal DRAM buffer, can greatly affect SSD failure rate, (4) higher temperatures lead to higher failure rates, but techniques that throttle SSD operation appear to greatly reduce the negative reliability impact of higher temperatures, and (5) data written by the operating system to flash-based SSDs does not always accurately indicate the amount of wear induced on flash cells due to optimizations in the SSD controller and buffering employed in the system software. We hope that the findings of this first large-scale flash memory reliability study can inspire others to develop other publicly-available analyses and novel flash reliability solutions.

A HIGH-SPEED MICRO-IMPACT TESTING SYSTEM FOR EVALUATING THE PROPERTIES OF LEAD-FREE SOLDER JOINTS

This study presents a novel high-speed micro-impact testing system for evaluating the shear strength and energy absorbance properties of lead-free solder ball joints under impact velocities of 0.3–1.0 m/s. The test method can examine the failure mode transition from ductile failure to brittle failure based on the failure mode distribution percentage. The load—displacement curves can distinguish between different failure modes. Notably, the values of peak load and the energy-to-peak load at various impact speeds can be used as indices for determining solder ball under impact loading conditions. Thus, the proposed method is a suitable technique for evaluating the mechanical response of solder ball joints used in typical semiconductor packages and, therefore, represents a simple and effective technique for optimizing the chip-level reliability of portable consumer electronic products.

Reliability computer-aided design tool for full-chip electromigration analysis and comparison with different interconnect metallizations

We have developed a set of methodologies for thermal aware circuit-level reliability analysis with either Al or Cu metallization in a circuit layout and implemented it in a public domain reliability CAD tool, SysRel. SysRel utilizes a hierarchical reliability analysis flow, with interconnect trees treated as the fundamental reliability unit, that sufficiently captures the differences in electromigration failure between Al and Cu metallizations. Under similar test conditions, the electromigration reliability of Al and Cu interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. Using the best estimates of material parameters and an analytical model, we present a detail comparison of electromigration reliability of a sample test-structure as well as of actual circuit layouts with Al and Cu dual-damascene interconnect systems. We also demonstrate fast thermal-analysis in SysRel for circuit performance driven chip-level reliability assessment.

Performance and Reliability of Low-Temperature Processed SrBi2Ta2 O 9 Capacitors for FeRAM Applications

Low-temperature processed (SBT) capacitors were tested as the ferroelectric memory cells of fully functional ferroelectric random access memory (FeRAM) devices. The 100 nm thick SBT films were deposited by the spin-on coating technique using a metallorganic decomposition source and crystallized by rapid thermal annealing at 700°C for 1 min followed by a furnace annealing at 650°C for 1 h under oxygen atmosphere, considered a low thermal budget process. The fabricated Pt/SBT/Pt capacitors showed reasonable ferroelectric performances with a (switching polarization-nonswitching polarization) of approximately 10 μC/cm2 after the full process integration. The FeRAM chip-level reliability analysis showed that the major reason for the function failure was from the opposite state retention characteristics due mainly to the small values. A 10-year guaranteed lifetime can be achieved when the operation voltage is higher than approximately 4 V at the test condition of 85°C operation and 125°C storage. © 2004 The Electrochemical Society. All rights reserved.

Copper may destroy chip-level reliability: handle with care-mechanism and conditions for copper migrated resistive short formation

Although copper has a number of advantageous parameters in comparison with aluminum, and therefore, is expected to become the metallization of future high-speed, high-density silicon devices, its application introduces a new failure mechanism into the systems which has never occurred with aluminum; this is the electrochemical migration (not equal to the electromigration) resulting in short circuit formation between adjacent metallization stripes under DC bias. A great alert signal must be given for semiconductor producers in order to perform lifetime tests before introducing copper into the everyday fabrication process, otherwise the reliability of future electronic systems may dramatically be destroyed.