Chemical Mechanical Polishing Tool Research Articles

Endpoint Detection Based on Optical Method in Chemical Mechanical Polishing.

Endpoint detection is an important technology in chemical mechanical polishing (CMP), which is used to capture the material interface and compensate the variations of consumables and incoming wafer thickness. This paper aimed to apply optical detection in metal CMP. An in situ optical measurement system was developed for a 12-inch CMP tool. Kinematic analysis of the scanning trajectory of the laser device indicated the relative position relationship between the device and the wafer. Average optical data within the wafer described the material removal of metal CMP. Furthermore, optical data and location described the non-uniformity of the entire wafer surface. In this research, the polishing condition and the residual of the wafer edge are characterized by optical trace. Pauta Criterion is used to discriminate the inflexion point of the material interface. The results reveal that the interface capture is accurate and effective.

Highest Quality and Repeatability for Single Wafer 150mm SiC CMP Designed for High Volume Manufacturing

Silicon Carbide (SiC) provides excellent characteristics such as superior thermal conductivity, high carrier mobility and extreme chemical stability in comparison with those of Silicon (Si). SiC is already showing significant device performance benefits in power devices, high performance communication, and LED lighting. However, SiC presents many challenges for wafer surface treatment because of its high hardness and remarkable chemical inertness. Today, mechanical polishing techniques on industrial batch CMP tools are the predominant methods for SiC wafer surface treatment, but material removal rate (MRR), surface defects and wafer flatness control are reaching fundamental limits with increasing wafer diameter. Batch processing typically results in a higher amount of surface scratches and defects, higher wafer to wafer variability, and higher wafer breakage rates. A unique single wafer chemical mechanical polishing (CMP) technique on 150mm n-doped, 4° off-axis, single crystal, 4H-SiC wafers was developed to create a virtually defect-free surface. A polishing head has been designed to manipulate polishing pressures at various zones of the wafer. This capability can modulate the removal thickness at each region on the wafer surface, resulting in a highly uniform wafer profile. Additionally, a CMP slurry has been formulated to maximize MRR from 2μm/hr to over 8.5μm/hr. Potassium permanganate has been selected as an oxidant and aluminum oxide particles as the abrasive. The oxidant concentration and abrasive content along with slurry pH level have also been optimized for ideal chemical and mechanical activity. Scratch-free wafer surfaces are observed with atomic force microscopy (AFM) and bright field (BF) and dark field (DF) inspection techniques. Roughness on the Si face is reduced to below 0.08nm. Total length of surface scratches was reduced to 10mm or less. Industrial metrics of wafer flatness, including total thickness variation (TTV) and local thickness variation (LTV) are modulated and improved. A test run completed on 25-wafers shows an overall 31% improvement of TTV post CMP process.

(Invited) Hybrid Wafer Bonding – The Fusion of Low Temperature Dielectric and Metal Bonding Technologies

There are two driving goals in wafer bonding. One is to use wafer bonding methods to engineer starting materials; to integrate silicon with any other material to enable hetero-device architectures. The second is to continually shrink device footprints by bonding layers of devices vertically. Low temperature wafer bonding combined with advances in CMP (chemical mechanical polishing), temporary bonding, and advanced metrology characterization tools are enabling researchers to achieve these goals. In particular, hybrid bonding, which enables simultaneous bonding of dielectric and metallic regions at an interface has produced extremely high-performance devices and miniaturization of display technologies. This talk will highlight the various requirements for hybrid bonding and critical specifications for implementing complex bonding methods.

(Invited) Hybrid Wafer Bonding – The Fusion of Low Temperature Dielectric and Metal Bonding Technologies

There have typically been two pinnacle goals in wafer bonding. The first and ongoing goal is to use wafer bonding methods to engineer starting materials; to integrate silicon with any other material to enable hetero-device architectures. The second aspiration is to continually shrink device footprints by bonding layer upon layer of devices vertically. Low temperature wafer bonding combined with advances in CMP (chemical mechanical polishing), temporary bonding, and advanced metrology characterization tools are enabling researchers to achieve these dreams come true. In particular, hybrid bonding, which enables simultaneous bonding of dielectric and metallic regions at the bond interface has produced extremely high performance devices and miniaturization of display technologies. This talk will highlight the various requirements for hybrid bonding and critical specifications for implementing complex bonding methods.

Data-driven Approach to Material Removal Rate Prediction in Chemical Mechanical Polishing

Chemical mechanical polishing (CMP) has been widely used in the semiconductor sector for creating planar surfaces with the combination of chemical and mechanical forces. CMP is very complex because several chemical and mechanical phenomena (e.g., surface kinetics, contact mechanics, stress mechanics, and tribochemistry) are involved. Due to the complexity of the CMP process, it is very challenging to predict material removal rate (MRR) with sufficient accuracy. While physics-based methods have been introduced to predict MRR, little research has been reported on data-driven predictive modeling of MRR in the CMP process. This paper presents a novel decision tree-based ensemble learning algorithm that trains a predictive model of MRR on condition monitoring data. A stacking technique is used to combine three decision tree-based learning algorithms, including the random forests (RF), gradient boosting trees (GBT), and extremely randomized trees (ERT). The proposed method is demonstrated on the data collected from a wafer CMP tool that removes material from the surface of the wafer. Experimental results have shown that the decision tree-based ensemble learning algorithm can predict MRR in the CMP process with very high accuracy.

Effect of Brush Treatment and Brush Contact Sequence on Cross Contaminated Defects during CMP in-situ Cleaning

Chemical mechanical polishing (CMP) is one of the most important processes for enabling sub-14 nm semiconductor manufacturing. Moreover, post-CMP defect control is a key process parameter for the purpose of yield enhancement and device reliability. Due to the complexity of device with sub-14 nm node structure, CMP-induced defects need to be fixed in the CMP in-situ cleaning module instead of during post ex-situ wet cleaning. Therefore, post-CMP in-situ cleaning optimization and cleaning efficiency improvement play a pivotal role in post-CMP defect control. CMP in-situ cleaning module normally consists of megasonic and brush scrubber processes. And there has been an increasing effort for the optimization of cleaning chemistry and brush scrubber cleaning in the CMP cleaning module. Although there have been many studies conducted on improving particle removal efficiency by brush cleaning, these studies do not consider the effects of brush contamination. Depending on the process condition and brush condition, brush cross contamination effects significantly influence post-CMP cleaning defects. This study investigates brush cross contamination effects in the CMP in-situ cleaning module by conducting experiments using 300mm tetraethyl orthosilicate (TEOS) blanket wafers. This study also explores brush pre-treatment in the CMP tool and proposes recipe effects, and critical process parameters for optimized CMP in-situ cleaning process through experimental results.

Research and Implementation on Critical Technology of Chemical Mechanical Polishing Tool for 300 mm Wafer

As the feature size scales down and the implementation of multilevel metallization, chemical mechanical polishing(CMP) has become one of the most important technologies in the ultra-large-scale integrated circuits manufacturing. However, the 300 mm wafer CMP tool is being increasingly monopolized by only a few foreign companies, and therefore the research level of 300 mm wafer CMP in our country is far behind other countries such as U.S., Japan, and South Korea. The critical technology of the 300 mm wafer CMP tool is studied. Firstly a 300 mm wafer multi-zone polishing head with pressure control system is developed, vacuum chuck and floating retainer ring are also available in the polishing head. And then the static and dynamic performance of the closed-loop pressure control system is tested. Finally a 300 mm wafer CMP tool is developed, and the 300 mm wafer CMP process flow is developed, improved, and optimized, which establishes the foundation for experimental research. The experimental results show that a material removal rate of 671.3 nm/min, and a within wafer non-uniformity of 3.93 % can be realized by the developed 300 mm wafer CMP tool.

Chemical mechanical polishing of thin film diamond

The demonstration that Nanocrystalline Diamond (NCD) can retain the superior Young’s modulus (1100GPa) of single crystal diamond twinned with its ability to be grown at low temperatures (<450°C) has driven a revival into the growth and applications of NCD thin films. However, owing to the competitive growth of crystals the resulting film has a roughness that evolves with film thickness, preventing NCD films from reaching their full potential in devices where a smooth film is required. To reduce this roughness, films have been polished using Chemical Mechanical Polishing (CMP). A Logitech Tribo CMP tool equipped with a polyurethane/polyester polishing cloth and an alkaline colloidal silica polishing fluid has been used to polish NCD films. The resulting films have been characterised with Atomic Force Microscopy, Scanning Electron Microscopy and X-ray Photoelectron Spectroscopy. Root mean square roughness values have been reduced from 18.3nm to 1.7nm over 25μm2, with roughness values as low as 0.42nm over ∼0.25μm2. A polishing mechanism of wet oxidation of the surface, attachment of silica particles and subsequent shearing away of carbon has also been proposed.

Low Cost and High Performance CMP Solution for Si Polishing in Backside Illumination (BSI) Application

Backside illumination (BSI) is an uprising technology to achieve high performance of CMOS (Complementary Metal-Oxide Semiconductor) imaging. Si CMP (Chemical-Mechanical Polishing) process is required in BSI application to remove grinding masks and dislocations from bonded wafer with typical 1.0~3.0um removal amount. BSI CMP appears easy compared to traditional IC CMP in that there is much less integration requirements from pre/post CMP steps. The challenges lie in CMP profile control to compensate incoming thickness variation from grinding for low TTV (total thickness variation), low surface roughness and supreme surface quality for optical path, and low cost for mass production. There is a need to develop slurries/process to conquer all the challenges. Reported in this paper is our recent effort to address such challenges in Si CMP process for BSI application by combining CMP slurry selection and process optimization together. The performances of these approaches were tested on laboratory-scale instruments and further optimized on 8” and 12” CMP tools. Polishing results from both blanket Si (EPI) wafers and SOI wafers are discussed to set up the final process conditions.

CMP Slurry and Process Development for TSV Front-Side Polishing

3D integration utilizing TSV (Through-Silicon Via) is a promising technology to achieve high performance 3DIC (three-dimentional integrated circuit), not only because it exponentially increases connection efficiency between dies, but also because it can be practically integrated into current IC manufacture processes with minimal impact on both FEOL and BEOL design and processing. During construction of TSV, CMP (Chemical-Mechanical Polishing) is required to reveal the vias and finish the wafer surface for future processing. Reported in this paper is our recent effort in developing a series of slurries for TSV front-side polishing by close collaboration in device design, slurry formulation and process fine-tuning. Specifically, high through-put and well performed Cu slurries, along with high SiO2/Si3N4 selectivity barrier slurries, are introduced. These slurries are tested on laboratory-scale instruments as well as foundry CMP tools. Polishing results from both blanket and pattern wafers are discussed.

Manufacturable 300mm Wafer Thinning for 3D Interconnect Applications

Abstract3D interconnect wafer-to-wafer or die-to-wafer integration requires a wafer thinning operation to expose copper (Cu)-filled through-silicon vias (TSVs) from the backside of the wafer. The wafer thinning flow uses edge trim, backgrind, backpolish, and chemical mechanical polishing (CMP). This paper presents an overview of the wafer grinding process. We have demonstrated the capability to edge-trim and backgrind 300 mm TSV and non-TSV wafers down to 30 microns (μm) while bonded to a handle wafer. TSV wafers were further processed on a CMP tool to remove the last few microns of Si, exposing the Cu-filled TSVs. Metrology techniques were used to inspect and measure the wafer edge trim and final thinned wafer thickness. The quality of the thinned wafer was characterized by atomic force microscopy (AFM) to observe surface roughness and by transmission electron microscopy (TEM) to quantify crystalline damage below the surface of the thinned wafer. Further characterization included measuring wafer thickness, total thickness variation (TTV), bow, and warp. Exposed TSVs were characterized by laser microscope to measure the height of Cu protrusions. These critical elements of a manufacturing-worthy 300 mm wafer thinning process for 3D are discussed.

CMP wastewater management using the concepts of design for environment

AbstractApplication of design for environment (DfE) concepts to management of wastewater from chemical mechanical polishing (CMP) processes are presented in this paper. Today, DfE is a prevailing concept and is widely adopted by advanced nations in lieu of the traditional “command and control” approach to control waste and toxic emissions. Designing environmentally‐benign processes and products is a new and challenging frontier for engineering professionals, including those in the semiconductor industry. An insatiable need for water and subsequent wastewater treatment has imposed a chilling effect on semiconductor industry growth. It was estimated that semiconductor producers consumed more than 5.523 × 108 m3 of water in 2000. Of this amount, CMP processes accounted for 40% of the total. The CMP tool market and CMP slurry market are estimated to have 36% and 29% annual growth rates, respectively between 2000 and 2005.Inevitably, a tremendous amount of waste slurry and post‐CMP rinse water will be generated and have to be managed properly. CMP wastewater is characterized by its high content of suspended solids having sub‐micron particle sizes, high turbidity, and high conductivity. Traditional wastewater treatment technologies, such as chemical coagulation/precipitation, do not work well for CMP wastewater, because it would generate a large volume of sludge, which might cause disposal problems in many countries, such as Taiwan. Therefore, utilizing pollution prevention principles in the design of CMP tools, development of new CMP slurries, and improved plant operations are necessary to minimize environmental damage.Reclamation of process water is also a common requirement in the semiconductor industry. To this end, several alternatives for source reduction of CMP wastewater and water reclamation are presented in this paper.

A model of abrasive-free removal of copper films using an aqueous hydrogen peroxide–glycine solution

Using a recently formulated cell model for mass transport with chemical reaction in chemical–mechanical polishing, predictions are made for the rates of chemical removal of copper from blanket films in a hydrogen peroxide solution containing glycine, and compared with experimental observations. The model requires input regarding the kinetics of the reaction, geometrical parameters, and the relative velocity between the wafer and the pad. Predictions of the removal rate as a function of the relative velocity between the wafer and the pad at three different glycine concentrations are found to be consistent with the trend displayed by experimentally measured results from a chemical–mechanical polishing tool.

The exothermic reaction and temperature measurement for tungsten CMP technology and its application on endpoint detection

A novel in-situ endpoint detection method used pad temperature measurement to control the polishing tungsten and barrier metal Ti/TiN is proposed. The metal chemical-mechanical polishing (CMP) process includes chemical reaction. It is an exothermic process as the polishing slurry reacts on tungsten and Ti/TiN films. Therefore, the pad temperature increases as tungsten and barrier metal films are polished, but will drop dramatically when metal layers are polished and touch the oxide layer. A non-contact thermal sensor system was installed on our CMP tool to measure the pad temperature. From the in-situ pad temperature curve, the endpoint can be detected clearly and the polishing process stops at the oxide layer. This method can also be used to study the reactions between the pad temperature curve and the effects of CMP process conditions such as down force, platen speed as well as polishing performance such as removal rate and uniformity.

Integration of chemical-mechanical polishing into CMOS integrated circuit manufacturing

Planarization by chemical-mechanical polishing (CMP) has been exploited by IBM in the development and manufacture of CMOS products since 1985. Among the products that use this technology are the 4-Mbit DRAM (which uses polysilicon, oxide, tungsten-line and tungsten-stud planarization) and its logic family (which uses four oxide and four tungsten-stud planarization steps). CMP is also used in the planarization of oxide shallow isolation trenches, as in the 16-Mbit DRAM. Reduced sensitivity to many types of defects is possible with CMP. A wafer that is truly flat is easier to clean, eliminates step coverage concerns, provides for better photolithographic and dry etch yields, and generally minimizes complications from prior level structures. Oxide CMP reduces sensitivity to certain pre-existing defects, such as crystalline inclusions or foreign material in an interlevel dielectric. Metal CMP can reduce the incidence of intralevel shorts relative to conventional RIE processing. Random defects associated with CMP, such as slurry residues and mechanical damage, are controlled by careful optimization of the post-polish clean and of the polish process itself. Systematic defects, such as incomplete planarization over very large structures, are controlled by process optimization and prudent design limitations. These include such things as constraints on the image size, the distance between images, and/or the local pattern density. Since its introduction in the 4-Mbit DRAM, there has been a steady increase in the use of chemical-mechanical polishing in IBM CMOS products. The number of steps, processes and materials polished continue to rise, both in current and planned future products. Individual applications range from the simple removal of back-side films to complex insulator or metal planarization requiring high removal uniformity. The process tolerances delivered by CMP have decreased faster than image size, even in the face of dramatic increases in circuit and layout complexity. CMP tools are installed in IBM semiconductor manufacturing and development sites worldwide. Chemical-mechanical polish processes and applications provide unique leverage to IBM products, and are a crucial part of both current and planned IBM CMOS technologies.