Transistor Characteristics Research Articles

71‐2: Distinguished Paper: 4,670‐PPI OLEDoS Pixel Circuit Design for Wide Data Voltage Range in a 5V 0.13μm CMOS Process

OLEDoS displays hold great promise for AR/VR applications, but the ultra‐high pixel density required for microdisplays, exceeding several thousand PPI, presents significant challenges for pixel circuit design. Above all, the maximum OLED current of each OLEDoS sub‐pixel is extremely low, on the order of several nanoamperes or less, resulting in a data voltage range narrower than a few hundred millivolts. Consequently, for example, when expressing 10‐bit grayscale, designing data driver circuits to divide the data voltage range into 1,024 levels becomes exceedingly challenging. Furthermore, circuit techniques that compensate for variations in transistor characteristics are nearly inapplicable due to the ultra‐small pixel area. This paper proposes a pixel circuit design method to expand the data voltage range for a 4,670‐PPI OLEDoS display while considering luminance uniformity. The effectiveness of the proposed pixel circuit was verified through measurements on 40×120 pixel arrays fabricated in a 5V 0.13μm CMOS process.

Effects of iodine doping on structural and electrical characteristics of solution-processed indium oxide thin-film transistors and its potential application for iodine sensing

Effects of iodine doping on structural and electrical characteristics of solution-processed indium oxide thin-film transistors and its potential application for iodine sensing

Fabrication of lateral diamond MOSFET with buried pn-junctions by diamond surface planarization based on carbon solid solution into nickel

New fabrication processes for buried p+-type diamond using etching techniques based on the solid-solution reaction of carbon with nickel were proposed and demonstrated. Specifically, an inversion-channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with source and drain regions buried in the body were fabricated, and their operation were confirmed. An etching process using etching techniques based on the solid-solution reaction of carbon with nickel was applied to realize trench formation and planarization after the growth of a p+-type diamond. The fabricated MOSFET exhibited drain current density equivalent to that of conventional MOSFET with source and drain p+-type regions deposited as islands on an n-type body, and ideal field-effect transistor characteristics with linear and saturation regions, and the drain current density was controlled by the gate voltage. However, the surface protrusion structure owing to the incomplete planarization process limited the device characteristics. The proposed fabrication processes for buried layers are expected to function as an important selective doping technique for diamond electronic devices such as ion implantation.

Analysis on charge-retention characteristics of sub-threshold synaptic IGZO thin-film transistors with defective gate oxides

We provide a quantitative analysis on the charge-retention characteristics of sub-threshold operating In–Ga–Zn–O (IGZO) thin-film transistors (TFTs) with a defective gate-oxide for low-power synaptic applications. Here, a defective SiO2 is incorporated as the synaptic gate-oxide in the fabricated IGZO TFTs, where a defect is physically playing the role as an electron trap. With this synaptic TFT, positive programming pulses for the electron trapping are applied to the gate electrode, followed by monitoring the retention characteristics as a function of time. And this set of the programming and retention-monitoring experiments is repeated in several times for accumulating effects of pre-synaptic stimulations. Due to these accumulated stimulations, electrons are expected to be getting occupied within a deeper trap-state with a higher activation energy, which can lead to a longer retention. To verify these phenomena, a stretched exponential function and respective inverse Laplace transform are employed to precisely estimate a retention time and trap activation-energy for transient experimental results.

Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process.

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants.

Effect of supporting layer on electrical characteristics of field-effect transistor based on reduced graphene oxide film

The field-effect transistors (FETs) based on reduced graphene oxide (rGO) with SiO2, porous silicon (PS), and oxidized porous silicon (PSox) supporting layers were obtained. The influence of charged impurities in the silicon substrate and electrically active defects in the support layers on the electrical properties of the FETs was studied based on the capacitance-voltage characteristic analysis. Localized electron states in the SiO2, PS, and PSox supporting layers that affect the charge transfer in the rGO-based FETs were determined using thermally stimulated depolarization spectroscopy. The influence mechanisms of various supporting layers on the electrical characteristics of the obtained FETs are discussed.

Organic Synaptic Transistors with Environmentally Friendly Core/Shell Quantum Dots for Wavelength-Selective Memory and Neuromorphic Functions.

Organic transistors based on organic semiconductors together with quantum dots (QDs) are attracting more and more interest because both materials have excellent optoelectronic properties and solution processability. Electronics based on nontoxic QDs are highly desired considering the potential health risks but are limited by elevated surface defects, inadequate stability, and diminished luminescent efficiency. Herein, organic synaptic transistors based on environmentally friendly ZnSe/ZnS core/shell QDs with passivating surface defects are developed, exhibiting optically programmable and electrically erasable characteristics. The synaptic transistors feature linear multibit storage capability and wavelength-selective memory function with a retention time above 6000 s. Various neuromorphic applications, including memory enhancement, optical communication, and memory consolidation behaviors, are simulated. Utilizing an established neuromorphic model, accuracies of 92% and 91% are achieved in pattern recognition and complicated electrocardiogram signal processing, respectively. This research highlights the potential of environmentally friendly QDs in neuromorphic applications and health monitoring.

Low-temperature preparation and characteristics of top-gate thin-film transistors with La-ZTO active layers and polymethylmethacrylate dielectric layers

A top-gate coplanar-structure thin-film transistor (TFT) combining the advantages of both a co-sputtered amorphous La-doped ZnSnO (a-La-ZTO) active layer and solution-based polymethylmethacrylate (PMMA) gate dielectric layer has been prepared under low temperature (100 °C) with low cost for the first time. The results indicate that the PMMA thin film demonstrates anti-reflection properties when it combines with a-La-ZTO layer to form a double-layer film, displaying high transparency to visible light of ∼90.3%. Moreover, it was found that the La target power during the deposition of a-La-ZTO film plays an important role in suppressing the formation of oxygen vacancies and adjusting the carrier concentration of a-La-ZTO active layer, thus impacting a-La-ZTO TFT performance. Overall, the optimum a-La-ZTO TFT with a La target power of 13.9 W, working in an n-channel enhancement mode, possesses a large saturated mobility (>10 cm2 (Vs)−1) and an on/off drain current ratio over 105.

4670‐PPI OLEDoS pixel circuit design for wide data voltage range in a 5 V 0.13 μm CMOS process

AbstractOLEDoS displays hold great promise for AR/VR applications, but the ultra‐high pixel density required for microdisplays, exceeding several thousand PPI, presents significant challenges for pixel circuit design. Above all, the maximum OLED current of each OLEDoS sub‐pixel is extremely low, on the order of several nanoamperes or less, resulting in a data voltage range narrower than a few hundred millivolts. Consequently, for example, when expressing 10‐bit grayscale, designing data driver circuits to divide the data voltage range into 1024 levels becomes exceedingly challenging. Furthermore, circuit techniques that compensate for variations in transistor characteristics are nearly inapplicable due to the ultra‐small pixel area. This paper proposes a pixel circuit design method to expand the data voltage range for a 4670‐PPI OLEDoS display while considering current uniformity. The effectiveness of the proposed pixel circuit was verified through measurements on 40 × 120 pixel arrays fabricated in a 5 V 0.13 μm CMOS process.

Design of novel low cost triple-node-upset self-recoverable hardened latch

CMOS devices are increasingly affected by triple-node-upset as transistor characteristics reduce, particularly in radiation environments. For the shortcomings of the existing radiation hardened designs, including high overhead and high delay, this paper proposes a novel low cost triple-node-upset self-recoverable latch. Simulation results show that compared with the existing triple-node-upset hardened designs, the proposed latch has reduced power consumption, delay, and power-delay product by 34.57 %, 6.42 %, and 34.98 %, respectively.

Investigation of cryogenic current–voltage anomalies in SiGe HBTs: Role of base–emitter junction inhomogeneities

The deviations of cryogenic collector current–voltage characteristics of SiGe heterojunction bipolar transistors (HBTs) from ideal drift-diffusion theory have been a topic of investigation for many years. Recent work indicates that direct tunneling across the base contributes to the non-ideal current in highly scaled devices. However, cryogenic discrepancies have been observed even in older-generation devices for which direct tunneling is negligible, suggesting that another mechanism may also contribute. Although similar non-ideal current–voltage characteristics have been observed in Schottky junctions and were attributed to a spatially inhomogeneous junction potential, this explanation has not been considered for SiGe HBTs. Here, we experimentally investigate this hypothesis by characterizing the collector current ideality factor and built-in potential of a SiGe HBT vs temperature using a cryogenic probe station. The temperature dependence of the ideality factor and the relation between the built-in potential as measured by capacitance–voltage and current–voltage characteristics are in good qualitative agreement with the predictions of a theory of electrical transport across a spatially inhomogeneous junction. These observations suggest that inhomogeneities in the base–emitter junction potential may contribute to the cryogenic non-idealities. This work helps to identify the physical mechanisms limiting the cryogenic microwave noise performance of SiGe HBTs.

Dual Interactive Mode Human-Machine Interfaces Based on Triboelectric Nanogenerator and IGZO/In2O3 Heterojunction Synaptic Transistor.

Imitating human neural networks via bio-inspired electronics advances human-machine interfaces (HMI), overcoming von Neumann limitations and enabling efficient, low-energy data processing in the big data era. However, single-contact mode HMIs have inherent limitations in terms of their capabilities and performances, such as constrained adaptability to dynamic environments, and reduced cognitive processing capabilities. Here, a dual-interactive-mode HMI system based on a triboelectric nanogenerator (TENG) and heterojunction synaptic transistor (HJST) is proposed for both contact and non-contact applications. The TENG incorporates a poly-methyl meth-acrylate (PMMA)-NiCo2S4/S film, in which the NiCo2S4/S composite traps and blocks electrons to optimize charge generation and storage. The heterojunction structure, mitigates the Debye screening effect, thereby improving transistor characteristics and reliability. The integrated TENG-HJST system exhibits synaptic functions, including excitatory/inhibitory postsynaptic current (EPSC/IPSC), paired-pulse facilitation/depression (PPF/PPD), and synaptic plasticity, enabling emulation of neural behavior and advanced information processing. Moreover, neural morphology manipulation is demonstrated in practical tasks, such as controlling international chess games. By integrating the TENG-HJST device with a robotic hand, conscious artificial responses are generated, enhancing event accuracy. This breakthrough in dual-interactive-mode interfacing holds promise for HMI systems and neural prostheses.

Enhancement of electrical characteristics of SnGaO thin-film transistors via argon and oxygen plasma treatment

The impact of Ar or O2 plasma treatment on the electrical characteristics of SnGaO thin film transistors (TFTs) fabricated via solution method was examined. The findings of the study revealed that Ar plasma treatment for an optimal duration enhances the electrical properties of SnGaO TFTs, including the improvement of mobility, subthreshold swing (S·S.), and on-off ratio. This result is considered to be due to the increased concentration of oxygen vacancy as donor in the channel layer. Oxygen plasma treatment has an opposite effect on the change in oxygen vacancy concentration, thereby reducing the off-state current and facilitating the adjustment of threshold voltage. However, excessive Ar or O2 plasma treatment duration led to an increase in deep defect states and a significant “hump" phenomenon in the output characteristic curve.

Tuning Gate Potential Profiles and Current-Voltage Characteristics of Polymer Electrolyte-Gated Transistors by Capacitance Engineering.

We demonstrate that the transfer characteristics of electrolyte-gated transistors (EGTs) with polythiophene semiconductor channels are a strong function of gate/electrolyte interfacial contact area, i.e., gate size. Polythiophene EGTs with gate/electrolyte areas much larger than the channel/electrolyte areas show a clear peak in the drain current vs gate voltage (ID-VG) behavior, as well as peak voltage hysteresis between the forward and reverse VG sweeps. Polythiophene EGTs with small gate/electrolyte areas, on the other hand, exhibit current plateaus in the ID-VG behavior and a gate-size-dependent hysteresis loop between turn on and off. The qualitatively different transport behaviors are attributed to the relative sizes of the gate/electrolyte and channel/electrolyte interface capacitances, which are proportional to interfacial area. These interfacial capacitances are in series with each other such that the total capacitance of the full gate/electrolyte/channel stack is dominated by the interface with the smallest capacitance or area. For EGTs with large gates, most of the applied VG is dropped at the channel/electrolyte interface, leading to very high charge accumulations, up to ∼0.3 holes per ring (hpr) in the case of polythiophene semiconductors. The large charge density results in sub-band-filling and a marked decrease in hole mobility, giving rise to the peak in ID-VG. For EGTs with small gates, hole accumulation saturates near 0.15 hpr, band-filling does not occur, and hole mobility is maintained at a fixed value, which leads to the ID plateau. Potential drops at the interfaces are confirmed by in situ potential measurements inside a gate/electrolyte/polymer semiconductor stack. Hole accumulations are measured with gate current-gate voltage (IG-VG) measurements acquired simultaneously with the ID-VG characteristics. Overall, our measurements demonstrate that remarkably different ID behavior can be obtained for polythiophene EGTs by controlling the magnitude of the gate-electrolyte interfacial capacitance.

One-Dimensional MoS2 Nanoscrolls as Miniaturized Memories.

Dimensionality of materials is closely related to their physical properties. For two-dimensional (2D) semiconductors such as monolayer molybdenum disulfide (MoS2), converting them from 2D nanosheets to one-dimensional (1D) nanoscrolls could contribute to remarkable electronic and optoelectronic properties, yet the rolling-up process still lacks sufficient controllability, which limits the development of their device applications. Herein we report a modified solvent evaporation-induced rolling process that halts at intermediate states and achieve MoS2 nanoscrolls with high yield and decent axial uniformity. The accordingly fabricated nanoscroll memories exhibit an on/off ratio of ∼104 and a retention time exceeding 103 s and can realize multilevel storage with pulsed gate voltages. Such open-end, high-curvature, and hollow 1D nanostructures provide new possibilities to manipulate the hysteresis windows and, consequently, the charge storage characteristics of nanoscale field-effect transistors, thereby holding great promise for the development of miniaturized memories.

Performance limits exploration of sub-5 nm monolayer germanane transistors: A first-principle quantum transport simulation

Two-dimensional germanium is considered a promising new channel material to replace silicon owing to its lower effective mass and larger electron–hole mobility. To investigate the transport characteristics of single-layer germanane transistors with gate lengths (Lg) below 5 nm, we utilize an ab initio quantum transport methodology. It was found that the n-type germanane transistors having Lg of 3 and 5 nm satisfy the International Technology Roadmap for Semiconductors (ITRS) requirements for the on-state current (Ion), effective delay time, and power-delay products of high-performance (HP) devices. Notably, by introducing a negative capacitive (NC) dielectric layer, the p-type germanane transistor having an Lg of 5 nm is almost able to meet the ITRS demands for HP devices. Despite reducing the gate length to 2 nm through the incorporation of the NC dielectric layer, the on-state currents for both n-type and p-type still satisfy approximately 80% of the ITRS standard. Therefore, monolayer germanane presents promising potential as a channel material in a sub-5 nm scale for HP applications.

Compact modeling of hysteresis in organic thin-film transistors

In this work, we propose a model that describes the temporal evolution of the threshold voltage and trapped charge density in Thin-Film Transistors (TFTs) under dynamic conditions, paving the way for the characterization and modeling of memory transistors. The model is expressed as a first-order differential equation for the trapped charge density, which is controlled by a time constant and an independent term proportional to the drain current. The time-dependent threshold voltage is introduced in a previously developed compact model for TFTs with special consideration to the contact effects. The combination of both models and the use of an evolutionary parameter extraction procedure allow for reproducing the experimental dynamic behavior of TFTs. The results of the model and the evolutionary procedure have been validated with published experimental data of pentacene-based transistors. The procedure is able to simultaneously reproduce three kinds of experiments with different initialization routines and constraints in each of them: output and transfer characteristics with hysteresis and current transients characteristics.

Analytical Modelling and Performance Characterization of Single Electron Transistor

One important component of the present nanotechnology research field is single electron transistor (SET) which has unrealized quality to operate at breakneck speeds with ultralow power consumption. The single electron transistor is a novel nanoscale switching device that can regulate the motion of a single electron in addition to maintaining its scalability down to the atomic level. In this context, scalability refers to the ability of electronic device to function better as their dimensions get smaller. The basic device properties that this single electron transistor (SET) operates on "quantized current-voltage (I-V) characteristic," "single electron tunneling effect," and "Coulomb blockade," are also covered. This study presents some of the key SET-related topics, such as modelling and simulation methods. Simulation of Nanostructures Method (SIMON) is circuit simulator for tunneling device with just a single electron device based on Monte Carlo approach. It enables simulation of any kind of circuits with voltage source, junctions in tunnels and capacitors in quasi stationary mode and transient mode. The most significant feature of SET that is applied in the research work is Coulomb blockade oscillation, so at the conclusion of this paper, a number of simulations utilizing the SIMON simulator are shown. The simulation results show that for gate capacitance CG = 2af, C∑ = 3af, IBIAS = 2nA, tunnel barrier resistance RT > 4.1KΩ and operating temperature T=21K the model reflects real SET characteristic with maximum voltage gain.

Non-volatile memory characteristics of flexible ferroelectric field-effect transistors consisting of Sm-doped BiFeO3 thin films

This study investigates the impact of Sm doping on the structural, electrical, and functional properties of BiFeO3 (BFO) thin films. The aim is to improve their non-volatile memory characteristics for use in flexible ferroelectric field-effect transistors (FeFETs). We fabricated Sm-doped BFO (SBFO) thin films on flexible mica substrates with Sm concentrations ranging from 0 to 15 %. The FeFET device structures, which include MoS2 monolayer channels and SBFO thin films with Pt bottom electrodes, were analyzed. The SBFO thin films displayed a (111) preferential orientation due to the influence of underlying Pt electrodes. Notably, the SBFO thin film doped with a 10 % Sm concentration showed optimal enhancements, including a reduction in leakage current density and an increase in remanent polarization to 55.8 μC/cm2, compared to undoped thin film (35.5 μC/cm2). Furthermore, the thin film exhibited superior fatigue resistance for up to 1012 switching cycles and maintained stable values under significant bending stress for ferroelectric polarizations. On the other hand, SBFO thin film with 15 % Sm doping displayed relaxor antiferroelectric behavior, highlighting the importance of doping concentration. Therefore, for non-volatile memory application reliability, the FeFET device featuring a 10 % Sm-doped SBFO thin film not only enhanced the memory window but also showed superior fatigue characteristics over 1012 switching cycles, compared to its undoped counterpart. These findings demonstrate the effect of Sm doping in customizing the properties of BFO thin films for advanced, flexible non-volatile memory devices, offering a novel insight to optimize ferroelectric field-effect transistor performance.

Impact of Dual-Gate Configuration on the Endurance of Ferroelectric Thin-Film Transistors With Nanosheet Polycrystalline-Silicon Channel Film

This work explores the characteristics of ferroelectric thin-film transistors (FeTFTs) utilizing an asymmetric dual-gate (DG) structure in both single-gate (SG) and DG operation modes. In the transfer characteristics, DG mode exhibits a memory window (MW) of 1.075 V, smaller than SG mode’s MW of 1.402 V, attributed to the back-gate bias effect causing a reduction in the device’s threshold voltage. However, DG mode demonstrates superior endurance characteristics with 106 cycles compared to SG mode’s 105 cycles. Additionally, the increase in erase pulse voltage (VERS) exacerbates the polycrystalline-silicon channel lattice damage of FeTFT, resulting in subthreshold swing (SS) degradation. Nevertheless, the extent of SS degradation from DG mode operation is significantly lower than that of SG mode, contributing to the superior endurance of DG mode. The elevation of program pulse voltage (VPRG) induces imprint and charge-trapping effects in the top-gate ferroelectric dielectric, leading to reduced endurance. Due to the use of SiO2 as the back-gate dielectric in FeTFT, DG mode exhibits lower impacts of charge-trapping effects from the top-gate ferroelectric dielectric layer, resulting in better endurance compared to SG mode. The asymmetric DG structure provides greater tolerance in the selection of VPRG and VERS.