Characteristics Of N-channel MOSFETs Research Articles

Bias and 1/f Noise Degradation Modeling of 90 nm n-Channel MOSFETs Induced by Hot Carrier Stress

The goal of this research is to model the drain current and 1/f noise degradation characteristics of n-channel MOSFETs. In this paper, we present the implementation of hot carrier degradation into drain current equations of BSIM4 model. We show simulation results of the DC drain current degradation, and then 1/f noise voltage density simulation results affected by the drain current degradation. We have extracted BSIM4 model parameters extensively with the measured data including I-V and 1/f noise measurement of our TEGs. Especially for 1/f noise degradation characterizations, the input referred noise has been calculated after extracting the 1/f noise parameter degradations.

Improved Body Effect and Analog Characteristics of n-Channel MOSFET With Lateral Asymmetric Substrate Doping

An n-channel MOSFET with lateral asymmetric substrate doping (LASD) is presented in this paper. The proposed LASD device has a p-well on the source side and a p-substrate on the drain side. The LASD MOSFET was designed by the simple p-well layout approach and fabricated using the 0.18 \(\mu \) m standard low-voltage CMOS process without any process modification. The experimental measurements showed the improved analog performances of the LASD MOSFET: higher transconductance (g \(_{\mathbf {m}}\) ), lower drain conductance (g \(_{{\mathrm {ds}}}\) ), lower drain induced barrier lowering, higher transconductance generation factor (g \(_{{\mathrm {m}}}/{\mathrm I}_{{\mathrm {D}}}\) ), and higher Early voltage (V \(_{{\mathrm {EA}}}\) ). In addition, the LASD device showed strong body-effect immunity: smaller V \(_{{\mathrm {T}}}\) shift according to body bias and lower body bias sensitivity factor (g \(_{{\mathrm {mb}}}/{\mathrm g}_{{\mathrm {m}}}\) ).

Characteristics of n-Channel MOSFETs With Tailored Source/Drain Extension for Mask ROM and EEPROM Applications

A novel 2-bits-per-transistor mask-programmable read-only memory (mask ROM) device with gate-to-drain nonoverlapped implantation (NOI) is investigated in this paper. The NOI mask ROM can be coded by using the lightly doped drain implantation mask and related processes. This simple coding scheme is fully compatible with industrial CMOS processing. The measured threshold voltage difference DeltaVth between the two logic states (ldquo0rdquo and ldquo1rdquo) of the devices is approximately 0.6 V. Moreover, DeltaVth can be improved when the pocket implant is incorporated into the NOI region based on the device simulation. The characteristics of this NOI mask ROM, including 2-bits-per-transistor operation, body effects, hot carrier impact, and array layouts, are investigated. By sharing the same array layout and readout circuit, the potential of NOI devices' seamless migration between the mask ROM and electrically erasable programmable read-only memory functions are also demonstrated.

Effects of Fabrication Process on the Electrical Characteristics of n-Channel MOSFETs Irradiated with Gamma-Rays

The effect of the fabrication process of n-channel 6H-SiC MOSFETs on their radiation resistance is investigated. MOSFETs that post implantation annealing for source and drain was carried out with carbon coating on the sample surface are compared to MOSFETs that post implantation annealing was carried out without carbon coating. The radiation resistance (gamma-rays) of the carbon-coated MOSFETs is higher than that of non-coated ones. The channel mobility for MOSFETs whose gate oxide was formed using pyrogenic or dry oxidation process dose not change by gamma-ray irradiation below 1x105 Gy. The value of channel mobility slightly increases with increasing dose above 1x105 Gy. No significant increase in irradiation induced interface traps is observed.

Enhanced off-state leakage currents in n-channel MOSFETs with N2O-grown gate dielectric

This paper reports on the off-state drain (GIDL) and gate current (Ig) characteristics of n-channel MOSFETs using thin thermal oxide (OX), N/sub 2/O-nitrided oxide (N2ON), and N/sub 2/O-grown oxide (N20G) as gate dielectrics. Important phenomena observed in N20G devices are enhanced GIDL and Ig in the low-field region as compared to the OX and N20N devices. They are attributed to heavy-nitridation-induced junction leakage and shallow-electron-trap-assisted tunneling mechanisms, respectively. Therefore, N2ON oxide is superior to N20G oxide in leakage-sensitive applications. >

Off-state gate current in n-channel MOSFETs with nitrided oxide gate dielectrics

The authors report on the off-state gate current (I/sub g/) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150 degrees C for 10-300 s. New phenomena observed in NO devices are a significant I/sub g/ at drain voltages as low as 4 V and an I/sub g/ injection efficiency reaching 0.8, as compared to 8.5 V and 10/sup -7/ in SiO/sub 2/ devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I/sub g/ in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure. >

A new isolation method with boron-implanted sidewalls for controlling narrow-width effect

A new isolation method for high packing density MOS devices has been developed. In this method the LOCOS technique is applied to wide isolation regions and the buried-oxide technique is applied to isolation regions less than 2 µm wide. No additional masks are needed in order to form SiO 2 film in the wide field regions because the photoresist is thicker near steps and inside the narrow trenches. For reducing the hump that appears in subthreshold current characteristics of n-channel MOSFET's, Using buried-oxide isolation, tilt-angle implantation to each of the four sidewalls is performed as a channel stop. The Sidewall channel stop can also control the narrow-channel effect.

Submicron channel MOSFET's logic under punchthrough

The characteristics of n-channel MOSFETs that make use of the punchthrough current are considered in this paper. The current conduction mechanisms of the short channel MOSFET under the bias condition of punchthrough have been studied through the use of two-dimensional computer simulation. Experimental devices with channel lengths as short as 0.5 /spl mu/m were fabricated on a lightly doped substrate. Current-voltage curves of these devices showed pentode-like characteristics for smaller drain biases and triode-like characteristics for larger drain biases. A switching delay as small as 75 ps was obtained for a 13-stage ring oscillator composed of the submicron channel devices.