Channel Layer Research Articles

Enhancement of electrical characteristics of SnGaO thin-film transistors via argon and oxygen plasma treatment

The impact of Ar or O2 plasma treatment on the electrical characteristics of SnGaO thin film transistors (TFTs) fabricated via solution method was examined. The findings of the study revealed that Ar plasma treatment for an optimal duration enhances the electrical properties of SnGaO TFTs, including the improvement of mobility, subthreshold swing (S·S.), and on-off ratio. This result is considered to be due to the increased concentration of oxygen vacancy as donor in the channel layer. Oxygen plasma treatment has an opposite effect on the change in oxygen vacancy concentration, thereby reducing the off-state current and facilitating the adjustment of threshold voltage. However, excessive Ar or O2 plasma treatment duration led to an increase in deep defect states and a significant “hump" phenomenon in the output characteristic curve.

Use of 3D printing to integrate microchip electrophoresis with amperometric detection.

This paper describes the use of PolyJet 3D printing to fabricate microchip electrophoresis devices with integrated microwire electrodes for amperometric detection. The fabrication process involves 3D printing of two separate pieces, a channel layer and an electrode layer. The channel layer is created by 3D printing on a pre-fabricated mold with a T-intersection. For the electrode layer, a stencil design is printed directly on the printing tray and covered with a piece of transparent glass. Microwire electrodes are adhered over the glass piece (guided by underlaying stencil) and a CAD design of the electrode layer is then printed on top of the microwire electrode. After delamination from the glass after printing, the microwire is embedded in the printed piece, with the stencil design ensuring that alignment and positioning of the electrode is reproducible for each print. After a thermal bonding step between the channel layer and electrode layer, a complete electrophoresis device with integrated microelectrodes for amperometric detection results. It is shown that this approach enables different microwire electrodes (gold or platinum) and sizes (100 or 50µm) to be integrated in an end-channel configuration with no gap between the electrode and the separation channel. These devices were used to separate a mixture of catecholamines and the effect of separation voltage on the potential voltage applied on the working electrode was also investigated. In addition, the effect of electrode size on the number of theoretical plates and limit of detection was studied. Finally, a device that contains different channel heights and a detection electrode was 3D-printed to integrate continuous flow sampling with microchip electrophoresis and amperometric detection.

Mechanism of electrical performance deterioration in a-Si:H TFTs caused by source/drain Decap treatment

During the fabrication process of the display industry, the Decap treatment is usually employed as a means to reuse semiconductor materials of thin film transistors (TFTs), but the influence and mechanism of Decap process on the properties of the decapped samples is unknown. To elucidate this occurrence, the electrical characteristics of the channel layer, as well as the microstructure and components at the interface between the Source/Drain (S/D) and the channel layer were examined. It reveals that the infiltration of impurity ion (O and Mo) has significant impact on the deterioration of device performance for a-Si:H TFTs with a Mo/Al/Mo stacked S/D electrode structure. More specifically, oxygen's intrusion leads to the formation of SiOX and the alterations of the surface energy levels and charge distribution of Si, thus introduces an interface trap states between channel layer and S/D electrodes to scatter and capture of interface carriers. And Mo's intrusion may induce the come into being of MoSi or MoP chemical states, causing the decrease of the doping efficiency of phosphorus and the reduction of carrier concentration (from 5.52 × 1016 cm−3 to 4.44 × 1016 cm−3) of a-Si:H channel layer. The combined effect of these two factors results in the decline of electrical performance of S/D decapped a-Si:H TFTs.

Non-equilibrium thermal transport study in steady state GaN MISHEMT channel layer based on electron Monte Carlo and phonon BTE

An electro-thermal coupling simulator for GaN devices based on electron Monte Carlo (e-MC) simulations is established. Taking GaN Metal Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) as example, the non-equilibrium thermal transport processes of self-heating effect in the channel layer are studied. This simulator is mainly coupled by e-MC and the phonon Boltzmann transport equation (pBTE), physical property parameters and electric field parameters are provided by first-principles and Technology Computer Aided Design (TCAD), respectively. We first verify the e-MC program by calculating the electron transport properties of GaN materials, verify the feasibility of the established GaN MISHEMT model by using TCAD and obtained its operating characteristics. Further, the simulator is used to evaluate the non-equilibrium processes inside the channel layer in detail, the results show that there is significant consistency in the peak positions of electric field strength, heat generation and diffusion temperature, the diffusion temperature peak occurs at the secondary peak of heat generation. The frequency distribution of phonon emission under different drain-source bias voltages is revealed by phonon emission spectrum analysis. The strength of the non-equilibrium effect is measured by effective temperature. Increasing the drain-source bias voltage will significantly increase the peak temperature of hotspot and further enhance the non-equilibrium effect. Our study reports an efficient scheme for electro-thermal simulations of GaN MISHEMT, which provides insights for thermal management of GaN-based transistor devices.

83 Automated PDMS Engraving and Assembly of a Prototype Microfluidic Artificial Lung

OBJECTIVES/GOALS: We report an automated manufacturing system, and a series of cylindrical multi-layer microfluidic artificial lungs manufactured with the system and tested for fluidic fidelity and function. METHODS/STUDY POPULATION: A Roll-to-Roll (R2R) system to engrave multiple-layer devices was assembled. A 100 um-thick silicone sheet passes through an embedded CO2 laser engraver, which creates patterns of any geometry on the surface. The sheet is plasma-activated to create an irreversible bond, and rerolled into a processed device. Unlike typical applications of R2R, this process is synchronized to achieve consistent radial positioning. This allows the fluidics in the device to be accessed without being unwrapped. The result is a cylindrical core surrounded by many layers of microfluidic channels that can be accessed through the side of the device or through fluidic vias. This core is cut to expose the microfluidic layers, and then installed into a housing which routes the fluids into their respective microfluidic flow paths. RESULTS/ANTICIPATED RESULTS: To demonstrate the capabilities of the R2R manufacturing system, this method was used to manufacture multi-layer microfluidic artificial lungs (µALs). Gas and blood flow channels are engraved in alternating layers and routed orthogonally. The close proximity of gas and blood separated by gas-permeable PDMS permits CO2 and O2 exchange. Three µALs were successfully manufactured. Their flow paths were visualized using dyed water and checked for leaks. Then they were evaluated using water for pressure drop and CO2 gas-exchange. The top performing device had 15 alternating blood and gas layers. Test with whole blood demonstrated oxygenation from venous (70%) saturation levels to arterial (95%) saturation levels at a flow rate of 3 ml/min. DISCUSSION/SIGNIFICANCE: The ability to cost-effectively produce high surface area microfluidic devices would bring many small-scale technologies from the realm of research to clinical and commercial applications. In particular, most microfluidic artificial lungs only have small rated flows due to a lack of manufacturing processes able to create high surface area devices.

17‐2: Characterization of A‐In‐Ga‐Zn‐O Field Effect Transistors with ALD‐Grown IGZO Channel Layer

17‐2: Characterization of A‐In‐Ga‐Zn‐O Field Effect Transistors with ALD‐Grown IGZO Channel Layer

Mathematical Modelling and Simulations of Active Direct Methanol Fuel Cell

A one dimensional isothermal model is proposed by modelling the kinetics of methanol transport at anode flow channel (AFC), membrane and cathode catalyst layer of direct methanol fuel cell (DMFC). Analytical model is proposed to predict methanol cross-over rate through the electrolyte membrane and cell performance. The model presented in this paper considered methanol diffusion and electrochemical oxidation at the anode and cathode channels. The analytical solution of the proposed model was simulated in a MATLAB environment to obtain the polarization curve and leakage current. The effect of methanol concentration on cell voltage and leakage current is studied. The methanol cross-over has the significant impact on cell performance. The presented model predicts higher leakage current with the increase of methanol feed concentration. The cell performance was predicted at 70°C and various methanol feed concentration. The proposed model was validated with the experimental polarization curve of active DMFC.

Defects Contributing to Hysteresis in Few-Layer and Thin-Film MoS2 Memristive Devices.

Molybdenum disulfide, a two-dimensional material extensively explored for potential applications in non-von Neumann computing technologies, has garnered significant attention owing to the observed hysteresis phenomena in MoS2 FETs. The dominant sources of hysteresis reported include charge trapping at the channel-dielectric interface and the adsorption/desorption of molecules. However, in MoS2 FETs with different channel thicknesses, the specific nature and density of defects contributing to hysteresis remain an intriguing aspect requiring further investigation. This study delves into memristive devices with back-gate modulated channel layers based on CVD-deposited flake-based and thin-film-based MoS2 FETs, with a few-layer (FL) and thin-film (TF) channel thickness. Analysis of current-voltage (I-V) and conductance-frequency (Gp/ω-f) measurements led to the conclusion that the elevated hysteresis observed in TF MoS2 devices, as opposed to FL devices, stems from a substantial contribution from intrinsic defects within the channel volume, surpassing that of interface defects. This study underscores the significance of considering both intrinsic defects within the bulk and the interface defects of the channel when analyzing hysteresis in MoS2 FETs, particularly in TF FETs. The selection between FL and TF MoS2 devices depends on the requirements for memristive applications, considering factors such as hysteresis tolerance and scaling capabilities.

Oxygen Driven Defect Engineering of Monolayer MoS2 for Tunable Electronic, Optoelectronic, and Electrochemical Devices

AbstractMolybdenum disulfide (MoS2), a two‐dimensional (2D) semiconducting material harbors intrinsic defects that can be harnessed to achieve tuneable electronic, optoelectronic, and electrochemical devices. However, achieving precise control over defect formation within monolayer MoS2, remains a notable challenge. Here, an in‐situ defect engineering approach for monolayer MoS2 using a pressure‐dependent chemical vapor deposition (CVD) process is presented. Monolayer MoS2 grown in a low pressure CVD conditions (LP‐MoS2) produces sulfur vacancy (Vs) induced defect‐rich crystals primarily attributed to the oxygen‐deficient growth conditions. Conversely, atmospheric pressure CVD‐grown MoS2 (AP‐MoS2) passivates these defects with oxygen from ambient conditions. This disparity in defect profiles profoundly impacts crucial functional properties and device performance. AP‐MoS2 shows a drastically enhanced photoluminescence, which is significantly quenched in LP‐MoS2 attributed to in‐gap electron donor states induced by the Vs defects. However, the n‐doping induced in LP‐MoS2 generates enhanced photoresponsivity and detectivity in fabricated photodetectors compared to the AP‐MoS2‐based devices. Defect‐rich LP‐MoS2 outperforms AP‐MoS2 as channel layers of field‐effect transistors (FETs), as well as electrocatalytic material for hydrogen evolution reaction (HER). This work presents a single‐step CVD approach for in situ defect engineering in monolayer MoS2 and presents a pathway to control defects in other monolayer 2D materials.

Automatic diagnosis of depression based on attention mechanism and feature pyramid model.

Currently, most diagnoses of depression are evaluated by medical professionals, with the results of these evaluations influenced by the subjective judgment of physicians. Physiological studies have shown that depressed patients display facial movements, head posture, and gaze direction disorders. To accurately diagnose the degree of depression of patients, this paper proposes a comprehensive framework, Cross-Channel Attentional Depression Detection Network, which can automatically diagnose the degree of depression of patients by inputting information from the facial images of depressed patients. Specifically, the comprehensive framework is composed of three main modules: (1) Face key point detection and cropping for video images based on Multi-Task Convolutional Neural Network. (2) The improved Feature Pyramid Networks model can fuse shallow features and deep features in video images and reduce the loss of miniscule features. (3) A proposed Cross-Channel Attention Convolutional Neural Network can enhance the interaction between tensor channel layers. Compared to other methods for automatic depression identification, a superior method was obtained by conducting extensive experiments on the depression dataset AVEC 2014, where the Root Mean Square Error and the Mean Absolute Error were 8.65 and 6.66, respectively.

Study on Epitaxial Growth of High‐Quality InSb Materials

AbstractThis paper discusses the optimization of the growth temperature and Sb/In ratio of 1 µm InSb thin films grown on GaAs substrates by molecular beam epitaxy due to the InSb materials with larger lattice constants have smaller growth windows. The results show that atomic steps can be clearly seen in InSb thin films grown at 420 °C with a Sb/In ratio of 6. The InSb material grown under this condition has the smallest FWHM, indicating the best crystal quality. At the same time, the highest electron mobility measured at room temperature is 38860 cm2 V−1 s−1. The transport properties and crystal quality of InSb/AlxIn1‐xSb heterostructures corresponding to different Al compositions are also studied. The results show that as the Al component increases, dislocation scattering caused by lattice mismatch affects the electron mobility of the channel layer. The highest electron mobility of InSb/AlxIn1‐xSb heterostructures obtained is 18900 cm2 V−1 s−1 at room temperature.

High‐Performance Nd: AIZO/Al2O3 Dual Active Layer Design Without Thermal Annealing: High‐Speed Electron Transport and Defect Modification in Thin Film Transistors

Flexible wearable electronics have been developing rapidly in recent years, and one of its core devices, thin‐film transistor (TFT), is also attracting attention. Current TFT preparation processes usually require high annealing temperatures (>350 °C), which is not conducive to their application on most flexible substrates (PET, PEN, nanopaper, etc.). In this article, a strategy for the room temperature preparation of Nd:AIZO/Al2O3 dual‐layer TFT devices is proposed, which has appreciable electrical properties without additional annealing treatment. Taguchi orthogonal experimental methods are used to investigate the effects of three essential process parameters on the performance of the films and devices. As Nd:AIZO deposition time decreases and Al2O3 oxygen percentage and time during deposition increase, the μsat and SS of TFT devices are improved. With the preferred combination of parameters applied to the device preparation, the device exhibits a saturation mobility μsat of 24.3 cm2 V−1 s−1, a threshold voltage Vth of −1.4 V, a subthreshold swing SS of 0.21 V decade−1 and an Ion/Ioff ratio of 4.26 × 108. The ultra‐thin Al2O3 layer act as defect modification and form high‐speed electron transport in channel layer. The room temperature preparation of the dual‐layer TFT process proposed in this article is compatible with large‐size low‐cost flexible substrates. It has great potential for application in green flexible wearable electronics.

3D Stackable Vertical‐Sensing Electrochemical Random‐Access Memory Using Ion‐Permeable WS2 Electrode for High‐Density Neuromorphic Systems

AbstractIon‐based electrochemical random‐access memory (ECRAM) is proposed for synaptic applications owing to its promising characteristics that have the potential to accelerate data processing through neuromorphic systems. However, attaining ideal synaptic functionalities and constructing high‐density vertical synapse arrays are challenging due to issues related to uncontrolled ion migration and constraints in 3D multi‐stacking. Here, a breakthrough using 3D stackable Li ion‐based vertical‐sensing ECRAM (VS‐ECRAM) is presented with an ion‐permeable ultrathin WS2 electrode synthesized through low‐temperature (200 °C) atmospheric‐pressure plasma‐enhanced chemical vapor deposition (AP‐PECVD). The direct AP‐PECVD of the WOx channel layer induces WS2 formation in the surface region, which exhibits sufficient electrical conductivity to function as an electrode. By utilizing the WS2 electrode as an ion‐barrier layer in the VS‐ECRAM synapse, excellent weight update linearity and cycling variability are achieved due to the finely controlled ion migration. Furthermore, a two‐layer stacked 3D VS‐ECRAM is successfully fabricated through the vertical WS2 formation, and independent weight updates without any disturbance are confirmed. Finally, a high pattern recognition accuracy of 95.22% is obtained using a multi‐layer perceptron‐based neural network. Therefore, the proposed 3D stackable WS2‐based VS‐ECRAM exhibits a strong potential for application in high‐density neuromorphic devices with excellent synaptic performances.

Solution-Processed Metal Oxide Thin-Film Transistor at Low Temperature via A Combination Strategy of H2O2-Inducement Technique and Infrared Irradiation Annealing.

Solution processing has emerged as a promising technique for the fabrication of oxide thin-film transistors (TFTs), offering advantages such as low cost, high throughput, and exceptional compositional control. However, achieving reasonable electrical properties typically demands high annealing temperatures in the fabrication process. In addressing this challenge, a novel combination strategy is proposed that involves integrating the H2O2 inducement technique with infrared (IR) irradiation annealing. The study investigates the effects of precursors and IR irradiation annealing temperatures on the electrical properties of In2O3 TFTs. It is found that H2O2 can help accelerate the decomposition of organic residues, while IR irradiation annealing could enhance the film densification. By employing the proposed strategy, metal oxide TFTs consisting of a Zr-Al-O dielectric fabricated at 230°C and an In2O3 channel layer fabricated at 185°C demonstrated high performance with field-effect mobility = 31.7 cm2V-1·s-1, threshold voltage = 1.3 V, subthreshold swing = 0.13 V per decade, and on-to-off current ratio = 1.1 × 105. This work demonstrates the proposed combinational strategy is a general method to fabricate not only metal oxide semiconductorsbut also dielectrics.

Simulation of capacitorless DRAM based on polycrystalline silicon with a vertical underlap structure and a separated channel layer

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on polycrystalline silicon (poly-Si) with a vertical underlap structure and a separated channel layer was designed and analyzed. The memory performance was improved by the vertical underlap structure and the region separated into channel and storage layers. The vertical underlap structure suppressed the recombination rate by storing the holes in the isolated body and could be more easily fabricated than a conventional underlap structure. The thicknesses of the vertical underlap structure and storage region were optimized to enhance the memory performance. When the grain boundary (GB) is centrally located, the proposed 1T-DRAM demonstrates a retention time and sensing margin of 3.618 s and 29.93 μA μm−1, respectively. Even when the GB is in the worst position at T = 358 K, the memory still shows a retention time of 1.991 s and a sensing margin of 4.51 μA μm−1.

Protocols of data collection networks based on IEEE 802.15.4 radio channels in complexes for the protection of underground metal structures from electrochemical corrosion

Radio communication systems in telemetry and telemechanics systems of active electrochemical protection of underground metal structures are considered. The requirements for radio exchange systems for data collection networks from remote control and measuring points of cathodic protection stations are formulated. The analysis of the applicability of known exchange protocols based on the specifications of the IEEE 802.15.4 standard and its software add-ons for such networks is carried out and the need for the development of specialized network and channel layer protocols is justified. The results of the development of specialized network protocols of the application, network and channel levels that implement data exchange modes required for the collection networks under consideration while minimizing energy consumption are presented.

Highly oriented crystalline si on epitaxial Gd2O3/Si(111) substrate using low-cost Radio Frequency sputtering for Silicon on Insulator application

Silicon-on-Insulator (SOI) technology has been the center of attraction with the advancement in Radio Frequency (RF) technology and the advent of Internet-of-Things due to its low-power operation with reduced parasitic and short-channel effects. However, the state-of-the-art smart-cut method used for the SOI wafer is costly. Alternatively, the notion of using the Si channel layer on epitaxial rare-earth oxide has been proposed. In literature, the existing techniques used to achieve the same, such as Molecular beam Epitaxy or reduced-pressure chemical vapor deposition technique, are either costly or non-high-volume manufacturable. In this context, we propose a method to fabricate the highly oriented crystalline Si(111) channel layer (Top-Si) on an epitaxial Gd2O3/Si(111) virtual substrate (SOXI) utilizing the solid phase epitaxy using the high-volume manufacturing friendly (HVM), low-cost RF magnetron sputtering technique. First, we have shown the multicrystalline Si and epitaxial Gd2O3 layer grown on Si(111) substrate, as confirmed using high-resolution X-ray diffraction (HRXRD) and Transmission Electron Microscopy (TEM). Second, we investigated the impact of rapid thermal annealing at 850 °C on the heterostructure using HRXRD and TEM. It is observed that the high-temperature annealing transforms the Top-Si layer into the highly oriented crystalline Si(111) layer by fusing smaller grains towards larger grains. Hence, we demonstrate a low-cost, HVM-friendly technique for the fabrication of SOXI wafers.

Investigation on Contact Properties of 2D van der Waals Semimetallic 1T-TiS2/MoS2 Heterojunctions.

Two-dimensional transition metal dichalcogenides (2D TMDCs) are considered promising alternatives to Si as channel materials because of the possibility of retaining their superior electronic transport properties even at atomic body thicknesses. However, the realization of high-performance 2D TMDC field-effect transistors remains a challenge owing to Fermi-level pinning (FLP) caused by gap states and the inherent high Schottky barrier height (SBH) within the metal contact and channel layer. This study demonstrates that high-quality van der Waals (vdW) heterojunction-based contacts can be formed by depositing semimetallic TiS2 onto monolayer (ML) MoS2. After confirming the successful formation of a TiS2/ML MoS2 heterojunction, the contact properties of vdW semimetal TiS2 were thoroughly investigated. With clean interfaces of the TiS2/ML MoS2 heterojunctions, atomic-layer-deposited TiS2 can induce gap-state saturation and suppress FLP. Consequently, compared with conventional evaporated metal electrodes, the TiS2/ML MoS2 heterojunctions exhibit a lower SBH of 8.54 meV and better contact properties. This, in turn, substantially improves the overall performance of the device, including its on-current, subthreshold swing, and threshold voltage. Furthermore, we believe that our proposed strategy for vdW-based contact formation will contribute to the development of 2D materials used in next-generation electronics.

Ultraflexible, High-Performance Transistors and Logic Circuits on Biocompatible Polylactic Acid (PLA) Substrate.

Wearable and implantable devices have gained significant popularity, playing a crucial role in smart healthcare and human-machine interfaces, which necessitates the development of more complex electronic devices and circuits on biocompatible flexible materials. Polylactic acid (PLA) stands out due to its biodegradability, cost-effectiveness, and low immunogenicity. In this study, we utilize a solution-based spin-coating method to produce high-quality PLA thin films, serving as substrates for the fabrication of thin-film transistors (TFTs) in which the dielectric layer material is silicon dioxide, the channel layer material is IGZO, and the gate, drain, and source material is ITO at low temperatures (<40 °C) through a shadow masking technique. The resulting PLA-TFT devices exhibited remarkable flexibility, biocompatibility, and impressive electrical characteristics, including a charge carrier mobility of 27.81 cm2/(V s), a subthreshold swing of 162.8 mV/decade, and an ON/OFF current ratio of up to 1 × 106, and maintained performance under various deformations. We successfully constructed fundamental logic gate circuits using PLA-TFTs, including AND, OR, and NOT gates, which effectively performed logical functions and demonstrated stability under diverse bending conditions. These research findings provide valuable support for future endeavors in fabricating intricate logic circuits and realizing advanced functionalities on biocompatible flexible materials.

Neutronic Design Modification of Passive Compact-Molten Salt Reactor

Passive compact molten salt reactor (PCMSR) is a design concept of a molten salt reactor (MSR) currently under development in Universitas Gadjah Mada, Indonesia. It is designed as a thermal breeder reactor using thorium fuel cycle. However, our previous study shows that the original PCMSR design was incorrectly modelled, primarily overestimating its thorium breeding capability. To improve PCMSR neutronic design, we modified the core configuration by the addition of radial fuel channel layers previously nonexistent in original PCMSR core design in various configurations. Neutronic parameters of modified PCMSR geometries in the beginning of life (BOL) were simulated using MCNP6.2 radiation transport code with ENDF/B-VII.0 library. All variations of fuel layer addition show improvement in both temperature coefficient of reactivity (TCR) and breeding ratio (BR), with TCR values became more negative and BR values are larger than unity, ensuring proper breeding capability. Configuration Inner Core-Outer Blanket (IC-OB) achieves the largest BR and lowest doubling time (DT), whilst its TCR is an improvement from the original design. Therefore, IC-OB fuel layer configuration can be applied to redesign the original PCMSR and used in various design optimization scenarios.