Verification Challenges Research Articles

Reverse engineering and verification of gene networks: Principles, assumptions, and limitations of present methods and future perspectives

Reverse engineering of gene networks aims at revealing the structure of the gene regulation network in a biological system by reasoning backward directly from experimental data. Many methods have recently been proposed for reverse engineering of gene networks by using gene transcript expression data measured by microarray. Whereas the potentials of the methods have been well demonstrated, the assumptions and limitations behind them are often not clearly stated or not well understood. In this review, we first briefly explain the principles of the major methods, identify the assumptions behind them and pinpoint the limitations and possible pitfalls in applying them to real biological questions. With regard to applications, we then discuss challenges in the experimental verification of gene networks generated from reverse engineering methods. We further propose an optimal experimental design for allocating sampling schedule and possible strategies for reducing the limitations of some of the current reverse engineering methods. Finally, we examine the perspectives for the development of reverse engineering and urge the need to move from revealing network structure to the dynamics of biological systems.

Engineering of the LISA Pathfinder mission—making the experiment a practical reality

LISA Pathfinder represents a unique challenge in the development of scientific spacecraft—not only is the LISA Test Package (LTP) payload a complex integrated development, placing stringent requirements on its developers and the spacecraft, but the payload also acts as the core sensor and actuator for the spacecraft, making the tasks of control design, software development and system verification unusually difficult. The micro-propulsion system which provides the remaining actuation also presents substantial development and verification challenges. As the mission approaches the system critical design review, flight hardware is completing verification and the process of verification using software and hardware simulators and test benches is underway. Preparation for operations has started, but critical milestones for LTP and field effect electric propulsion (FEEP) lie ahead. This paper summarizes the status of the present development and outlines the key challenges that must be overcome on the way to launch.

Structured Types and Separation Logic

Structured types, such as C's arrays and structs, present additional challenges in pointer program verification. The conventional proof abstractions, multiple independent typed heaps and separation logic, which in previous work have been built on a low-level memory model for C and shown to be sound, are not directly applicable in verifications. This is due to the non-monotonic nature of pointer and lvalue validity in the presence of the unary &-operator. For example, type-safe updates through pointers to fields of a struct break the independence of updates across typed heaps or ∧∗-conjuncts. In this paper we present a generalisation of our earlier formal memory model that captured the low-level features of C's pointers and memory and formed the basis for an expressive implementation of separation logic, with new features providing explicit support for C's structured types. We implement this framework in the theorem prover Isabelle/HOL and all proofs are machine checked.

A challenge for atomicity verification

An unpublished algorithm of Haldar and Vidyasankar implements an atomic variable of an arbitrary type T for one writer and one reader by means of 4 unsafe variables of type T , three two-valued safe variables, and one three-valued regular variable. We present this algorithm, and prove its correctness by means of a refinement towards a known specification of an atomic variable. The refinement is a composition of refinement functions and a forward simulation. The correctness proof requires many nontrivial invariants. In its construction, we relied on the proof assistant PVS for the administration of invariants and proofs and the preservation of consistency.

Towards verifiable deeply embedded systems

An important class of deeply embedded systems (DES) involves interlocking cyber-physical control loops, each with its own dynamics and correctness constraints. For instance, in medical systems which monitor a patient's vital signs and control drug infusion rates, multiple sensing and control systems may be implicitly coupled. These systems present new challenges for control theory, scheduling and verification. What is needed are platforms capable of precise monitoring and enforcement of diverse execution constraints, and techniques to verify system correctness.

Verification of Mondex electronic purses with KIV: from transactions to a security protocol

Abstract The Mondex case study about the specification and refinement of an electronic purse as defined in the Oxford Technical Monograph PRG-126 has recently been proposed as a challenge for formal system-supported verification. In this paper we report on two results. First, on the successful verification of the full case study using the KIV specification and verification system. We demonstrate that even though the hand-made proofs were elaborated to an enormous level of detail we still could find small errors in the underlying data refinement theory, as well as the formal proofs of the case study. Second, the original Mondex case study verifies functional correctness assuming a suitable security protocol. We extend the case study here with a refinement to a suitable security protocol that uses symmetric cryptography to achieve the necessary properties of the security-relevant messages. The definition is based on a generic framework for defining such protocols based on abstract state machines (ASMs). We prove the refinement using a forward simulation.

Specification and verification challenges for sequential object-oriented programs

Abstract The state of knowledge in how to specify sequential programs in object-oriented languages such as Java and C# and the state of the art in automated verification tools for such programs have made measurable progress in the last several years. This paper describes several remaining challenges and approaches to their solution.

Formal Verification of Simulation Traces Using Computation Slicing

Concurrent and distributed systems, such as system-on-chips (SoCs), present an immense challenge for verification due to their complexity and inherent concurrency. Traditional approaches for eliminating errors in concurrent and distributed systems include formal methods and simulation. We present an approach toward combining formal methods and simulation in a technique called predicate detection (aka runtime verification), while avoiding the complexity of formal methods and the pitfalls of ad hoc simulation. Our technique enables efficient formal verification on execution traces of actual scalable systems. Traditional simulation methodologies are woefully inadequate in the presence of concurrency and subtle synchronization. The bug in the system may appear only when the ordering of concurrent events is different from the ordering in the simulation trace. We use a partial order trace model rather than the traditional total order trace model and we get the benefit of properly dealing with concurrent events and especially of detecting errors from analyzing successful total order traces. Surprisingly, checking properties, even on a finite partial order trace, is NP-complete in the size of the trace description (aka state-explosion problem). Our approach to ameliorating state explosion in partial order trace model uses two techniques: 1) slicing and 2) exploiting the structure of the property itself-by imposing restrictions-to evaluate its value efficiently for a given execution trace. Intuitively, the slice of a trace with respect to a property is a subtrace that contains all of the global states of the trace that satisfy the property such that it is computed efficiently (without traversing the state space) and represented concisely (without explicit representation of individual states). We present temporal slicing algorithms with respect to properties in temporal logic RCTL+. We show how to use the slicing algorithms for efficient predicate detection of design properties. We have developed a prototype system, partial order trace analyzer (POTA), which implements our algorithms. We verify several scalable and industrial protocols, including CORBA's general inter-ORB protocol, PCI-based system-on-chip, ISO's asynchronous transfer mode ring, cache coherence, and mutual exclusion. Our experimental results indicate that slicing can lead to exponential reduction over existing techniques, such as the ones in SPIN model checker, both in time and space

Uppsalator's acceleration

Semiquantitative prediction of the Uppsalator (electroosmotical oscillator developed in Uppsala) under constant voltage is confirmed via numerical solution of exact nonlinear integro-differential equations in partial derivatives (PDE). Critical voltage and characteristic features of pressure and liquid flow velocity as functions of time are reproduced with high precision. In particular, the number of inflection points per period of oscillating velocity increases with growing voltage from two to six. A new feature is demonstrated. For sufficiently high voltages the Uppsalator shows normal deceleration, i.e., the oscillation period grows with voltage. However, in some supercritical range of voltages, acceleration is observed, as expressed by decrease of the oscillation period with growing voltage. Thus, the Uppsalator at constant voltage considered earlier as an impossible phenomenon represents a great challenge for experimental verification.

B3 THE LMS INTEGRATED ENGINEERING PROCESS : A NEW FRONTIER IN SPACE SYSTEMS DEVELOPMENT

Advancements in system verification concern both advancements in test and simulation technologies, methods and practices. It is this combined progress in both areas that will be essential to cope with the challenges of system verification on ever more complex structures. This paper will discuss three areas: The Virtual Engineering Process, where our LMS Virtual. Lab solution allows for the integrated multi-attribute analysis of a spacecraft system. This in turn increases analysis accuracy (more physics can be incorporated and optimized) and increases productivity (a single seamless analysis environment). The Hybrid Engineering Process, where we show our Virtual. Lab Assembly and NVH system synthesis capabilities for combining test and simulation models to produce a coupled simulation response. Optimization, where we show our LMS Virtual. Lab Optimization solution, which allows for the target setting and optimization of key parameters for optimal performance design. Each item will be illustrated with an industry example.

A decision-support system for safeguards information analysis

The international nuclear proliferation control regime is facing the necessity to handle increasing amounts of information in order to assess nations' compliance with their safeguards commitments. The present paper proposes a Decision Support System (DSS) based on a fuzzy logic approach. The inbuilt information aggregation methodology is based on proliferation indicators as 'quanta of information' and develops within the framework of fuzzy sets as their computable counterpart. Both the reliability of the information sources and the relevance of the information are essential characteristics that are taken into account in the aggregation process. The decision-support system described in this work was presented at the IAEA Symposium on International Safeguards Addressing Verification Challenges, Vienna, Austria, 16-20 October 2006, and the fuzzy aggregation methodology at the Fuzzy Logic in Nuclear Science Conference (FLiNS06) in Genoa, Italy, 28-30 August 2006.

How to stop time stopping

Abstract Zeno-timelocks constitute a challenge for the formal verification of timed automata: they are difficult to detect, and the verification of most properties (e.g., safety) is only correct for timelock-free models. Some time ago, Tripakis proposed a syntactic check on the structure of timed automata: if a certain condition (called strong non-zenoness’ SNZ) is met by all the loops in a given automaton, then zeno-timelocks are guaranteed not to occur. Checking for SNZ is efficient, and compositional (if all components in a network of automata are strongly non-zeno, then the network is free from zeno-timelocks). Strong non-zenoness, however, is sufficient-only: There exist non-zeno specifications which are not strongly non-zeno. A TCTL formula is known that represents a sufficient-and-necessary condition for non-zenoness; unfortunately, this formula requires a demanding model-checking algorithm, and not all model-checkers are able to express it. In addition, this algorithm provides only limited diagnostic information. Here we propose a number of alternative solutions. First, we show that the compositional application of SNZ can be weakened: some networks can be guaranteed to be free from Zeno-timelocks, even if not every component is strongly non-zeno. Secondly, we present new syntactic, sufficient-only conditions that complement SNZ. Finally, we describe a sufficient-and-necessary condition that only requires a simple form of reachability analysis. Furthermore, our conditions identify the cause of zeno-timelocks directly on the model, in the form of unsafe loops. We also comment on a tool that we have developed, which implements the syntactic checks on Uppaal models. The tool is also able to derive, from those unsafe loops in a given automaton (in general, an Uppaal model representing a product automaton of a given network), the reachability formulas that characterise the occurrence of zeno-timelocks. A modified version of the carrier sense multiple access with collision detection protocol is used as a case-study.

The Evolution of Site Verification in Interventional Radiology

Caring for patients in interventional radiology (IR) presents unique challenges in procedural site verification. At Children's Hospital Boston, we have developed a site verification process that addresses the issues that differentiate IR from the operating room environment. Our IR site verification process evolved as a result of an incident in which, despite adherence to existing policies, the contralateral site was accessed. As a team, we responded by analyzing and identifying the contributing risk factors specific to IR and incorporating them into a revised site verification checklist that meets JCAHO standards. This poster will follow the evolution of this site verification tool.

Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs

This paper reports our experiences of applying process algebras and associated tools (esp. CSP/FDR2) to verify asynchronous circuit designs developed in the Balsa environment. Balsa is an asynchronous logic synthesis system which uses syntax-directed compilation to generate gate-level implementations from high-level descriptions in a parallel programming language (also called Balsa). Previously, we have proposed a unifying approach to compositionally verifying Balsa designs across several abstraction levels. This paper continues our effort by applying and testing our approach on several large-scale real-life case studies. We describe the outcome of verification for the case studies, and also analyse the strengths and limitations of our method.

Bringing communication networks on a chip: test and verification implications

In this article we present test and verification challenges for system chips that utilize on-chip networks. These SOCs and networks on a chip are introduced, where the NOC is exemplified by Philips' AE THEREAL NOC architecture. We discuss existing test and verification methods for SOCs and NOCs, and show the particular advantages of using an NOC for both testing and verifying the network, and testing and verifying the other components of the SOC. This article is concluded with our experiences with NOCs and a description of ongoing work within Philips in this emerging field.

3GPP W-CDMA systems: design and testing

Newly emerging wireless signal formats can present significant design challenges to the system design engineer. Wideband code division multiple access (W-CDMA) can present many engineering design and verification challenges, due to its physical layer complexity as well as complexities that can arise when integrating RF and baseband designs to achieve a working system. System design engineers typically have the task of interpreting standards specifications, first for partitioning subsystem requirements, then verifying that the end-to-end system design (typically including both baseband and RF designs) will meet specifications when they are finally integrated. This article considers a case study that illustrates the importance of simulating baseband and RF designs together to accomplish this task. Specifically, a conceptual system design that includes system models, a fixed-point finite impulse response filter, and transistor-level circuit design is simulated and verified together against measurements defined in the third-generation partnership project (3GPP) W-CDMA standards specifications. Tradeoffs between improving either the RF or baseband design to meet overall system specifications will be discussed. Finally, design verification using "connected solutions," or connectivity between, electronic design automation software and test equipment will be described, illustrating how verification testing can be started earlier to help reduce risk by identifying performance issues early in the design cycle, when they are potentially easier and costly to implement.

7.5.4 International Space Station Integrated Verification Process

ABSTRACTThe International Space Station (ISS) verification challenge was developing a process that ensured the verification of lots of requirements for a very complex system. The ISS integrated verification process was developed to provide a disciplined engineering approach for the verification of the ISS specification requirements and to provide a traceable archive of verification data needed to sustain ISS operations. The ISS integrated verification process has proven itself to be a tried and true structured process that can be adapted to any type of simple or complex system.

In the best of circumstances: ONUSAL and the challenges of verification and institutional strengthening in El Salvador

No abstract availableRealidad: Revista de Ciencias Sociales y Humanidades No. 56, 1997: 153-185

Verifying Arms Control Agreements: Arms Control Verification . The Technologies That Make It Possible. Kosta Tsipis, David W. Hafemeister, and Penny Janeway, Eds. Published in cooperation with the Program in Science and Technology for International Security, Massachusetts Institute of Technology, by Pergamon- Brassey, Washington, D.C., 1986. xvi, 419 pp., illus. $34.95. From a conference, Cambridge, MA, Feb. 1984.; Verification. .

Verifying Arms Control Agreements: <i>Arms Control Verification</i> . The Technologies That Make It Possible. Kosta Tsipis, David W. Hafemeister, and Penny Janeway, Eds. Published in cooperation with the Program in Science and Technology for International Security, Massachusetts Institute of Technology, by Pergamon- Brassey, Washington, D.C., 1986. xvi, 419 pp., illus. $34.95. From a conference, Cambridge, MA, Feb. 1984.; <i>Verification.</i> .