Carrier-based Modulation Research Articles

Design of Angle based 27-level Trinary Ladder Inverter Using Cross Compiler

This paper presents the design of the Multi-Level Inverter circuit based on the switched ladder topology using the angle events for the level changes. The change of events for the inverter is formulated using the Half Height Algorithm. The VHDL code is utilized for the generation of the angles as digital equivalence with the resolution of 27 bits. In ladder topology, there are several types of inverter namely Binary Ladder Inverter, Ye Progression, Luo Progression. Among all these topologies, the Trinary Ladder topology is advantageous for the number of levels attainment with the less number of switches. Also, the carrier-based modulation is erroneous with the High THD% and low Voltage Parameter values. The use of the non-carrier half-height method manipulates the accurate angle to measure acceptable THD %. The proposed Trinary Switched Ladder Inverter is cross-compiled with Xilinx Vivado and Matlab Simulink Took to evaluate the parameters such as THD%, VRMS, VPEAK, for the 27-level. The parametric analysis exhibits improvement in the proposed Ladder topology with cost, size, and performance when synthesized using the Xilinx Vivado tool.

A Comprehensive Modulation Strategy for the Neutral-Point Clamped Wind Power Converter Thermal Management During Low-Voltage Ride Through

The temperature fluctuations in the semiconductor devices within neutral-point clamped (NPC) wind power converter during low-voltage ride-through operation would reduce the lifetime cycle of the converter and jeopardize the reliability of the wind power system. In this article, a thermal management strategy based on carrier-based modulation techniques, i.e., zero-sequence and dipolar injections, is proposed to address this issue. The temperature fluctuations in semiconductor devices among three phases can be reduced and balanced. Besides, the neutral-point voltage balancing can be guaranteed. Simulation and experimental results are presented to verify the feasibility and effectiveness of the proposed technique. Its influences on the converter total power loss and output current harmonics are discussed as well.

Leakage Current Suppression With Capacitor Voltage Control of Three-Level Flying Capacitor Grid-Connected Inverters

Leakage current issues are worthy of attention for nonisolated grid-connected systems. This article introduces the method of eliminating common-mode (CM) voltage and reducing the leakage current based on modulation, and analyzes the correlation between actual effects of the method and the flying capacitor (FC) voltage balance in three-phase three-level FC grid-connected inverter. The proposed carrier-based modulation can balance the FC voltage by changing the transmission sequences of pulses and theoretically achieve zero CM voltage. In order to deal with the low frequency fluctuation and bias voltage of FC caused by asymmetry of actual hardware, the control method is introduced, which controls FC voltage by changing the action times’ distribution of switches, while still eliminating the CM voltage. Simulation and experimental results are provided to validate that the proposed method can control FC voltage and achieve good performance in suppressions of CM voltage, leakage, current and CM electromagnetic interference noise.

Prediction of DC-Link Voltage Switching Ripple in Three-Phase Four-Leg PWM Inverters

This paper presents a thorough prediction of DC-link voltage switching ripples in the three-phase four-leg inverters operating in balanced and unbalanced working conditions. The unbalanced modes examined here employ the highest degree of AC current imbalance while still preserving three-phase operation. This behavior can be found in many grid-connected or standalone grid-forming three-phase converters that supply “heavy” single-phase loads, comprising a recent trend in smart-grid, smart electric vehicle (EV)-charging applications. In this sense, for instance, the smart EV chargers might be employed in conditions when different power is drawn/injected from/to the grid, providing power conditioning services to the latter. The analysis of three-phase four-leg inverters is then extended to single-phase operations typical of home-charging or vehicle-to-home (V2H) applications. Their performances in terms of DC-link voltage switching ripple are demonstrated. Two of the most common carrier-based PWM modulation techniques are employed to drive the three-phase inverter—namely, sinusoidal PWM and centered PWM (carrier-based analogy of the space vector modulation). The derived mathematical expressions of peak-to-peak and RMS values of DC-link voltage switching ripple for balanced and unbalanced conditions are handy for designing the associated DC-link capacitor and estimating the overall efficiency of the converter. Extensive numerical simulations and experimental tests have been performed to validate the presented analytical developments.

A three-phase transformer based T-type topology for DSTATCOM application

ABSTRACT Among the various reduced switch count multilevel inverter (RSC-MLI) topologies, T-type is the simplified configuration with appreciable reduction in switch count and, posses an ability to serve an alternative to cascaded H-bridge (CHB) MLI. However, extreme reduction in switch count of T-type topology has limited its switching redundancies and created critical dc-link voltage balancing issues in closed-loop applications. In addition, conventional multi-reference PWM scheme reported for T-type produces poor line-voltage total harmonic distortion (THD). Therefore, in this paper, a five-level T-type topology is presented, which involves only one-third dc source requirement of conventional T-type and CHB. This will greatly reduce the dc-link voltage balancing issues and cost. Further, to improve the harmonic performance of conventional multi-reference PWM, a simple carrier-based modulation scheme is proposed. The open and closed performance on the proposed scheme is validated on Simulink and experimental environment considering five-level T-type configuration. To evaluate the dynamic performance of developed T-type configuration, a three-phase three-wire (3P3W) distributed static compensator (DSTATCOM) application is considered, where its ability to eliminate source current harmonics, reactive power and load unbalance is investigated. To promote the superiority of the developed T-type topology, its cost comparison with conventional T-type and CHB is presented.

A Direct Carrier-Based Modulation Scheme With Full Index Range for DC-Link Current Ripple Mitigation of a Current Source Converter

This article presents a direct carrier-based modulation scheme to mitigate the dc-link current ripple for a current source converter (CSC). Excessive dc-link current ripple increases system losses, causes current distortion, and leads to more electromagnetic interference, so, it should be mitigated. Compared with increasing dc-link inductor or switching frequency, it is more attractive to mitigate dc-link current ripple with modulation schemes. However, existing modulation schemes suffer from either high dc-link current ripple or shrink of modulation index range. To address this issue, this article analyzes the mechanism of mitigating the dc-link current ripple and proposes a new modulation scheme for a CSC. By employing two kinds of non-nearest three vectors to synthesize the reference current, the proposed scheme successfully extends the index range from [ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sqrt 3 /3$</tex-math></inline-formula> , 1] to <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[0, 1]</xref> . For easier implementation, its carrier-based modulation, which can automatically select the desired vectors and last predetermined dwell times, is also presented. Theoretical analyses show that the proposed scheme can mitigate the dc-link current ripple over the full index range for a CSC. The effectiveness of the proposed modulation scheme is verified experimentally with a CSC operating as a rectifier.

Optimal Vector Sequences for Simultaneous Reduction of the Switching Loss, Zero-Sequence Circulating Current, and Torque Ripple in Two Parallel Interleaved Inverter-Fed PMSM Drives

The two-parallel interleaved converters system is essentially a multilevel converter and introduces more vector redundancies than a single converter, leaving a large space for vector sequences optimization for the simultaneous optimization of crucial indicators. However, the vector redundancies have not been fully explored by previous studies to achieve multiple crucial indicators optimization. This article aims to obtain high efficiency and low torque ripples for the two-parallel interleaved converters-fed permanent-magnet synchronous motor (PMSM), which are dominantly affected by the switching loss, zero-sequence circulating current (ZSCC), and torque ripples. First, given the vector redundancies, this article explores the available vector sequences according to switching times, the minimal torque ripple, and ZSCC with a priority of the switching times. The resultant vector sequences split each 60° sector into eight subsectors, but each subsector has redundant vector sequences. Then, this article further quantitatively analyzes the torque ripple and ZSCC of the redundant vector sequences in the subsectors, based on which each subsector applies an optimal vector sequence. Despite the complexity of the divisions of the subsectors, this article proposes a simple carrier-based modulation scheme and the implementation of the proposed optimal vector sequences amounts to corresponding common-mode voltage (CMV) injections into the references, which only require a simple logic judgment. The theoretical analysis confirms that the proposed method yields smaller torque ripples, ZSCCs, and switching losses than existing pulsewidth modulation (PWM) schemes over the whole modulation indices. Finally, the experimental results further verify the theoretical analysis and the effectiveness of the proposed strategy.

AC Current Ripple Harmonic Pollution in Three-Phase Four-Leg Active Front-End AC/DC Converter for On-Board EV Chargers

Three-phase four-leg voltage-source converters have been considered for some recent projects in smart grids and in the automotive industry, projects such as on-board electric vehicles (EVs) chargers, thanks to their built-in ability to handle unbalanced AC currents through the 4th wire (neutral). Although conventional carrier-based modulations (CBMs) and space vector modulations (SVMs) have been commonly applied and extensively studied for three-phase four-leg voltage-source converters, very little has been reported concerning their pollution impact on AC grid in terms of switching ripple currents. This paper introduces a thorough analytical derivation of peak-to-peak and RMS values of the AC current ripple under balanced and unbalanced working conditions, in the case of three-phase four-leg converters with uncoupled AC-link inductors. The proposed mathematical approach covers both phase and neutral currents. All analytical findings have been applied to two industry recognized CBM methods, namely sinusoidal pulse-width modulation (PWM) and centered PWM (equivalent to SVM). The derived equations are effective, simple, and ready-to-use for accurate AC current ripple calculations. At the same time, the proposed equations and diagrams can be successfully adopted to design the conversion system basing on the grid codes in terms of current ripple (or total harmonic distortion (THD)/total demand distortion (TDD)) restrictions, enabling the sizing of AC-link inductors and the determination of the proper switching frequency for the given operating conditions. The analytical developments have been thoroughly verified by numerical simulations in MATLAB/Simulink and by extensive experimental tests.

Common-Mode Voltage Reduction Method for Three-Level Inverter With Unbalanced Neutral-Point Voltage Conditions

The three-level inverter has been widely researched and adopted in industry. This article further proposes a carrier-based modulation method to reduce the common-mode voltage (CMV) and obtain high-quality output currents for three-level inverter with unbalanced neutral-point voltage conditions. In this method, the zero-sequence voltage is calculated by three-phase modulation waves, three-phase output currents, and voltages across the dc-link capacitors. The limitations of the zero-sequence component are carefully considered in order not to generate the basic voltage vector with high CMV magnitudes. In addition, a deadbeat control scheme for controlling the dc-link voltages asymmetrically with the proposed pulsewidth modulation method is presented, and asymmetrical control of dc-link voltages can be realized with fast response. Compared with the conventional space vector modulation (SVM) and the virtual SVM methods, the proposed scheme can reduce the CMV by half. Simulated and experimental results validate the effectiveness of the proposed method.

A study on performances of carrier-based pulse-width modulation techniques for three-phase three-level t-type neutral-point-clamped inverter under switch-open-circuit fault on two neutral-point-connected legs

Multilevel voltage source inverters (VSIs) have been used for several decades thanks to their advantages compared with traditional two level VSI. Among various types of multilevel configuration, the T-type neutral-point-clamped VSI (3L TNPC VSI or 333-type VSI) has gained the attention in recent years. Due to the unique structure, the 333-type VSI has critical issues in reliability in operation such as switch-open-circuit (SOC) and switch-short-circuit (SSC), which lead to several unrequired issues, for instance, reduction of system performance, distorted and unbalanced output voltages and currents, or triggering the protection circuits. In some applications, the amplitude reduction and harmonics distortion of output voltages in SOC faults are not acceptable. Therefore, it is necessary to develop a pulse-width modulation (PWM) algorithm for 333-type VSI working under SOC fault which guarantees the desired output fundamental component voltage. The simultaneous SOC fault on two neutral-point-connected legs in the 333-type VSI may cause a large reduction in the output voltage. Under this circumstance, the 333-type VSI becomes an asymmetrical one called 322-type VSI. Certain studies regarding to the operation of 333-type VSI under SOC faults have been carried out. However, these studies require more semiconductor devices in order to create a redundant switching circuit. This leads to higher system cost with reduced inverter effieciency due to the additional loss. In this study, two carrier-based pulse-width modulation (CBPWM) techniques, i.e. 322-sinusoidal PWM (322-SPWM) and 322-medium offset CBPWM (322-MOCBPWM) are proposed for 322-type VSI. The proposed techniques are firstly simulated in MATLAB/Simulink and then implemented on a hardware setup. Performances of the proposed techniques are evaluated in terms of total harmonic distortion (THD) and weighted-THD (WTHD) of output voltages. Simulation results show that considering the worst output voltage under SOC fault, vBC, the proposed 322-SPWM technique could improve the THD by 40% and the WTHD by 94% compared with the uncompensated case with m=0.8. The corresponding results of 322-MOCBPWM technique are 42% and 96%, respectively. Characteristics of THD and WTHD values are also presented for demonstration the effectiveness of the proposed algorithm.

Implementation of LDN to MLI and RSC-MLI configurations with a simple carrier-based modulation

The design of multilevel inverters (MLI) and reduced switch count (RSC) MLIs majorly depend on the requirements of desired output voltage levels, number of dc sources switching devices, and their ratings. With regard to these requirements ‘Level Doubling Network (LDN)’ configuration is introduced. LDN has the ability to double the output voltage levels of any MLI or RSC-MLI, preserving inverter modularity. However, the implementation of LDN to MLI or RSC-MLI is not unified and varies with switching operations. Thus, this work presents the implementation of LDN to popular MLI and RSC-MLI configurations and further presents a brief comparison on theswitch count, number of levels, and harmonic performance for both LDN and non-LDN cases. Further, a generalized carrier-based PWM scheme is presented to implement the LDN for any MLI and RSC-MLI configurations irrespective of voltage levels, dc-voltage ratios, and topological configuration. The performance of the inverter and the proposed modulation scheme are validated on MATLAB/Simulink environment.

Analysis of Cascaded Multilevel Inverter with a Reduced Number of Switches for Reduction of Total Harmonic Distortion

Multilevel inverters (MLI) are aligned with lower harmonics and less commutation losses, which offer high power capacity. MLI is one of the best widespread converters due to its ability to eliminate the harmonic distortion without dropping the converter power output. The cascaded MLI is utilized for a reduced number of switches. In this topology, the switching angles at fundamental frequency are attained by solving the selective harmonic eliminations using sine cosine algorithm. This attains the desired output voltage with the elimination of certain lower order harmonics. In this paper, the analysis of seven-level cascaded MLI is presented with the scheme of carrier-based modulation techniques i.e. Phase-Disposition (PD), Phase-Opposition Disposition (POD) and Alternative Phase-Opposition Disposition (APOD). The Artificial intelligence (AI) is carried out for PD technique. These techniques are capable of defining the required switching angles to eliminate the preferred values of harmonics. The harmonic contents of output voltage in carrier-based modulation are observed with the indices, such as the modulation index with frequency modulation index and amplitude modulation index. The simulation results are obtained for seven-level inverter using MATLAB/SIMULINK. The hardware implementation is carried out using Main Power Management IC TPS65217C Beagle Bone Black Board for seven-level open loop control to justify the achievement of the suggested topology.

An Overall System Delay Compensation Method for IPMSM Sensorless Drives in Rail Transit Applications

In rail transit application, the multimode pulsewidth modulation (PWM) is used to take full advantage of the dc-bus voltage in wide speed range. To improve the sensorless control performance of interior permanent magnet synchronous motor (IPMSM) drives in this condition, an overall system delay compensation method is proposed for a hybrid position observer that combines a simple square-wave voltage injection with a nonsingular terminal sliding mode observer. Due to the delay effect, the currents and position estimation performance are deteriorated, such as more severe dq-axis currents coupling and fluctuation of estimated position error. In order to solve these problems, the analysis of delay characteristics in the IPMSM sensorless drives is first presented. For carrier-based modulation, the compensation time is obtained through a self-tuning PI regulator based on predictive q-axis voltage error. Then, the three-phase reference currents are utilized to judge the direction near zero-crossing point and the parameters robustness is also analyzed. For optimal PWM modulation, the voltage vector angle and modulation depth are predicted in a simple way, and the delay effect can be eliminated. Furthermore, the harmonics distribution in sensorless control is described by power spectral density. Finally, the effectiveness of proposed strategy is verified by experimental results with a 3.7-kW IPMSM sensorless drive platform.

Equivalent Phase Current Harmonic Elimination in Quadruple Three-Phase Drives Based on Carrier Phase Shift Method

Multiphase drives are entering the spotlight of the research community for transportation applications with their high power density and the possibility of high fault tolerance. The multi three-phase drive is one of the main types of multiphase drives that allows for the direct adoption of commercial three-phase converters and high control flexibility. The elimination of high-frequency current harmonics will reduce the flux linkage harmonics, torque ripple, vibration and noise in machine drives. Therefore, this work introduces a new method to the modelling of equivalent phase current in multi three-phase drives with the double integral Fourier analysis method. A new carrier-based pulse-width modulation (CPWM) method is introduced to reduce the equivalent phase current harmonics by applying proper carrier phase angle to each subsystem in the multi three-phase drives. The proposed angles of carrier signals are analyzed for quadruple three-phase drives, and the corresponding experimental results confirm the significance of the proposed phase-shifted CPWM method to eliminate the equivalent phase current harmonics.

Comprehensive Spectral Analysis of PWM Waveforms With Compensated DC-Link Oscillations

In the available literature, including reference books on the topic, the spectral analysis of voltage waveforms obtained through the use of pulse width modulation (PWM) relies on the assumption of an ideally flat voltage across the dc-link of a considered switching structure. Nevertheless, certain converter families (e.g., modular multilevel converter, characterized by the presence of distributed and floating dc-links), feature low-frequency oscillations of dc voltage within their switching stages. On these terms, the flat dc-link assumption cannot be considered valid from both theoretical and practical viewpoints. In case carrier-based modulation is employed, unless properly compensated through the modulation signal adjustments, the above mentioned voltage oscillations cause undesirable distortion of the converter currents. However, the very same adjustments of modulation signals introduce additional challenges in the spectral analysis of the voltage across the ac terminals of an observed switching stage. This article provides the ac terminals voltage analysis of a single half-bridge experiencing dc-link oscillations, which are compensated through the modulation signal generation process. PWM with the conventional triangular carrier is considered, while all the results are presented in a generalized form, making them easily extendable to cascaded structures. All of the presented results were experimentally validated.

A Novel Space Vector Modulation Scheme for a 10-Switch Converter

Three-level converters have drawn extensive attention due to their ability to deliver high-quality power. High semiconductor count is the main drawback of three-level converters. As a solution to this, a 10-switch converter is presented, that has advantages over both two- and three-level converters, simultaneously, plus it is applicable to a variety of power ranges. However, the switching pattern of 10-switch converter is not as simple as standard three-level converter due to lack of medium vectors. This paper presents a novel space vector modulation (SVM) for a 10-switch converter to reduce total harmonic distortion (THD) and common mode voltage (CMV) of this converter in comparison to prior carrier-based modulation methods. A simplified, low-cost modulation algorithm for the converter is proposed. The designed switching sequence has aimed at a low output THD and enhancement of DC bus voltage utilization. The performance of the proposed SVM is then compared to upgraded sinusoidal PWM. AC power quality and CMV of a 10-switch converter based on two modulation methods are investigated via simulation models. It was validated via simulation and experimental models that the proposed SVM utilized DC bus voltage more efficiently, generated remarkably less THD compared to other methods, and had a lower peak and rms CMV.

A Capacitor Voltage Balancing Scheme for Single-Source Fed Switch Optimized Three-Phase Nine-Level Inverter

This article proposes a novel floating capacitor (FC) and dc-link capacitor voltage balancing scheme for a single-source three-phase nine-level inverter with reduced part count. Although nine levels are generated by keeping the dc-link capacitor voltage to FC voltage ratio as 3:1, it comes with complete absence of any useful pole voltage redundancies. Therefore, the conventionally adopted redundant-state-switching-based pulsewidth modulation technique cannot be applied for FC voltage balancing. Hence, a novel carrier-based modulation scheme is proposed here, which addresses the issue of FC voltage balancing by safely clamping the modulating reference to pole voltage levels that aid in FC voltage balancing. The dc-link capacitor voltages are also balanced using a unique way suitable for this inverter having nonredundant characteristics. Simulation and experimental results verify the capability of the proposed balancing scheme for the optimized nine-level inverter under different modulation and load conditions. It is found that a maximum fundamental phase peak voltage of 0.607 times dc-link voltage (at 0.91 modulation index) can be achieved at unity power factor and, thus, utilizing the dc bus of the inverter effectively.

A Composite Voltage-Balancing Method for Four-Level NPC Inverters

Four-level neutral-point-clamped (NPC) inverter suffers from the neutral-point (NP) voltage-balancing problem, which seriously hinders its application in the industry. Carrier-overlapped pulsewidth modulation (COPWM) is a newly proposed carrier-based modulation method which can solve this problem. However, the total switching transitions under this modulation method are doubled, and hence the switching losses are increased. In order to alleviate this problem, a composite modulation and voltage-balancing method is proposed in this article. For a low modulation index range under 0.5, phase-disposition pulsewidth modulation (PDPWM) is utilized and the relationship between the NP currents and the reference phase voltage is derived. A zero-sequence voltage injection-based NP voltage balancing method is proposed. For a high modulation index range more than 0.5, a decoupled voltage-balancing method based on COPWM is used. By combining the two modulations and voltage-balancing methods, the NP voltages can be balanced under the full modulation index range with reduced switching losses. Simulation and experimental results are presented to confirm the validity of this method.

Current Balancing Control Methods Using Advanced Carrier-Based Modulation for Five-Level Current Source Rectifiers

In an ideal ac–dc five-level current source multilevel converter, the dc current is equally divided between the two converters connected in parallel. However, current imbalances occur due to the nonidealities of the system, making the current balancing control to improve the multilevel converter performance. This article proposes two different methods for dc current balancing control for a five-level current source rectifier using an advanced carrier-based modulation strategy implemented through three different modulation patterns. A 6-kW prototype is constructed to demonstrate the current balancing control and a comparison among the methods is presented.

Elimination of Common Mode Voltage in the Three-To-Nine-Phase Matrix Converter

A multiphase matrix converter (MC) is a direct AC/AC converter with n-phase input and m-phase output that is required to supply multiphase systems. To synthesize the controllable sinusoidal output voltage and input current with controllable displacement angle, the pulse width modulation (PWM) is implemented. On account of the PWM usage, there is common mode voltage (CMV), which is detrimental and causes lots of failures. This paper investigates the CMV elimination in the three-to-nine-phase MC. The carrier-based space vector modulation (SVM) with Venturini modulation functions is used. The elimination of the CMV is realized by applying rotating voltage space vectors only. The simulation results presented in this study show that the CMV is entirely eliminated and prove the usefulness of the proposed modulation method.