Carbon Nanotube Field-effect Transistors Circuits Research Articles

A Review on low-Power VLSI CMOS and CNTFET Circuits

Nowadays, power consumption is one of the primary considerations in the design of VLSI (Very Large Scale Integration) circuits based on complementary metal oxide semiconductors (CMOS) and carbon nanotube field effect transistors (CNTFET). This is because of the present circumstance. The fundamental reason for this is that power utilisation has been raised to the status of a top priority due to the improvements in integration and scaling as well as the constant increases in operating frequency. Additional power consumption from circuits and designs makes them challenging to implement in portable devices. The quantity of power lost during operation has an immediate effect on the cost of packaging the IC and systems. A variety of power dissipation sources and low power VLSI design strategies for CMOS and CNTFET-based circuits are discussed in this article.

Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits

Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional devices, the emerging device technologies such as Graphene Nano Ribbon Field Effect Transistor (GNRFET) and carbon nanotube field effect transistor (CNTFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties such as the ability to control the threshold voltage. This variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit.This work presents a 4-input ternary adder using carbon nanotube field effect transistor (CNTFET). Many researchers have been done work on implementation of ternary adders and multipliers. But no one has done the comparison of this proposed ternary adder with different types of nano transistors. Hence this work has been proposed a design of low power and high speed 4-input adder which will be useful for designing of fast ternary multipliers. All the proposed designs have been simulated using emerging device such as CNTFET at 32nm technology node. From the simulations, we have calculated the power consumptions of the proposed designs, carry propagation delay and power delay product for the CNTFET circuits. It has been observed that CNTFET based proposed logic circuits given a better performance than the conventional logical circuits.

Modification of a carbon nanotube FET compact model for digital circuit simulation

Carbon nanotube field-effect transistor (CNTFET) based circuit systems have received extensive attention due to their energy-efficiency benefits. However, there is not yet a generally accepted compact SPICE model for CNTFETs compatible with existing electronics design automation platforms. In this paper, the Stanford top gate CNTFET model is optimized through the consideration of different doping levels in source/drain as well as the simplification of an equivalent capacitance network in the intrinsic channel. Based on this, compact models are built for both top gate and wrapped gate CNTFETs. Then the DC properties and the cut-off frequency of top gate and wrapped gate CNTFETs with 15 nm channel length, and their basic logic circuits based on our modelling, are simulated by HSPICE. In the circuit simulation, we add the influence of gate-to-gate capacitance. The influences of structural parameters such as the diameter, number of CNTs and their gap on the current–voltage property, transconductance, cut-off frequency, circuit delay and power consumption are studied. Through comparison with the simulation using the Stanford model, our modelling is more suitable for the design and development of CNTFET circuits. For given parameters, the top gate CNTFETs have a larger maximum cut-off frequency and the wrapped gate CNTFETs’ saturate current is larger. Wrapped gate logic circuits have less delay but more dynamic power than top gate circuits. More CNTs in FETs with a bigger gap and shorter tube pitch lead to less circuit delay and more dynamic power.

Carbon Nanotube-Based CMOS SRAM: 1 kbit 6T SRAM Arrays and 10T SRAM Cells

We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate 1 kbit (1024) 6 transistor (6T) SRAM arrays fabricated with complementary metal-oxide-semiconductor (CMOS) CNFETs (totaling 6144 p- and n-type CNFETs), with all 1024 cells functioning correctly without any per-unit customization. Moreover, we show the first demonstration of CNFET CMOS 10T SRAM cells, capable of operating at highly scaled voltages down to 300 mV. We characterize the CNFET CMOS SRAM and demonstrate robust operation by writing and reading multiple patterns (to both the kbit arrays as well as the 10T SRAM cells), measuring SRAM variations in read, write, and hold margins and repeat cycling of cells. Moreover, due to the low-temperature back-end-of-line (BEOL)-compatible CNT-specific processing, CNFET SRAM enables new opportunities for digital systems, since: 1) CNFET SRAM can be fabricated directly on top of computing logic to realize three-dimensional integrated circuits; and 2) CNFET circuits can utilize metal routing both above and below the CNFET device layer (e.g., as in our demonstration which utilizes buried power rails, whereby the power rails are fabricated underneath the FETs while metal routing is fabricated above the FETs), providing opportunities for further SRAM density scaling.

Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization

Carbon nanotube field-effect transistors (CNFETs) show great potential to build digital systems on advanced technology nodes with big benefits in terms of power, performance, and area (PPA). However, CNFET-specific additional features such as the number of tubes, pitch (spacing between tubes), tube position, and diameter in array of tubes play a significant role in accurate PPA evaluation. Furthermore, count and density variations in carbon nanotubes (CNTs) due to manufacturing limitations, like the presence of metallic tubes in the CNFET channel, degrade the anticipated PPA benefits. Moreover, modeling the CNFET parameters, CNT variations and etching techniques for CNTs create additional complexity during performance optimization. Hence, for realistic optimization of CNFET circuit’s performance, it is imperative to incorporate the impact of these parameters and variations. In this paper, we propose delay models [pitch-aware logical effort (PALE) and position-aware pitch factor (PAPF)] for fast and accurate performance evaluation by including the impact due to CNFET-specific parameters and CNT variations. These models are developed based on industry standard logical effort framework. Furthermore, we present an optimization tool using PALE and PAPF to minimize the delay and area of CNFET circuits. We deploy several circuit-level techniques prior to optimizing the tubes (CNTs) in the logic gates to achieve globally optimum solution. For better optimization of the circuits, we also include the impact of wire parasitic in estimating the delay of the individual gates. Our optimization tool results in the maximum and average delay improvement by 27% and 17%, respectively, and $2.5\times $ reduction in area for standard ISCAS and OpenSPARC benchmark circuits. Fast and fairly accurate delay computation in our optimization framework offers great runtime benefits as compared to state-of-the-art simulation and statistical-based methods.

Low-Temperature Side Contact to Carbon Nanotube Transistors: Resistance Distributions Down to 10 nm Contact Length

Carbon nanotube field-effect transistors (CNFETs) promise to improve the energy efficiency, speed, and transistor density of very large scale integration circuits owing to the intrinsic thin channel body and excellent charge transport properties of carbon nanotubes. Low-temperature fabrication (e.g., <400 °C) is a key enabler for the monolithic three-dimensional (3D) integration of CNFET digital logic into a device technology platform that overcomes memory bandwidth bottlenecks for data-abundant applications such as big-data analytics and machine learning. However, high contact resistance for short CNFET contacts has been a major roadblock to establishing CNFETs as a viable technology because the contact resistance, in series with the channel resistance, reduces the on-state current of CNFETs. Additionally, the variation in contact resistance remains unstudied for short contacts and will further degrade the energy efficiency and speed of CNFET circuits. In this work, we investigate by experiments the contact resistance and statistical variation of room-temperature fabricated CNFET contacts down to 10 nm contact lengths. These CNFET contacts are ∼15 nm shorter than the state-of-the-art Si CMOS "7 nm node" contact length, allowing for multiple generations of future scaling of the transistor-contacted gate pitch. For the 10 nm contacts, we report contact resistance values down to 6.5 kΩ per source/drain contact for a single carbon nanotube (CNT) with a median contact resistance of 18.2 kΩ. The 10 nm contacts reduce the CNFET current by as little as 13% at VDS = 0.7 V compared with the best reported 200 nm contacts to date, corroborated by results in this work. Our analysis of RC from 232 single-CNT CNFETs between the long-contact (e.g., 200 nm) and short-contact (e.g., 10 nm) regimes quantifies the resistance variation and projects the impact on CNFET current variability versus the number of CNT in the transistor. The resistance distribution reveals contact-length-dependent RC variations become significant below 20 nm contact length. However, a larger source of CNFET resistance variation is apparent at all contact lengths used in this work. To further investigate the origins of this contact-length-independent resistance variation, we analyze the variation of RC in arrays of identical CNFETs along a single CNT of constant diameter and observe the random occurrence of high RC, even on correlated CNFETs.

A fast method for process reliability analysis of CNFET-based digital integrated circuits

Due to aggressive technology scaling in electronic of digital integrated circuits, the circuit reliability is becoming an ever-increasing challenge. In nanoscale technologies, the physical and chemical properties of materials are fundamentally different compared to the larger scales. Therefore, it is necessary to revise the conventional reliability assessment techniques considering their applicability to nanoscale integrated circuits. This paper presents a method for evaluating the circuit reliability at the transistor level of abstraction considering the physical characteristics of the transistors. The proposed method considers various parameters, including the probability of different types of a transistor failure, the topology of logic gates and the logical values of the applied input vectors. Experimental results show that the proposed approach provides accurate transistor-level circuit reliability evaluations (with < 4% inaccuracy) as compared to a reference method based on Monte Carlo HSPICE simulations in addition to more than 800 times speedup. Moreover, to show the comprehensiveness and extensibility of the proposed reliability analysis method for the technologies beyond conventional MOSFETs, it is applied to carbon nanotube field-effect transistor (CNFET) technology as one of the most promising candidates for future CMOS circuits. The obtained results re-acknowledge that in order to achieve a more accurate reliability estimation approach for CNFET circuits, it is necessary to consider the open and short failure probability values individually instead of considering them in the form of a single transistor failure probability.

Channel and Gate Workfunction-Engineered CNTFETs for Low-Power and High-Speed Logic and Memory Applications

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green’s functions (NEGF) solved self - consistently with Poisson’s equations. It is revealed that hetero -material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ФSUBM1/SUB/ФSUBM2/SUB have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

Optimization of CNFET Parameters for High Performance Digital Circuits

The Carbon Nanotube Field Effect Transistor (CNFET) is one of the most promising candidates to become successor of silicon CMOS in the near future because of its better electrostatics and higher mobility. The CNFET has many parameters such as operating voltage, number of tubes, pitch, nanotube diameter, dielectric constant, and contact materials which determine the digital circuit performance. This paper presents a study that investigates the effect of different CNFET parameters on performance and proposes a new CNFET design methodology to optimize performance characteristics such as current driving capability, delay, power consumption, and area for digital circuits. We investigate and conceptually explain the performance measures at 32 nm technologies for pure-CNFET, hybrid MOS-CNFET, and CMOS configurations. In our proposed design methodology, the power delay product (PDP) of the optimized CNFET is about 68%, 63%, and 79% less than that of the nonoptimized CNFET, hybrid MOS-CNFET, and CMOS circuits, respectively. Therefore, the proposed CNFET design is a strong candidate to implement high performance digital circuits.

Fault Tolerant Design and Analysis of Carbon Nanotube Circuits Affixed on DNA Origami Tiles

Due to its programmable nature, DNA nanotechnology is currently one of the most advanced and most reliable self-assembly-based methodologies for constructing molecular-scale structures and devices. This makes DNA nanotechnology a highly promising candidate for generating radically new manufacturing technologies. Our specific interest is in the use of DNA as a template and scaffold for the self-assembly of carbon-nanotube field effect transistor (CNFET) circuits. In this paper, we introduced a novel high-level design framework for self-assembling CNFET circuits. According to this methodology, the elements of the circuits, i.e., CNFETs and the connecting carbon nanotube wires, are affixed on different rectangular DNA scaffolds, called tiles, and self-assemble into the desired circuit. The introduced methodology presents several advantages, both at the design level, and for analyzing the reliability of these systems. We make use of these advantages and introduce a new fault-tolerant architecture for CNFET circuits. Then, we analyze its reliability both by computer simulations and by analytical methods.

Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits

As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/μm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/μm.

Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations

Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly-scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfortunately, existing approaches for such exploration and optimization are computationally expensive, and mostly rely on trial-and-error-based ad hoc techniques. In this paper, we present a framework that quickly evaluates the impact of CNT variations on circuit delay and noise margin, and systematically explores the large space of CNT processing options to derive optimized CNT processing and CNFET circuit design guidelines. We demonstrate that our framework: 1) runs over 100x faster than existing approaches, and 2) accurately identifies the most important CNT processing parameters, together with CNFET circuit design parameters (e.g., for CNFET sizing and standard cell layouts), to minimize the impact of CNT variations on CNFET circuit speed with less than 5% energy cost, while simultaneously meeting circuit-level noise margin and yield constraints.

Performance analysis of an ultralow power circuit using single halo CNTFETs

This work presents a comprehensive study of the influence of channel engineering on the switching, high frequency characteristics, and circuit-level performance of carbon nanotube field-effect transistors (CNTFETs). At the device level, new CNTFETs with single halo doping (SH-CNTFETs) have been proposed. The impact of SH implantation on the cutoff frequency (fT), switching delay (τ), and on/off current ratio (Ion/Ioff) has been explored and it is revealed that SH-CNTFETs have improved radio frequency (RF) and switching characteristics. At the circuit level, using the Hailey Simulation Program with IC Emphasis (HSPICE) with lookup table (LUT)-based Verilog-A models, the performance parameters of the circuit have been calculated. Results show that compared to a conventional CNTFET (C-CNTFET)-based inverter, the SH-CNTFET-based inverter exhibits better performance. In addition, we evaluate the stability and performance of six-transistor (6T) CNTFET static random access memory (SRAM) cells with SH-CNTFETs. The performance parameters such as static noise margin (SNM) and write delay as well as power-delay product (PDP) and SNM/write delay (SWD) have been calculated and optimized. It is shown that SH-CNTFET SRAMs have an improved performance in SNM, PDP, and write power compared to C-CNTFET SRAMs and the optimum halo doping level has been concluded. Our results may be useful for designing and optimizing CNTFET devices and circuits.

Carbon Nanotube Circuit Integration up to Sub-20 nm Channel Lengths

Carbon nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging technology projected to achieve over an order of magnitude improvement in energy-delay product, a metric of performance and energy efficiency, compared to silicon-based circuits. However, due to substantial imperfections inherent with CNTs, the promise of CNFETs has yet to be fully realized. Techniques to overcome these imperfections have yielded promising results, but thus far only at large technology nodes (1 μm device size). Here we demonstrate the first very large scale integration (VLSI)-compatible approach to realizing CNFET digital circuits at highly scaled technology nodes, with devices ranging from 90 nm to sub-20 nm channel lengths. We demonstrate inverters functioning at 1 MHz and a fully integrated CNFET infrared light sensor and interface circuit at 32 nm channel length. This demonstrates the feasibility of realizing more complex CNFET circuits at highly scaled technology nodes.

Radio-Frequency Performance of Carbon Nanotube-Based Devices and Circuits Considering Noise and Process Variation

This paper provides a global overview of the radio-frequency (RF) performance potential of carbon-nanotube field-effect transistors (CNFET), which for the first time includes the impact of noise. We develop noise and manufacturing process variability extensions for the Stanford CNFET compact model, implemented in Verilog-A and compatible with conventional circuit simulators. CNFET figures-of-merit (FoM) are determined both on the device and on the circuit level. Compared to silicon technology, CNFET devices show much better performance in terms of most of the RF-CMOS requirements of the International Technology Roadmap for Semiconductors. FoM projections for basic RF building blocks (low-noise amplifier and oscillator) show that good performance can already be obtained with simple circuit topologies. The main advantage of CNFET circuits yet lies in easily reaching operation frequencies of several hundreds of gigahertz, which are hard to be exploited by silicon technologies at similar technology nodes.

Carbon Nanotube Robust Digital VLSI

Carbon nanotube field-effect transistors (CNFETs) are excellent candidates for building highly energy-efficient electronic systems of the future. Fundamental limitations inherent to carbon nanotubes (CNTs) pose major obstacles to the realization of robust CNFET digital very large-scale integration (VLSI): 1) it is nearly impossible to guarantee perfect alignment and positioning of all CNTs despite near-perfect CNT alignment achieved in recent years; 2) CNTs can be metallic or semiconducting depending on chirality; and 3) CNFET circuits can suffer from large performance variations, reduced yield, and increased susceptibility to noise. Today's CNT process improvements alone are inadequate to overcome these challenges. This paper presents an overview of: 1) imperfections and variations inherent to CNTs; 2) design and processing techniques, together with a probabilistic analysis framework, for robust CNFET digital VLSI circuits immune to inherent CNT imperfections and variations; and 3) recent experimental demonstration of CNFET digital circuits that are immune to CNT imperfections. Significant advances in design tools can enable robust and scalable CNFET circuits that overcome the challenges of the CNFET technology while retaining its energy-efficiency benefits.

A novel, efficient CNTFET Galois design as a basic ternary-valued logic field

This paper presents arithmetic operations, including addition and multiplication, in the ternary Galois field through carbon nanotube field-effect transistors (CNTFETs). Ternary logics have received considerable attention among all the multiple-valued logics. Multiple-valued logics are an alternative to common-practice binary logic, which mostly has been expanded from ternary (three-valued) logic. CNTFETs are used to improve Galois field circuit performance. In this study, a novel design technique for ternary logic gates based on CNTFETs was used to design novel, efficient Galois field circuits that will be compared with the existing resistive-load CNTFET circuit designs. In this paper, by using carbon nanotube technology and avoiding the use of resistors, we will reduce power consumption and delay, and will also achieve a better product. Simulation results using HSPICE illustrate substantial improvement in speed and power consumption.

Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations

Variations in the spatial density of carbon nanotubes (CNTs), resulting from the lack of precise control over CNT positioning during chemical synthesis, is a major hurdle to the scalability of carbon nanotube field effect transistor (CNFET) circuits. Such CNT density variations can lead to non-functional CNFET circuits. This paper presents a probabilistic framework for modeling the CNT count distribution contained in a CNFET of given width, and establishes the accuracy of the model using experimental data obtained from CNT growth. Using this model, we estimate the impact of CNT density variations on the yield of CNFET very large-scale integrated circuits. Our estimation results demonstrate that CNT density variations can significantly degrade the yield of CNFETs, and can be a major concern for scaled CNFET circuits. Finally, we analyze the impact of CNT correlation (i.e., correlation of CNT count between CNFETs) that exists in CNT growth, and demonstrate how the yield of a CNFET storage circuit (primarily limited by its noise immunity) can be significantly improved by taking advantage of such correlation.

Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance

Current transport and dynamic models of carbon nanotube field-effect transistors are presented. A model of single-walled carbon nanotube as interconnect is also presented and extended in modeling of single-walled carbon nanotube bundles. These models are applied in studying the performances of circuits such as the complementary carbon nanotube inverter pair and carbon nanotube as interconnect. Cadence/Spectre simulations show that carbon nanotube field-effect transistor circuits can operate at upper GHz frequencies. Carbon nanotube interconnects give smaller delay than copper interconnects used in nanometer CMOS VLSI circuits.

Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits

Carbon-nanotube (CNT) field-effect transistors (CNFETs) are promising extensions to silicon CMOS. Simulations show that CNFET inverters fabricated with a perfect CNFET technology have 13 times better energy delay product compared with 32-nm silicon CMOS inverters. The following two fundamental challenges prevent the fabrication of CNFET circuits with the aforementioned advantages: 1) misaligned and mispositioned CNTs and 2) metallic CNTs. Misaligned and mispositioned CNTs can cause incorrect functionality. This paper presents a technique for designing arbitrary logic functions using CNFET circuits that are guaranteed to implement correct functions even in the presence of a large number of misaligned and mispositioned CNTs. Experimental demonstration of misaligned and mispositioned CNT-immune logic structures is also presented.