Capacitorless DRAM Research Articles

Comparative analysis of capacitorless DRAM performance according to stacked junctionless gate-all-around structures

The characteristic comparison of the capacitor-less DRAMs in the structural form variation is investigated. Based on the simulation results of the three basic structures, such as circular, square, and rectangular nanosheets, the gate length (Lg), channel thickness (Tsi), and width of the nanosheet (Wsi) are considered as the main factors in design and the characteristic variations are verified according to the junctionless (JL) gate-all-around (GAA) geometry factors. The channel thickness is a major factor that has a major influence on the sensing margin and the retention time, which are important characteristics of DRAM. The thinner the thickness, the more deteriorated the sensing margin is confirmed. Retention time is due to the influence of the electric field distribution of the JL GAA structure, resulting in differences in structure. Finally, the rectangular type nanosheet is implemented in the stacked structure. As the number of stacks increases, the effective channel width increases compared to the layout footprint. In addition, by stacking vertically, the area where holes can be stored increases. Therefore, the sensing margin tends to increase as the number of stacks increases. However, the difference in diffusion due to the difference in the initially stored hole density, the retention time deteriorates as the number of stacks increases

CMOS Logic and Capacitorless DRAM by Stacked Oxide Semiconductor and Poly-Si Transistors for Monolithic 3-D Integration

CMOS Logic and Capacitorless DRAM by Stacked Oxide Semiconductor and Poly-Si Transistors for Monolithic 3-D Integration

Simulation of capacitorless DRAM based on polycrystalline silicon with a vertical underlap structure and a separated channel layer

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on polycrystalline silicon (poly-Si) with a vertical underlap structure and a separated channel layer was designed and analyzed. The memory performance was improved by the vertical underlap structure and the region separated into channel and storage layers. The vertical underlap structure suppressed the recombination rate by storing the holes in the isolated body and could be more easily fabricated than a conventional underlap structure. The thicknesses of the vertical underlap structure and storage region were optimized to enhance the memory performance. When the grain boundary (GB) is centrally located, the proposed 1T-DRAM demonstrates a retention time and sensing margin of 3.618 s and 29.93 μA μm−1, respectively. Even when the GB is in the worst position at T = 358 K, the memory still shows a retention time of 1.991 s and a sensing margin of 4.51 μA μm−1.

Simulation of Capacitorless DRAM Based on the Polycrystalline Silicon Nanotube Structure with Multiple Grain Boundaries.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM), based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is designed and analyzed using technology computer-aided design (TCAD) simulation. In the proposed 1T-DRAM, the 1T-DRAM cell exhibited a sensing margin of 422 μA/μm and a retention time of 213 ms at T = 358 K with a single GB. To investigate the effect of random GBs, it was assumed that the number of GB is seven, and the memory characteristics depending on the location and number of GBs were analyzed. The memory performance rapidly degraded due to Shockley-Read-Hall recombination depending on the location and number of GBs. In the worst case, when the number of GB is 7, the mean of the sensing margin was 194 µA/µm, and the mean of the retention time was 50.4 ms. Compared to a single GB, the mean of the sensing margin and the retention time decreased by 59.7% and 77.4%, respectively.

Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications

High-speed write/read operation and low energy consumption along with a lower footprint are prerequisites for one transistor (1 T) embedded DRAM (eDRAM). This work evaluates the suitability of two different reconfigurable transistors (RFET) architectures for implementing 1T-eDRAM based on key metrics such as high-temperature operation, speed, scalability, and energy consumption. Amongst the two topologies, a twin gate RFET (with one control and program gate each on top and bottom gate oxide) is better suited for 1T-eDRAM due to (i) fast write (∼1 ns) and read (∼1 ns) operations, (ii) scalability down to a total source-to-drain length of 60 nm, (iii) better sense margin, and (iv) lower energy consumption during write operation. However, RFET topology with two program gates and one control gates (each on top and bottom gate oxide) shows an enhanced retention time but at the expense of higher energy consumption which may be a challenge for energy efficient system-on-chip applications.

Capacitorless DRAM Cells Based on High-Performance Indium-Tin-Oxide Transistors With Record Data Retention and Reduced Write Latency

In this work, capacitorless memory cells using high mobility ultrathin indium-tin-oxide (ITO) channel are successfully demonstrated, addressing the retention and latency challenges in 2T0C DRAM cells based on wide bandgap oxide semiconductors. The short channel 50 nm ITO FET shows excellent transconductance exceeding <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$300 ~\mu \text{S}/\mu \text{m}$ </tex-math></inline-formula> and record-high on-state current of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$990 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1450 ~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> at room temperature and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$85 ^{\circ} \text{C}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {ds}} =0.5$ </tex-math></inline-formula> V. BEOL-compatible 2T0C DRAM cells exhibit record-long retention time of 2250 s and 425 s at room temperature and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$85 ^{\circ} \text{C}$ </tex-math></inline-formula> , respectively, owing to the low off-state leakage current from the wide bandgap. A fast write speed of 100 ns can be obtained experimentally, with a projected value down to ~ 1 ns, owing to the high on-current of the ITO access transistor, much faster than previously projected values. This work shows the potential of the ITO transistor for future nonvolatile monolithic 3D DRAM.

Capacitor-Less 4F DRAM Using Vertical InGaAs Junction for Ultimate Cell Scalability

In this work, we demonstrated capacitor-less 4F2 2-terminal InGaAs npn junction DRAM through careful device design. Using epitaxially grown InGaAs which have a steep junction, fabricated InGaAs bistable resistor (biristor) DRAM showed low voltage operation (~2 V), fast switching speed (<20 ns), long-term retention (103 s at 85 °C), and high endurance (>1010 cycles) with a high sensing margin. Considering this feasibility study, we believe that InGaAs <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{n}^{+}$ </tex-math></inline-formula> pn+ junction DRAM could be a good technological option for future scalable 3D DRAM.

A Novel Capacitorless 1T DRAM with Embedded Oxide Layer.

A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate of stored holes and sensing electrons. Based on TCAD simulations, the new structure is predicted to not only have the characteristics of fast access, random read and integration of 4F2 cell, but also to realize good retention and deep scaling. At the same time, the new structure has the potential of scaling compared with the conventional capacitorless 1T DRAM.

Design of a Capacitorless DRAM Based on Storage Layer Separated Using Separation Oxide and Polycrystalline Silicon

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon (Poly-Si) metal-oxide-semiconductor field-effect transistor (MOSFET) with a storage layer separated using a separation oxide was designed and analyzed using technology computer-aided design (TCAD). The channel and storage layers were separated using a separation oxide to improve the inferior retention time of the conventional 1T-DRAM, and we adopted the underlap structure to reduce Shockley-Read-Hall recombination. In addition, poly-Si, which has several advantages, including low manufacturing cost and availability of high-density three-dimensional (3D) memory arrays, is used to easily fabricate silicon-on-insulator (SOI)-like structures. Accordingly, we extracted memory performance by analyzing the effect of grain boundary (GB). The proposed 1T-DRAM achieved a sensing margin of 14.10 μA/μm and a retention time of 251 ms at T = 358 K, even in the existence of a GB.

Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure.

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 μA/μm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future.

3-D stacked polycrystalline-silicon-MOSFET-based capacitorless DRAM with superior immunity to grain-boundary’s influence

In this paper, a capacitorless one-transistor dynamic random access memory (1 T-DRAM) based on a polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect transistor with the asymmetric dual-gate (ADG) structure is designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was used within the device due to its low fabrication cost and feasibility in high-density three-dimensional (3-D) memory arrays. We studied the transfer characteristics and memory performances of the single-layer ADG 1 T-DRAMs and the 3-D stacked ADG 1 T-DRAMs and analyze the reliability depending on the location and the number of grain-boundaries (GBs). The relative standard deviation (RSD) of the threshold voltages (Vth) is depending on the location and the number of GBs. The RSDs of the single-layer ADG 1 T-DRAM and the 3-D stacked ADG 1 T-DRAM are 1.58% and 0.68%, respectively. The RSDs of retention time representing the memory performances are 54.7% and 41%, respectively. As a result of the 3-D stacked structure, the averaging effect occurs, which greatly aids in improving the reliability of the memory performances as well as the transfer characteristics of 1 T-DRAMs depending on the influence of GBs. The proposed 3-D stacked ADG 1 T-DRAM helps implement a high-reliability single-cell memory device.

Effect of Work-function Variation on Transfer Characteristics and Memory Performances for Gate-all-around JLFET based Capacitorless DRAM

In this study, we present variations in transfer characteristics and memory performances caused by work-function variation (WFV) in the metal gate of a one-transistor dynamic random-access memory cell based on a gate-all-around junctionless field-effect transistor (GAA-JLFET). To investigate the influence of WFV, we simulated 200 samples of GAA-JLFETs. The samples had different transfer characteristics depending on the metal grain granularity. In addition, we calculated and analyzed the mean and standard deviations for the transfer characteristics. Further, the memory performances were analyzed using two extreme cases with the highest and lowest threshold voltage (V<SUB>th</SUB>) as examples. When WFV was not considered, the current ratio was 108, and retention time was more than 10 ms. Meanwhile, when WFV was considered, the current ratio was 10² and 10⁴, and the retention time was reduced to 0.051 ms and 2.2 ms, respectively. These results showed that WFV affected not only the transfer characteristics in GAA-JLFET but also the memory performances; it could adversely affect the reliability of the memory device.

Polycrystalline-Silicon-MOSFET-Based Capacitorless DRAM With Grain Boundaries and Its Performances

In this work, a capacitorless one-transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect transistor was designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was utilized within the device because of several advantages, including its low fabrication cost and the feasibility of its use in high-density three-dimensional (3D) memory arrays. An asymmetric dual-gate structure is proposed to perform the write “1” operation and achieve high retention characteristics. The proposed 1T-DRAM cell demonstrates a high sensing margin of 8.73 μA/μm and a high retention time of 704.4 ms compared to previously reported 1T-DRAMs, even at a high temperature. In addition, the effect of grain boundaries on the memory performance of the proposed device was investigated, and the results validated the excellent reliability of its retention characteristics even in the presence of grain boundaries (>64 ms at T = 358 K).

Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure

Design of Capacitorless DRAM Based on Polycrystalline Silicon Nanotube Structure

Electrical and Data-Retention Characteristics of Two-Terminal Thyristor Random Access Memory

Two-terminal (2-T) thyristor random access memory (TRAM) based on nanoscale cross-point vertical array is investigated in terms of lengths and doping concentrations of storage regions for long data retention time ( T ret). For high device scalability and low program voltage ( V P), lengths of the storage regions are determined by the sum of depletion widths of N- and P-storage regions. When doping concentrations of two storage regions are equal to each other at 1018 cm−3, 2-T TRAM exhibits the longest T ret of 100 ms and the lowest impact ionization of the device can suppress various reliability issues such as hot carrier injection and junction degradation. Although T ret of 2-T TRAM can be reduced from 100 ms to 1.5 ms due to decreased read voltage with operating temperature rising from 300 K to 360 K, T ret can be further improved to >10 s by applying standby voltage ( V standby). The effective way to set minimum V standby is presented using the I A- V A characteristics with 1000-s fall time. Moreover, the optimal V standby is set to 0.60 V by considering disturbance in array operation. Consequently, the proposed design and operation guidelines can provide a pathway to realize nanoscale 2-T TRAM for capacitor-less 4F2 1T DRAM technology.

Sharp Logic Switch Based on Band Modulation

The capability of Z2-FET (Zero Impact Ionization and Zero Subthreshold Slope FET) to operate as a sharp logic switch is demonstrated in advanced FD-SOI (Fully Depleted SOI) technology. The operation mechanism is band-modulation which enables remarkable DC performance in terms of ON/OFF current ratio and sharp switch (~1 mV/decade). Z2-FETs have successfully been used for ESD protection and capacitorless DRAM memory, but the presence of an inherent hysteresis has handicapped so far logic applications. However, this letter shows that fast pulses on the gate result in hysteresis-free switching: the device turns ON and OFF at same gate bias. The sharpness of the switch depends on device parameters, bias and speed of operation. Systematic experiments compare the performance of Z2-FETs with dual or single ground-planes.

Characterization of a Capacitorless DRAM Cell for Cryogenic Memory Applications

A partially depleted silicon-on-insulator MOSFET is analyzed over a wide temperature range from 380K to 80K to characterize memory performance at cryogenic temperatures and verify its feasibility as a cryogenic memory cell. In the Shockley-Read-Hall theory, the generation–recombination rate decreases with decreasing temperature, therefore, the retention properties of the capacitorless single transistor DRAM cell are greatly improved as temperature decreases. The static and dynamic retention times increase sharply as temperature decreases. The dynamic retention time reaches up to ~3.5 s at 80K, which is ~104 times larger than that at 300K. In addition, as the temperature decreases, the current sensing margin also increases more than 2.5 times at 80K ( $\sim 11~\mu \text{A}$ ) compared to that at 300K, due to the improved dynamic retention characteristics and the increased transconductance.

Analysis of operation characteristics of junctionless poly-Si 1T-DRAM in accumulation mode

Capacitorless DRAM (1T-DRAM) is considered to be a promising candidate to replace conventional 1T-1C DRAM which is facing a scaling limit. 1T-DRAM with a poly-Si body has attracted much attention specifically for its simple SOI fabrication and stackable memory which allow for ultrahigh density. A single crystal silicon-based junctionless (JL) transistor is unsuitable for a 1T-DRAM cell because the transistor’s body is too thin to have a storage region and its junction barrier is too low to store holes. In contrast, a JL transistor with a thin poly-Si body can be used as a 1T-DRAM cell because it uses a grain boundary as its charge storage region instead of a floating body. We carried out intensive simulations of JL transistors with poly-Si body and confirmed the possibility of using a JL structure as a poly-Si 1T-DRAM cell. In addition, we analyzed the memory mechanism and characteristics of this structure.

A Gated Diode DRAM Cell for Improved Power and Speed

In this paper performance analysis of Gated diode based Dynamic Random Access Memory (GD-DRAM) cell is compare with capacitor based DRAM cell in terms of average power dissipation, propagation delay, read access time and write access time at 250nm technology. The GD-DRAM is also referred as capacitorless DRAM. This gated diode stored data in DRAM which is an alternative solution to capacitor. This gated diode DRAM shows cutback in leakage and access time as compared to capacitor based DRAM. A gated diode is formed by shorting two terminal of MOS transistor i.e. source and drain. When the voltage Vgs is higher than knee voltage Vth; then data get stored on it. Nowadays dynamic random access memory is highly attracting market as compared static RAM because of its high package density, low cost and small area. In this paper this gated diode also resolves the issue of fabrication of capacitor in conventional DRAM cell. The major problem associated with DRAM is power dissipation. The above cells were designed and simulated in Tanner EDA tool and their results were analyzed at 250μm technology. Here we investigated that gated diode based DRAM has superior performance in terms of read time, write time and average power dissipation.

Investigation of thin gate-stack Z2-FET devices as capacitor-less memory cells

Thin-oxide Z2-FET cells operating as capacitor-less DRAM devices are experimentally demonstrated. Both the retention time and memory window demonstrate the feasibility of implementing this cell in advanced 28 nm node FDSOI technology. Nevertheless a performance drop and higher variability with respect to thicker oxide Z2-FET cells are observed.