Temperature Capacitance-voltage Research Articles

Impact of the Buffer/Absorber Interface on the Metastability of Fill Factor Temperature Coefficients in CIGSSe Solar Cells

AbstractThe metastable behavior of the fill factor temperature coefficient (βFF,rel) in Cu(In,Ga)(S,Se)2 solar cells is investigated for absorbers with a different Ga content in the front surface, and for different buffer materials. The buffer/absorber interface region is suggested to be the location which causes the metastability in βFF,rel. Temperature dependent current–voltage curves, light‐biased external quantum efficiency, and low temperature capacitance–voltage measurements are performed to characterize the electrical properties and metastable defects in the investigated solar cell devices. The presence of Ga in the absorber front surface, together with the buffer layer material plays a significant role in the metastable behavior. Additionally, energy dispersive X‐ray spectroscopy indicates that the InxSy buffer layers allow for elemental interdiffusion from absorbers with a Ga‐richer front surface, whereas a Zn(O,S) buffer shows to be rather resilient to atomic diffusion. The elemental interdiffusion between the buffer and absorber layers is proposed to be the cause of the defects causing the observed βFF,rel metastability.

Voltage-Tunable Quantum-Dot Array by Patterned Ge -Nanowire-Based Metal-Oxide-Semiconductor Devices

Semiconductor quantum dots (QDs) are being regarded as the primary unit for a wide range of advanced and emerging technologies including electronics, optoelectronics, photovoltaics and biosensing applications as well as the domain of q-bits based quantum information processing. Such QDs are suitable for several novel device applications for their unique property of confining carriers 3-dimensionally creating discrete quantum states. However, the realization of such QDs in practice exhibits serious challenge regarding their fabrication in array with desired scalability and repeatability as well as control over the quantum states at room temperature. In this context, the current work reports the fabrication of an array of highly scaled Ge-nanowire (radius ~25 nm) based vertical metal-oxide-semiconductor devices that can operate as voltage tunable quantum dots at room temperature. The electrons in such nanowire experience a geometrical confinement in the radial direction, whereas, they can be confined axially by tuning the applied bias in order to manipulate the quantum states. Such quantum confinement of electrons has been confirmed from the step-like responses in the room temperature capacitance-voltage (C-V) characteristics at relatively low frequency (200 kHz). Each of such steps has observed to encompass convolution of the quantized states occupying ~6 electronic charges. The details of such carrier confinement are analyzed in the current work by theoretically modeling the device transport properties based on non-equilibrium Green's function (NEGF) formalism.

Current–Voltage, Capacitance–Voltage–Temperature, and DLTS Studies of Ni|6H-SiC Schottky Diode

Current–Voltage, Capacitance–Voltage–Temperature, and DLTS Studies of Ni|6H-SiC Schottky Diode

Theoretical and experimental investigations of barrier height inhomogeneities in poly-Si/4H-SiC heterojunction diodes

p-Si/4H-SiC heterojunction diodes are realized by sputter-deposition of the Si top contact and subsequent post-deposition annealing at either 900 °C or 1000 °C. The high Schottky barrier height (SBH) of this junction architecture of around 1.65 V is ideal to analyze SBH inhomogeneities present in most Schottky- and heterojunctions. Current-voltage-temperature (IVT) and capacitance-voltage-temperature (CVT) measurements are conducted in a wide temperature range from 60 K up to 460 K while applying standard techniques for SBH extraction. Strong deviations from ideal IV characteristics are present especially at lowest temperatures when assuming a homogenous SBH. Additionally, the extracted SBHs at low temperatures differ a lot between the two methods, indicating the presence of low barrier conduction paths. The presence of at least two distinct SBH inhomogeneities is found, which are labeled as ‘intrinsic’ and ‘extrinsic’. Next, the Tung model was applied to fit the measured IVT data using a discretized Gaussian distribution of patch parameters to account for spreading resistance effects. By using multiple Gaussian distributions, excellent fitting results were achieved, giving the density values of the different patches and a background barrier height from the IVT data, which are in excellent agreement with the CVT data over a wide temperature range of 400 K.

High electron density β-(Al0.17Ga0.83)2O3/Ga2O3 modulation doping using an ultra-thin (1 nm) spacer layer

This report discusses the design and demonstration of β-(Al0.17Ga0.83)2O3/Ga2O3 modulation doped heterostructures to achieve high sheet charge density. The use of a thin spacer layer between the Si delta-doping and the heterojunction interface was investigated in a β-(AlGa)2O3/Ga2O3 modulation doped structure. It is shown that this strategy enables a higher two-dimensional electron gas (2DEG) sheet charge density up to 4.7 × 1012 cm−2 with an effective mobility of 150 cm2/V s. The presence of a degenerate 2DEG channel was confirmed by the measurement of a low temperature effective mobility of 375 cm2/V s and the lack of carrier freeze out from low temperature capacitance voltage measurements. The electron density of 4.7 × 1012 cm−2 is the highest reported 2DEG density obtained without parallel conducting channels in a β-(AlxGa(1−x))2O3/Ga2O3 heterostructure system.

Co/aniline blue/silicon sandwich hybrid heterojunction for photodiode and low-temperature applications

The temperature dependence of the current–voltage and room temperature capacitance–voltage measurements of Co/aniline blue/ n-Si sandwich-type rectifying device was investigated.Furthermore, the effects of the illumination on the current–voltage measurements were tested with 100 mW/cm2 light intensity, and it was seen that Co/aniline blue/ n-Si sandwich-type device showed a clear response to illumination, and it may be a candidate for solar cells or photodiode applications. The rectifying device parameters, such as the barrier height (Ф), the ideality factor ( n), the rectification ratio, and the series resistance ( Rs), were obtained as a function of temperature using thermionic emission, Cheung function, and Norde function. The interface state densities versus energy were obtained. The Richardson constant ( A*) obtained from the In( Io/ T2) versus 1000/ T plot was much less than the theoretical value for n-Si. The mean Schottky barrier height[Formula: see text] and the standard deviation ( σo) were calculated using the apparent Schottky barrier height Фap versus 1/2 kT plot. So, it has been found to be 1.08 eV and 0.15 V (260–460 K) and 0.79 eV and 0.10 V (100–260 K), respectively. The results were discussed based on the presence of two Gaussian distributions of Фb potential in the contact area of Co/aniline blue/ n-Si/Al device.

Identifying of series resistance and interface states on rhenium/n-GaAs structures using C–V–T and G/ω–V–T characteristics in frequency ranged 50 kHz to 5 MHz

In this study, Re/n-GaAs with a native oxide layer based on metal–semiconductor (MS) structures were produced and then, the capacitance–voltage–temperature (C–V–T) and the conductance–voltage–temperature (G/ω–V–T) data of them were obtained in the frequency ranged 50 kHz to 5 MHz. Using the raw data, the electronic parameters was calculated by the developed LabVIEW-based program. Methodologically, the series resistance (Rs) values were calculated from the measured capacitance (Cm) and conductivity (Gm) values, while the interface state (Nss) values were obtained from using the combined high (CHF)–low (CLF) frequency capacitance method by Nicollian and Brews. Experimentally, the C values increased with a decreasing frequency, while decreased with increasing temperatures in the depletion and accumulation regions. On the other hand, G/ω values decreased with increasing frequency in forward and reverse bias regions. It can be attributed that, the C and the G/ω values are quite affected by the presence of the Rs and the Nss in the forbidden energy gap and a native oxide layer between M and S. The Rs–V–T curves have especially peaks in accumulation and depletion regions at low frequency values, whereas these peaks decreased at high frequencies. In addition, the Nss–V–T curves give peaks in the range of − 0.1 V to 0.7 V at variable temperatures and the Nss values decrease with increasing temperature and shift towards negative bias regions. Experimental results indicate that the Rs and Nss are important parameters and so, these parameters must be considered in sensor applications based on Re/n-GaAs structures.

C-DLTS interface defects in Al0.22Ga0.78N/GaN HEMTs on SiC: Spatial location of E2 traps

The purpose of this paper has focused on the investigation of the High electron mobility transistors AlGaN/GaN HEMTs based on SiC substrates by means of capacitance-voltage-temperature (C-V-T) and Deep Level Transient Spectroscopy (DLTS). The C-V analysis have been recorded in the 20–320 K temperature range and exhibit an increase in the pinch-off voltage by an amount of 300 mV once the temperature exceeds 200 K. A hysteresis phenomenon has been observed in the C-V spectra by sweeping the gate voltage Vgs forth and back between −5 and 0 V. This parasitic effect has identified to be related to trapping and detrapping mechanisms occurring in the GaN-HEMT device. DLTS results have proved the presence of two traps, labeled E1 and E2, with activation energies of 0.31eV and 0.525eV and capture cross sections of 3.86 × 10−18cm2 and 2.75 × 10−15cm2, respectively. The major E2 trap seems to be nitrogen anti-sites, possibly located in the buffer layer near to the interface AlGaN/GaN. It has been reported that there exists a good correlation betwixt the anomalies in C-V-T characteristics and DLTS measurements.

Temperature effects on the electrical characteristics of $$\mathrm{Al}/\mathrm{PTh}-\mathrm{SiO}_{2}/\mathrm{p\hbox {-}Si}$$ Al / PTh - SiO 2 / p - Si structure

The temperature-dependent current–voltage (\(I\text {--}V\)) and capacitance–voltage (\(C\text {--}V\)) characteristics of the fabricated Al/p-Si Schottky diodes with the polythiopene–SiO\(_{2}\) nanocomposite (\(\hbox {PTh--SiO}_{2}\)) interlayer were investigated. The ideality factor of \(\hbox {Al}/\hbox {PTh--SiO}_{2}/{p}\text {-Si}\) Schottky diodes has decreased with increasing temperature and the barrier height has increased with increasing temperature. The change in the barrier height and ideality factor values with temperature was attributed to inhomogeneties of the zero-bias barrier height. Richardson plot has exhibited curved behaviour due to temperature dependence of barrier height. The activation energy and effective Richardson constant were calculated as 0.16 eV and \(1.79 \times 10^{-8} \hbox {A\,cm}^{-2} \,\hbox {K}^{-2}\) from linear part of Richardson plots, respectively. The barrier height values determined from capacitance–voltage–temperature (\(C\text {--}V\text {--}T\)) measurements decrease with increasing temperature on the contrary of barrier height values obtained from \(I\text {--}V\text {--}T\) measurements.

Dielectric Properties of and Charge Transport in Columnar Microfibrous Thin Films of Parylene C

Parylene-C microfibrous thin films ( $\mu $ FTFs), grown using oblique-angle physicochemical vapor deposition, were examined for potential use as low-relative-permittivity (i.e., low- $\kappa $ ) interlayer dielectrics in integrated circuits and, more importantly, flexible electronics. These films were characterized using capacitance–voltage–temperature (CVT) and current–voltage–temperature experiments at different temperatures (ranging from 298 to 420 K) and frequencies (ranging from 1 kHz to 1 MHz). Field emission scanning electron microscopy revealed the Parylene C $\mu $ FTFs to be highly porous. Consequently, their $\kappa $ values are at least 20% lower than those of bulk Parylene C. The dependences of $\kappa $ on frequency and temperature suggest that molecular dipole oscillations are responsible for charge polarization in the $\mu $ FTFs. The dc leakage current in the $\mu $ FTFs at temperatures not exceeding 100 °C (~373 K) was found to arise from Poole–Frenkel (PF) emissionmechanism with a barrier energy of about 0.77 eV. Moreover, when fitted to the PF model, the experimental data yielded high-frequency values $\kappa _{\infty }$ of $\kappa $ in agreement with those obtained from CVT experiments, thus confirming our identification of PF as themajor responsiblemechanism and confirming the low- $\kappa $ characteristic of microfibrous Parylene C. The ac current transport in the $\mu $ FTFs was found attributable to small-polaron-tunneling hopping conduction and characterized by the power law $ \omega ^{s}$ , with $s\in [{0.082,0.85}]$ increasing with temperature. AC conduction in the $\mu $ FTFs is temperature-activated with an activation energy that decreases from 0.020 to 0.012 eV as frequency increases from 1 kHz to 1 MHz.

Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance–voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

Electrical behavior of CdS/Al Schottky barrier diode at low temperatures

In this study CdS/Al Schottky barrier diode (SBD) was fabricated by depositing Al metal dot of area 0.001256 cm2 on spray deposited CdS thin film. Current-voltage characteristics of CdS/Al SBD were measured at different temperatures ranging 303-193 K and were analysed to understand the effect of temperature on the electrical parameters of the diode. Both forward and reverse current was found to decrease with the decrease of temperature. The series resistance (RS) and ideality factor (n) were found to increase for the decrease of temperature. The barrier height (ϕb), and Richardson constant (A∗∗) are found to be equal to 0.128 eV and 8.94 x 10-5 AK-2cm-2, respectively. Room temperature capacitance-voltage (C-V) measurement was used to find the carrier concentration (NA) and built in voltage (Vbi) of the CdS/Al Schottky barrier diode. Carrier concentration and the built in potential were found to be 1.84 x 1023 m-3 and 0.393 V, respectively. Schottky barrier height (ɸb) was also measured from C-V characteristics at room temperature and is equal to 0.399 eV. The value of barrier height obtained from low temperature I-V measurements was smaller than that obtained from C-V characteristics. This can be due to the existence of an interface layer or due to spatial inhomogeneities at the CdS/Al contact.

Current–voltage–temperature and capacitance–voltage–temperature characteristics of TiW alloy/p-InP Schottky barrier diode

We systematically characterize TiW alloy/p-InP Schottky barrier diode using current–voltage (I–V) and capacitance–voltage (C–V) measurements for different temperatures from 300 K to 400 K. The electrical parameters such as barrier height (Φb0) and ideality factor (n) have been obtained from the thermal emission (TE) theory. Φb0 increases and n decreases with the increasing of temperature. The temperature dependency of barrier characteristics is interpreted by TE theory assuming a Gaussian distribution of the barrier heights according to the inhomogeneous model. The mean barrier height Φ¯b0(T=0K)=1.09V and standard deviation σ0 = 135 mV are obtained by plotting Φb0 versus 1/2kT, indicating the Gaussian distribution of the barrier heights. The value of extracted Richardson constant A* is 56.2504 Acm−2 K−2, which is in good agreement with the theoretical value. All these obtained results show that the carrier transport process can be modeled by the TE theory. In addition, the C–V characteristics are analyzed by taking into account series resistance (Rs). The extracted interface states distribution shows the increase of the interface state density from midgap towards the top of the valence band.

Device application of AgGa0.5In0.5Se2 thin films deposited by thermal sequential stacked layer method

An In/n-AgGa0.5In0.5Se2/p-Si/Al heterostructure was produced by thermal sequential stacked layer deposition method and the device characteristics were investigated. The compositional analysis showed that the depositions of the intended stoichiometric composition of AgGa0.5In0.5Se2 structure were obtainable by controlling and providing the necessary deposition conditions during the deposition processes. By means of the room temperature Hall effect and transmission measurements, the carrier concentration and optical band gap values were determined as cm−3 and 1.65 eV, respectively. In addition, temperature-dependent current-voltage (I–V) and the room temperature capacitance-voltage (C–V) measurements of this heterostructure were carried out. The rectification factor was obtained as about 104 at 1.20 V for all sample temperatures. Depending on the change in the temperature, the series and shunt resistances were calculated as 101 and 106 Ω, respectively. The studies on the current transport mechanisms showed that there were two different mechanisms at two different voltage regions: tunneling enhanced recombination mechanism in the voltage range of 0.08 and 0.30 V and the space charge limited current mechanism in the voltage range of 0.30 and 0.60 V. The barrier height, built-in potential and interface states density of the deposited heterostructure were also calculated and discussed.

Analysis of Temperature-Dependent Electrical Characteristics of n-ZnO Nanowires (NWs)/p-Si Heterojunction Diodes

This paper presents the electrical characteristics of n-zinc oxide (ZnO) nanowires (NWs)/p-Si (100) heterojunction diodes fabricated by the oxidation of thermally deposited metallic Zn on Al:ZnO-coated p-Si 〈1 0 0〉 substrates. The electrical parameters of the n-ZnO NWs/p-Si diodes have been estimated by using the room temperature capacitance-voltage (C-V) and temperature-dependent current-voltage (I-V) characteristics of the heterojunction. The carrier concentration of the ZnO NW film and the barrier height of the diode estimated from the C-V characteristics at room temperature are 1.54 × 10 15 cm -3 and 0.75 eV, respectively. The thermionic emission model was used to analyze the temperature-dependent measured I-V characteristics to estimate the parameters of the diode. The estimated values of the barrier height and ideality factor at room temperature were 0.715 eV and 2.13, respectively. The spatial barrier inhomogeneity was included in the aforementioned analysis by assuming a Gaussian distribution for the barrier height at the n-ZnO NWs/p-Si heterojunction. The Richardson constant A* of ZnO was found to be increased from a relatively low value of 9.75 ×10 - 8 A ·cm - 2 ·K - 2 to a more realistic value of 49A ·cm - 2 ·K - 2 after incorporating the barrier inhomogeneity phenomenon in the aforementioned analysis.

Analysis of the Temperature Dependence of the Capacitance–Voltage and Conductance–Voltage Characteristics of Au/TiO2(rutile)/n-Si Structures

The capacitance–voltage–temperature (C–V–T) and the conductance/angular frequency–voltage–temperature (G/ω–V–T) characteristics of Au/TiO2(rutile)/n-Si Schottky barrier diodes (SBDs) were investigated over the temperature range from 200 K to 380 K by considering the series resistance effect. Titanium dioxide (TiO2) was deposited on n-type silicon (Si) substrate using a direct-current (DC) magnetron sputtering system at 200°C. To improve the crystal quality, the deposited film was annealed at 900°C to promote a phase transition from the amorphous to rutile phase. The C−2 versus V plots gave a straight line in the reverse-bias region. The main electrical parameters, such as the doping concentration (ND), Fermi energy level (EF), depletion layer width (WD), barrier height (фCV), and series resistance (RS), of Au/TiO2(rutile)/n-Si SBDs were calculated from the C–V–T and the G/ω–V–T characteristics. The obtained results show that фCV, RS, and WD values decrease, while EF and ND values increase, with increasing temperature.

Analysis of temperature dependent electrical properties of Au/perylene-diimide/n-Si Schottky diodes

The electrical properties of Au/perylene-diimide/n-Si Schottky diode have been determined by means of current–voltage measurements in the temperature range of 75–300K. These devices showed good rectifying behavior and the temperature dependence of the current–voltage characteristics could be explained by thermionic emission mechanism. The experimental values of barrier height and ideality factor for device have been calculated as 0.168eV and 7.63eV at 75K and 0.690eV and 1.57eV at 300K, respectively. The fabricated Schottky diode shows non-ideal current–voltage behavior and so it is thought that the device have a metal-interface layer-semiconductor configuration. In addition to current–voltage measurements, the room temperature capacitance–voltage characteristics of Au/perylene-diimide/n-Si devices were also investigated. The barrier height value of 1.051eV obtained from the capacitance–voltage measurements was found to be higher than that of 0.690eV obtained from the current–voltage measurements at room temperature. Furthermore, the energy distribution of the interface state density determined from current–voltage characteristics increases exponentially with bias from 8.01×1012eV−1cm−2 at (Ec−0.666)eV to 5.86×1013eV−1cm−2 at (Ec−0.575)eV.

The modification of Schottky barrier height of Au/p-Si Schottky devices by perylene-diimide

Perylene-diimide (PDI) thin film was fabricated by spin coating method on p-Si single-crystal substrate to prepare Au/PDI/p-Si Schottky device. The electrical properties of the Au/PDI/p-Si Schottky device were investigated by current-voltage (I–V) measurements in the temperature range 80–300 K and room temperature capacitance-voltage (C–V) measurement. Results showed a rectification behavior. Junction parameters such as ideality factor (n), barrier height (ϕB0), series resistance (Rs) interface state density (Nss), built-in potential (Vbi), carrier concentration (NA), and the width of the depletion layer (WD) were obtained from the I–V and C–V measurements. The values of ideality factor (n) and barrier height (BH) for the Au/PDI/p-Si structure from the I–V measurements were obtained as 1.77 and 0.584 eV at 300 K, 7.78 and 0.176 eV at 80 K, respectively. It was seen that the BH value of 0.584 eV calculated for the Au/PDI/p-Si structure was significantly larger than the value of 0.34 eV of conventional Au/p-Si Schottky diodes at room temperature. Thus, modification of the interfacial potential barrier for Au/p-Si diodes has been achieved using a thin interlayer of the peryleen-diimide organic semiconductor; this has been ascribed to the fact that the peryleen-diimide interlayer increases the effective barrier height because of the interface dipole induced by passivation of the organic layer. Furthermore, the energy distribution of the interface state density determined from I–V characteristics increases exponentially with bias from 1.11 × 1012 eV−1 cm−2 at (0.556−Ev) eV to 11.01 × 1013 eV−1 cm−2 at (0.449−Ev) eV.

Deep centers and persistent photocapacitance in AlGaN/GaN high electron mobility transistor structures grown on Si substrates

Deep trap spectra in AlGaN/GaN high electron mobility transistor structures grown on Si by metalorganic chemical vapor deposition show four major electron traps (Ec—0.15, 0.29, 0.40 and 0.76 eV) in the AlGaN barrier/interface region and three (Ec—0.18, 0.27 and 0.45 eV) in the undoped GaN buffer region. The presence of a high density of deep acceptor traps was observed in the AlGaN barrier region, as determined by hysteresis in low temperature capacitance-voltage (C-V) characteristics. The spectral dependence of persistent photocapacitance shifts showed two optical thresholds of 1.5 V and 3.1 eV, with the second being specific to structures grown on Si substrates. Comparison of results obtained on transistors and on large-area Schottky diodes prepared on heterostructures from which transistors are fabricated show that measurements on test large-area diodes are representative of the main characteristics important for transistor performance.

Transport-mechanism analysis of the reverse leakage current in GaInN light-emitting diodes

The reverse leakage current of a GaInN light-emitting diode (LED) is analyzed by temperature dependent current–voltage measurements. At low temperature, the leakage current is attributed to variable-range-hopping conduction. At high temperature, the leakage current is explained by a thermally assisted multi-step tunneling model. The thermal activation energies (95–162 meV), extracted from the Arrhenius plot in the high-temperature range, indicate a thermally activated tunneling process. Additional room temperature capacitance–voltage measurements are performed to obtain information on the depletion width and doping concentration of the LED.