Capacitance-voltage Techniques Research Articles

Suppression of irradiation effect on electrical properties of silicon diodes by iron in p-silicon

Radiation-hardness of silicon (Si) has been the subject of interest due to the damage of the material-based detectors during and after operation. In this work, the effects of 4 MeV proton-irradiation on the electrical properties of devices fabricated on undoped and Fe-doped p-Si were investigated using current-voltage (I-V) and capacitance-voltage (C-V) techniques. A decrease in current and capacitance is less pronounced and the conduction mechanism remains unchanged on Fe-doped p-Si diode after proton-irradiation. This insignificant change of electrical parameters of the Fe-doped diode after proton-irradiation indicates the suppression of the radiation effect by Fe in Si. The electrical properties of the diode are less dependent on incident radiation, because of the possible prevention of further dislodgement of atoms by incident radiation. As a result, the material becomes resistant to radiation damage, making the electrical properties of the diode independent of incident radiation due to Fe atoms in Si. As a result of the ohmic behaviour displayed by the Fe-doped Si diode, it is possible that in Si, Fe is responsible for generation-recombination (g-r) centres, which are defect levels positioned at the middle of the energy gap of Si. The possibility of these defects being responsible for the suppression of the radiation effect is explained in this work, making Fe a promising dopant to improve the radiation-hardness of Si.

Investigation of Low Energy Electron Irradiated SiO2 Based MOS Devices by Capacitance-Voltage and Thermally Stimulated Current Techniques

Investigation of Low Energy Electron Irradiated SiO2 Based MOS Devices by Capacitance-Voltage and Thermally Stimulated Current Techniques

Fabrication and characterization of heavily doped n-type GaAs for mid-infrared plasmonics

N-type doping in GaAs is a self-limited process, rarely exceeding a carrier concentration level of 1019 cm−3. Here, we investigated the effect of intense pulsed light melting on defect distribution and activation efficiency in chalcogenide-implanted GaAs by means of positron annihilation spectroscopy and electrochemical capacitance–voltage techniques. In chalcogenide-doped GaAs, donor–vacancy clusters are mainly responsible for donor deactivation. Using positrons as a probe of atomic scale open volumes and DFT calculations, we have shown that after nanosecond pulsed light melting the main defects in heavily doped GaAs are gallium vacancies decorated with chalcogenide atoms substituting As, like VGa–nTeAs or VGa–nSAs. The distribution of defects and carriers in annealed GaAs follows the depth distribution of implanted elements before annealing and depends on the change in the solidification velocity during recrystallization.

Porous PZT Films: How Can We Tune Electrical Properties?

Porous ferroelectric lead zirconate titanate (PZT) films are a promising material for various electronic applications. This study focuses on understanding how the structure-directing agent, polyvinylpyrrolidone, can alter the structure and electrical properties of porous PZT films prepared through chemical solution deposition. Films with various porosities of up to ~40 vol.% and pore connectivities from 3-0 to 3-3 were prepared and studied by capacitance-voltage, dielectric hysteresis, transient current, photocurrent, and local current techniques. We have found that a linear decrease in material volume in a porous film is not the only factor that determines film properties. The creation of new internal grain boundaries plays a key role in changing electrical properties. This research expands the understanding of physical phenomena in porous ferroelectric films and may facilitate the development of new materials and devices.

Effect of Gadolinium on Electrical Properties of Polyethyleneimine Functionalized and Nitrogen‐Doped Graphene Quantum Dot Nanocomposite Based Diode

AbstractCarbon, especially graphene quantum dots (GQDs) based electronics have become an attractive technology in recent years. The controlled modification of the electrical and optoelectronic properties of GQDs by physical/chemical processes or synthetic methods may lead to new applications. Gadolinium‐doped polyethyleneimine (PEI) functionalized and nitrogen‐doped graphene quantum dots (GdNPs‐PEI@N‐GQDs) are synthesized by a hydrothermal method to determine how doping carbon‐based materials with Gd alters the electrical properties of the structure. The electrical properties of the GdNPs/PEI@N‐GQDs nanocomposite‐based diode are investigated using the current–voltage (I–V) technique and the capacitance and conductance voltage (C–V & G/ω–V) technique at 300 K in the frequency range of 0.5 to 500 kHz at ± 5 V. The rectification ratio (RR) is found to be 14 at a voltage of ±5 V. The rectifying behavior of the diode changes to an ohmic behavior after doping with Gd, compared to the Gd‐free PEI@N‐GQDs sample (2.8 × 104 at ±5 V). The results are expected to have an impact on the understanding of carbon‐based electronics technology.

Optimizing Non-Contact Doping and Electrical Defect Metrology for Production of SiC Epitaxial Wafers

The recently introduced corona charge non-contact capacitance-voltage technique, CnCV, is analyzed considering the production needs of epitaxial SiC wafers. The interfering mechanism of charge dissipation on fresh epitaxial 4H-SiC is identified as surface diffusion and is effectively eliminated by optimized ultraviolet pretreatment (UVPT). It is shown that optimized UVPT increases the CnCV dopant measurement voltage range and the depth of profiling. Concurrent UVPT and measurement provides a practical solution for improving throughput for multiple wafers. Electrical defect mapping shows that UVPT reduces the effective defect size. This will be helpful to avoid defects in patterns used for CnCV dopant measurements.

Structural and electronic characterization of silicon based MIS contact by xanthene dye molecules (Erythrosine B)

The effect of erythrosine B (ERY) organic material as an interface layer on the electronic characteristics of the Al/p-Si junction is examined in the present work. AFM, NMR, UV–Vis and FTIR measurements have been conducted on the ERY dye molecule. The ERY film on the surface of the substrate is coated with nanoparticles, according to the surface analysis performed using the AFM technique. The basic diode parameters of Al/p-Si and Al/ERY/p-Si junctions were measured by utilizing current-voltage (I–V) and capacitance-voltage (C-V) techniques. The junctions with and without organic interfacial layers were found to have ideality factors of 1.931 and 1.925, respectively. For MS and MIS contacts, the estimated values of barrier height were 0.592 eV and 0.937 eV, respectively. Additionally, the series resistances for the MS and MIS structures by utilizing Norde function, were determined to be 0.14 kΩ and 322.85 kΩ, respectively. In addition, the reverse bias 1/C2-V characteristics were used to analyze the barrier height values and compare the findings to those from I-V method. The experimental findings demonstrated that the Al/ERY/p-Si MIS diode has a barrier height that is remarkably greater than that of the reference Al/p-Si junction. Placement of the ERY dye interlayer between a metal and a semiconductor could enhance and regulate the performance and characteristic of these types of junctions.

Carmoisine azo dye-modified Al/p-Si junction

This study investigates the impact of a Carmoisine azo dye layer on electronic transport at the p-silicon/Al interface. The morphology of the Carmoisine azo layer is characterized using atomic force microscopy (AFM). Various spectroscopic measurements, including nuclear magnetic resonance (NMR), ultraviolet–visible (UV–Vis), and Fourier transform infrared (FTIR) spectroscopy, are employed to analyze the Carmoisine dye molecule. The direct and indirect band gap values of the Carmoisine dye molecule, prepared in methanol solvent, are determined to be Eg,1 = 2.15 eV and 2.06 eV (D band) and Eg,2 = 3.54 eV and 3.35 eV (C band), respectively. Results indicate that the Carmoisine film on a glass slide consists of non-homogeneous microstructures, with a surface roughness of 16.76 nm. A spin coater is used to form an Al/Carmoisine/p-Si device, which is a cost-effective and readily scalable approach for creating semiconductor films. The basic contact parameters of the Al/p-Si and Al/Carmoisine/p-Si contacts are measured using current-voltage (IV) and capacitance-voltage (CV) techniques. The Al/Carmoisine/p-Si device exhibits good rectifying behaviour, with an ideality factor value of 1.547, indicating that the Carmoisine azo dye used as the interface material enhances the junction's performance and reduces the ideality factor. Barrier height (BH) parameters are calculated to be 0.770 eV, 0.733 eV, and 0.799 eV using the lnI-V, Cheung, and Norde techniques, respectively. The interfacial dipole created by passivation of the film causes the Carmoisine interlayer to raise the BH, resulting in an improved interface region for Al/p-Si structures. The extracted interfacial level concentration (Nss) of the Al/Carmoisine/p-Si junction is lower than that of the Al/p-Si contact, indicating that the Carmoisine dye molecule reduces the Nss value. Furthermore, the reverse bias 1/C2-V characteristic is employed to analyze the barrier height values and compare the findings to those from the IV method. The results show that the thin Carmoisine azo dye layer decreases leakage current and defect-trapped charge density, enhancing the reliability and performance of the devices. This study contributes a new organic electronic material, Carmoisine dye, to the literature on semiconductor devices.

Extraction of effective mobility of In0.8Ga0.2As/In0.52Al0.48As quantum well high-electron-mobility transistors on InP substrate

In this work, we explored the effective mobility of In-rich InxGa1-xAs/In0.52Al0.48As (x > 0.53) quantum well (QW) high-electron-mobility transistors (HEMTs) on an InP substrate. Historically, the carrier transport properties of these types of devices have been assessed mostly using their Hall mobility, not using the effective mobility, mainly because the excessive gate leakage current degrades and contaminates their measured capacitance voltage (CV) characteristics. However, our recent studies on these devices achieved a significant reduction in the gate leakage current, which motivated us to explore their effective mobility. In this work, therefore, we used a conventional split CV technique to determine and analyze the effective mobility of In0.8Ga0.2As/In0.52Al0.48As QW HEMTs. We also attempted to model the extracted effective mobility by considering three different scattering mechanisms—Coulombic scattering, phonon scattering and surface-roughness scattering— under the guidance of Matthiessen’s rule.

(Invited) ALD HfO2/β-Ga2O3 Reliability for Future Power Devices

The ultra-wide bandgap (UWBG) semiconductor, β-gallium oxide, has shown great potential in power devices due to its excellent electrical properties and availability of high-quality single-crystalline substrates. Significant progress has been made in the development of β-Ga2O3 metal-oxide-semiconductor (MOS) devices, but further progress will require optimization of the gate-dielectric interface. In this talk, I will describe the investigation of HfO2 dielectric reliability on β-Ga2O3 for future power devices. I fabricated β-Ga2O3 (010) MOS capacitors with atomic layer deposited (ALD) HfO2 and used capacitance-voltage (C-V) and current density-voltage (J-V) techniques to analyze the electrical reliability of ALD HfO2/β-Ga2O3 MOSCAPs. Positive bias stress measurements indicated that HfO2/β-Ga2O3 MOSCAPs are more susceptible to charge trapping at lower electric stress fields compared to HfO2/Si MOSCAPs, likely due to the smaller conduction band offset between HfO2 and β-Ga2O3. Initial flatband voltage shifts were observed for C-V sweeps of HfO2/β-Ga2O3 MOSCAPs, showing the significance of border traps within the dielectric. The lack of mobile holes in the β-Ga2O3 impedes the recombination of these trapped charges in the dielectric while the MOSCAP is in depletion. We observed full recovery from stress-induced charge trapping in the HfO2/β-Ga2O3 MOSCAPs upon deep ultra-violet illumination. The negative valence band offset between the dielectric and semiconductor allows the recombination of photo-generated holes with the trapped dielectric charges [1]. Because many fabrication steps require high temperature processing, we also investigated the thermal reliability of the ALD HfO2/β-Ga2O3 (010) interface. Negligible Ga atom diffusion was observed in secondary ion mass spectrometry (SIMS) depth profiles for anneals at temperatures up to 850°C in N2 environment for 10 minutes. Significant Ga diffusion into the HfO2 layer was observed upon annealing at 900°C, resulting in a severely degraded MOS structure. Additional analysis was performed to investigate the impact of high temperature processing on the MOS electrical characteristics [2].H.N.M was supported by a National Science Foundation Graduate Research Fellowship under Grant No. DGE 1256260. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation. Portions of this work were performed at the Lurie Nanofabrication Facility and J. D. Hanawalt X-Ray MicroAnalysis Laboratory, which are supported by the College of Engineering at the University of Michigan.[1] H. N. Masten, J. D. Phillips, and R. L. Peterson, “Charge trapping and recovery in ALD HfO2/β-Ga2O3 (010) MOS capacitors,” Semicond. Sci. Technol., vol. 36, no. 4, p. 04LT01, Mar. 2021, doi:10.1088/1361-6641/abe880.[2] H. N. Masten, J. D. Phillips, and R. L. Peterson, “Effects of High Temperature Annealing on the Atomic Layer Deposited HfO2 /β-Ga2O3 (010) interface,” Journal of Applied Physics, Accepted.

(Invited, Digital Presentation) Exploring the Potential and Limits of Gallium Oxide Electronics: In-Situ Dielectrics, Heterointegration and High-k Field Plates

The intrinsic properties of beta phase Gallium Oxide such as the high breakdown field strength makes it a very attractive material for next generation electronics. Rapid progress has been made over the last few years in pushing the performance of Gallium Oxide-based vertical Schottky diodes and lateral field effect transistors and impressive figure of merit has been reported. However, the device performance is farther from the expected performance based on intrinsic properties. Exploration of the intrinsic potential is rather limited by several factors such as the quality of dielectrics and dielectric/semiconductor interfaces, electric field management challenges due to the lack of p-type material, to name a few. In this work, we will highlight a few approaches to tackle some of these challenges.(1) In-situ dielectrics: High quality dielectric-semiconductor interfaces are critical for reliable high-performance transistors. We report in situ metal–organic chemical vapor deposition of Al2O3 on β-Ga2O3 as a potentially better alternative to the most commonly used atomic layer deposition (ALD) [1]. The growth of Al2O3 is performed in the same reactor as Ga2O3 using trimethylaluminum and O2 as precursors without breaking the vacuum at a growth temperature of 600 °C. The fast and slow near interface traps at the Al2O3/β-Ga2O3 interface are identified and quantified using stressed capacitance–voltage (CV) measurements on metal oxide semiconductor capacitor (MOSCAP) structures. The density of shallow and deep level initially filled traps (Dit) are measured using ultraviolet-assisted CV technique. The average Dit for the MOSCAP is determined to be 6.4 × 1011 cm−2eV−1. The conduction band offset of the Al2O3/ Ga2O3 interface is also determined from CV measurements and found out to be 1.7 eV which is in close agreement with the existing literature reports of ALD Al2O3/Ga2O3 interface. The current–voltage characteristics are also analyzed and the average breakdown field is extracted to be approximately 5.8 MV cm−1.(2) Field management using High-K field Plate: We report a vertical (001) β-Ga2O3 field-plated (FP) Schottky barrier diode (SBD) with a novel extreme permittivity dielectric field oxide [2] . A thin drift layer of 1.7μm was used to enable a punch-through (PT) field profile and very low differential specific on-resistance (Ron-sp) of 0.32 mΩ-cm2. The extreme permittivity field plate oxide facilitated the lateral spread of the electric field profile beyond the field plate edge and enabled a breakdown voltage (Vbr) of 687 V. The edge termination efficiency increases from 13.2%for non-field plated structure to 61% for high permittivity field plate structure. The high permittivity field plated SBD demonstrated a record high Baliga's figure of merit (BFOM) of 1.47 GW/cm2 showing the potential of Ga2O3 power devices for multi-kilovolt class applications.(3) p-type III-nitride/Ga2O3 integration for field management: This work presents the simulation and analysis of a novel Ga 2 O 3 vertical Schottky diode with three different guard ring (GR) configurations to reduce the peak electric field at the metal edges [3]. Highly doped p-type GaN, p-type nonpolar AlGaN, and polarization-doped graded p-AlGaN are simulated and analyzed as the GR material, which forms a heterojunction with the Ga 2 O 3 drift layer. GR with nonpolar graded p-AlGaN with a bandgap larger than Ga 2 O 3 is found to show the best performance in terms of screening the electric field at the metal edges. The proposed GR configuration is also compared with a reported Ga 2 O 3 Schottky diode with no GR and a structure with high-resistive nitrogen-doped GR. The optimized design is predicted to have a breakdown voltage as high as 6.2 kV and a specific ON-resistance of 3.55 mΩ-cm 2, which leads to an excellent power figure of merit of 10.8 GW/cm 2.The approaches discussed here can offer a pathway towards understanding the true potential and limitations of Gallium Oxide for extreme electric field devices. We acknowledge funding support from NSF (DMR-1931652) and the AFOSR MURI program (FA9550-18-1-0507).

Morphological and electrical properties of Ag/p-type indium phosphide MIS structures with malachite green organic dyes

Malachite Green (MG) organic dye thin film was prepared by simple drop casting method. Microstructural property of MG layer was investigated by Scanning Electron Microscopy (SEM). SEM image indicated that MG organic thin layer was formed from nanoclusters. Later, it was fabricated Ag/Malachite Green(MG)/p-InP diodes by drop cast method. The barrier height (BH) and ideality factor by using I-V characteristics for the device were found as 0.75 eV and 1.68. By using the Norde method, the BH and the resistance of neutral region of the device were extracted as 0.80 eV and 1.17x104 Ω. The interfacial states concentration of the device has been seen to decrease from 2.79×1013 eV-1 cm-2 to 5.80×1012 eV-1 cm-2 . By using capacitance-voltage technique, the values of the built-in voltage, BH and semiconductor doping density were found as 1.22 V, 0.83 eV and 1.87x1017 cm-3 for the Ag/MG/p-InP diode, respectively.

Characterization Of Gallium Oxide With A Novel Non-Contact Electrical Metrology, CnCV, For Wide Bandgap Semiconductors

Cost savings and short feedback time are significant advantages of the corona non-contact capacitance voltage (CnCV) technique, recently introduced for wide bandgap SiC, GaN, and AlGaN/GaN as a replacement for C-V measurements on fabricated electrical test structures. The goal of this work is to verify the basic applicability and effectiveness of CnCV in characterization of Ga2O3. The results demonstrate excellent measurement conditions on Ga2O3 epitaxial and bulk grown wafers, enabling the determination of important electrical properties such as the dopant concentration profile, initial surface charge, electron affinity and depletion current.

Extraction of Interface-Trap Densities of the Stacked Bonding Structure in 3D Integration Using High-Frequency Capacitance-Voltage Technique.

An extraction method of the interface-trap densities (Dit) of the stacked bonding structure in 3D integration using high-frequency capacitance–voltage technique is proposed. First, an accurate high-frequency capacitance–voltage model is derived. Next, by numerically solving the charge-balance equation and charge conservation equation, Dit is extracted by fitting the measured and calculated capacitance–voltage curves based on the derived model. Subsequently, the accuracy of the derived model is verified by the agreements between the analytical results and TCAD simulation results. The average extraction error proves the precision and efficiency of the extraction method. Finally, the stacked bonding structure has been fabricated, and Dit at the interface between silicon and insulator is extracted to diagnose and calibrate the fabrication processes.

Generation, relaxation and annealing of Si/SiO2 charges induced by low-energy electron beam

Silicon oxide based, aluminum gated MOS structures fabricated on n-type silicon were subjected to a low energy electron beam irradiation in the scanning electron microscope. The induced interface states and the oxide charges were studied by the high frequency capacitance–voltage technique as a function of the electron beam energy, irradiation dose, annealing time, temperature and electric field. Strong initial increase and subsequent saturation of the donor-like interface state density with the irradiation dose was observed for all electron beam energies used. Besides, shallow positively charged traps were found to be formed in the silicon oxide after irradiation, while at the initial stage of irradiation the formation of a negative charge was established. The irradiation induced interface states and the positively charged shallow oxide traps demonstrated notable reduction at room temperature. Zero bias annealing at the temperatures of about 250–300 °C resulted in a complete removal of the interface states and partial compensation or elimination of the oxidation induced positive fixed charge, presumably due to remaining negative charge in oxide.

In Situ Dielectric Al2O3/β‐Ga2O3 Interfaces Grown Using Metal–Organic Chemical Vapor Deposition

AbstractHigh quality dielectric‐semiconductor interfaces are critical for reliable high‐performance transistors. This paper reports the in situ metal–organic chemical vapor deposition of Al2O3 on β‐Ga2O3 as a potentially better alternative to the most commonly used atomic layer deposition (ALD). The growth of Al2O3 is performed in the same reactor as Ga2O3 using trimethylaluminum and O2 as precursors without breaking the vacuum at a growth temperature of 600 °C. The fast and slow near interface traps at the Al2O3/β‐Ga2O3 interface are identified and quantified using stressed capacitance–voltage (CV) measurements on metal oxide semiconductor capacitor (MOSCAP) structures. The density of shallow and deep level initially filled traps (Dit) are measured using ultraviolet‐assisted CV technique. The average Dit for the MOSCAP is determined to be 6.4 × 1011 cm−2eV−1. The conduction band offset of the Al2O3/ Ga2O3 interface is also determined from CV measurements and found out to be 1.7 eV which is in close agreement with the existing literature reports of ALD Al2O3/Ga2O3 interface. The current–voltage characteristics are also analyzed and the average breakdown field is extracted to be approximately 5.8 MV cm−1. This in situ Al2O3 dielectric on β‐Ga2O3 with improved dielectric properties can enable Ga2O3‐based high‐performance devices.

Comparison and analysis of Al0.7InAsSb avalanche photodiodes with different background doping polarities

Background doping polarity is a key parameter in the design of numerous electrical and optoelectronic devices. It is especially critical for avalanche photodiodes (APDs). Recently, high-performance APDs have been demonstrated based on the AlInAsSb digital alloy materials system. A critical element of this work was the determination of the background doping polarity of the molecular beam epitaxial grown wafers. In this work, we determine the unintentional background doping polarity of Al0.7InAsSb using the double mesa capacitance-voltage technique. We fabricated two p-i-n Al0.7InAsSb structures: one with p-type background polarity and the other with n-type. The measurements indicate that devices with different background doping polarities show different capacitance relations to the mesa diameters; moreover, the relationship reverses at high voltage in a p-type background device. Subsequent simulations reveal that this reversal is caused by electrical field confinement after the depletion reaches the smaller top mesa. These findings are consistent with reports of reduced surface leakage current in double and triple mesa structures.

Characterization of magnetic Czochralski silicon devices with aluminium oxide field insulator: effect of oxygen precursor on electrical properties and radiation hardness

Aluminium oxide (Al2O3) has been proposed as an alternative to thermal silicon dioxide (SiO2) as field insulator and surface passivation for silicon detectors, where it could substitute p-stop/p-spray insulation implants between pixels due to its negative oxide charge, and enable capacitive coupling of segments by means of its higher dielectric constant.Al2O3 is commonly grown by atomic layer deposition (ALD), which allows the deposition of thin layers with excellent precision.In this work, we report the electrical characterization of single pad detectors (diodes) and MOS capacitors fabricated on magnetic Czochralski silicon substrates and using Al2O3 as field insulator. Devices are studied by capacitance-voltage, current-voltage, and transient current technique measurements. We evaluate the influence of the oxygen precursors in the ALD process, as well as the effect of gamma irradiation, on the properties of these devices. We observe that leakage currents in diodes before the onset of breakdown are low for all studied ALD processes. Charge collection as measured by transient current technique (TCT) is also independent of the choice of oxygen precursor. The Al2O3 films deposited with O3 possess a higher negative oxide charge than films deposited by H2O, However, in diodes a higher oxide charge is linked to earlier breakdown, as has been predicted by simulation studies. A combination of H2and O3 precursors results in a good compromise between the beneficial properties provided by the respective individual precursors.

Capacitance–Voltage Technique Based on Time Varying Magnetic Field for VDMOSFET—Part I: Concept and Implementation

In this article, we report a new capacitance–voltage technique ${C}$ ( ${V}$ ) to investigate the interface proprieties of MOS devices. This technique is based on surface potential modulation using time varying (ac) magnetic field. It is experimentally validated on vertical double diffusion MOSFET (VDMOSFET). Data show that the surface potential is modulated using external ac magnetic field. In fact, applying an ac magnetic field with dc voltage sweeping of VDMOSFET gate ( ${V}~_{G}$ ), we have been able, for the first time, to modulate the surface potential and measure the gate–source ( ${C} _{\text {GS}}$ ) and gate–drain ( ${C} _{\text {GD}}$ ) capacitances as a function of gate voltage ( ${V}~_{G}$ ) for P- and N-type transistors. Therefore, it offers a powerful tool to characterize different regions of the transistor and extract their technological and electrical parameters.

Capacitance–Voltage Technique Based on Time Varying Magnetic Field for VDMOSFET—Part II: Measurements and Parameter Extractions

In part I, we have proposed a new capacitance–voltage technique ${C}$ ( ${V}$ ), which is simultaneously based on external ac magnetic field for surface potential modulation and on dc voltage to sweep the gate voltage. In part II, we describe the parameter extractions of vertical double diffusion metal–oxide–semiconductor field effect transistor (VDMOSFET) devices, combining the capacitance characteristics of gate–source, ${C}_{\text {GS}}$ ( ${V}_{G}$ ) and gate–drain ${C}_{\text {GD}}$ ( ${V}_{G}$ ), measured using the above cited technique, with those measured conventionally. In doing so, we have been able to extract semiconductor capacitance ( ${C}_{\text {SC}}$ ), interface trap capacitance ( ${C}_{\text {it}}$ ), doping profile concentration ${N}$ ( ${x}$ ), and interface trap density ${D}_{\text {it}}$ ( ${E}$ ) of different regions of VDMOSFET.