Interconnect Capacitance Extraction Research Articles

3-D IC Interconnect Parasitic Capacitance Extraction With a Reformulated PGD Algorithm

Proper generalized decomposition (PGD) is a recently developed model-order reduction method based on the use of variable-separated representations. In this paper, space variable-separated PGD is applied on the 3-D capacitance extraction of interconnects in integrated circuits to reduce its computational complexity. To make the PGD solver feasible, the complex boundary conditions are simplified by a characteristic function technique. 3-D singular-value decomposition of the coefficient functions is avoided by using a reformulated PGD algorithm, and therefore, the proposed method can effectively deal with problems with inhomogeneous dielectric layers and dummy fills. Numerical examples are given to verify the method.

3-D IC Interconnect Capacitance Extraction Using Dual Discrete Geometric Methods With Prism Elements

The dual discrete geometry methods (DGMs) in terms of scalar potential using prism elements are employed in 3-D interconnect capacitance extraction of integral circuits. The energy complementarity property of the dual methods is explored to speed up the extraction. The dual DGMs work on the mutually orthogonal primal-dual mesh doublets, i.e., dual Delaunay–Voronoi mesh complex. As the orthogonal dual mesh is built based on the circumcenter of the primal mesh, the stability of the dual DGM heavily depends on the quality of the mesh. Elements with circumcenter dropping outside of the elements inevitably appear in the nonstructured prismatic meshes, due to the complicated structures in practical problems. The impact of these elements on the stability of the DGM is discussed. Comprehensive comparison between dual DGMs and dual finite-element methods (FEMs) and other golden references is performed. The dual DGM in terms of scalar potential has a reduced number of unknowns and simpler forms and works without extra links as required in the dual FEM in terms of vector potential. Capacitance extraction examples, such as a CMOS inverter and multilayer crossover parallel wires, are studied. The results demonstrate the energy bounds of dual DGMs and the improvement of accuracy with reduced cost.

Interconnect Modeling Using the Quasi Monte Carlo Integration Technique

A new fast and accurate capacitance determination methodology for interconnect capacitance extraction is presented. The methodology is based on Quasi Monte Carlo integration technique applied to method of moments solution of integral equation. As an example, the interconnects are modeled as parallel plate, cylindrical, and spherical capacitors separated by some distance and multilayered and multiconductor interconnects. The proposed capacitance determination methodology is more efficient and accurate than conventional methods and is also capable of dealing with singularity problem encountered in the kernel of the integrand. It is shown that the computed capacitances have excellent agreement with analytical formula based results within 2% error.

A reliable quick parasitic capacitance extraction tool for the physical layer in communication systems

High speed communication and application requirements are rapidly increasing, and the quality of physical layer is more and more important to realize real reliable communications. It requires accurate and reliable hardware devices, or else communications may be unstable and unsure. In this paper, we focus on the high speed network hardware integrated circuit systems to obtain good electrical, mechanical and procedural characters. Very large scale integrations (VLSI) form the basis for the implementation of high-performance, low-power, and low-cost wireless computing and mobile application systems. In integrated circuit (IC) design flow, distributed electromagnetic effects at high frequencies become prominent and decisively impact overall IC performance. To solve this problem, this paper presents an electronic design automation tool capable of automatic capacitance extraction for IC interconnections. This tool integrates electromagnetic field based two-dimensional (2-D) and three-dimensional (3-D) interconnect capacitance extraction solvers. It can be used for VLSI parasitic capacitance parameters extraction. The system architecture, capacitance extraction process flow and some important data structures will be discussed. Some extraction experimental results will demonstrate the accuracy and high efficiency of our 2-D and 3-D solvers.

Generalized Stochastic Collocation Method for Variation-Aware Capacitance Extraction of Interconnects Considering Arbitrary Random Probability

For variation-aware capacitance extraction, stochastic collocation method (SCM) based on Homogeneous Chaos expansion has the exponential convergence rate for Gaussian geometric variations, and is considered as the optimal solution using a quadratic model to model the parasitic capacitances. However, when geometric variations are measured from the real test chip, they are not necessarily Gaussian, which will significantly compromise the exponential convergence property of SCM. In order to pursue the exponential convergence, in this paper, a generalized stochastic collocation method (gSCM) based on generalized Polynomial Chaos (gPC) expansion and generalized Sparse Grid quadrature is proposed for variation-aware capacitance extraction that further considers the arbitrary random probability of real geometric variations. Additionally, a technique based on Minimum Spanning Tree (MST) structure is proposed to reduce the computation cost at each collocation point, for not only recycling the initial value, but also recycling the preconditioning matrix. The exponential convergence of the proposed gSCM is clearly shown in the numerical results for the geometric variations with arbitrary random probability.

PEEC capacitance extraction of 3-D interconnects

As feature size of electronic devices decreases, fast and accurate capacitance extraction has become increasingly critical for verification and analysis as regard as electromagnetic compat- ibility and signal integrity issues. The partial element equivalent circuit method is implemented for three-dimensional capacitance extraction of interconnects and very large-scale integration circuits with multiple dielectrics. The electric field coupling due to free and bound charges are analysed and modelled separately thus allowing to distinguish their contribution. The proposed approach provides physical insight, totally compatible fast methods for accelerating matrix-vector products, allows an easy treatment of lossy and dispersive dielectrics and is well suited for applying model order reduction techniques. Modern electronic design is surely extremely challenging. It is known that power distribution and management, digital computing and radio frequency wireless communication have very different bandwidths, as well as voltage and current levels. In addition, today's mobile devices share the same printed circuit board and/or packaging substrate in a very dense design. The consequence of this fact is that parasitics and interference poses significant design challenges and deserves a special attention to electromag- netic compatibility (EMC) engineers to meet design requirements. Parasitics may compromise the signal fidelity and/or level and dominate the coupling in the case of elec- tromagnetic interference and immunity. Typically, coupling takes place through the electric field (capacitive coupling), magnetic field (inductive coupling) or through a common current return path. It is understood that design meeting EMC criteria has a critical need for methodologies and computer-aided design tools, which allow to predict para- sitic effects and capture coupling physics. Also it is extre- mely desirable to extract parasitic lumped element circuit models from a layout geometry. As the feature size of electronics in mobile devices has dramatically decreased, the interconnect is becoming a dominant factor in system delay and signal integrity (SI). An accurate and efficient electromagnetic modelling of three-dimensional (3-D) high speed interconnects and very large-scale integration (VLSI) circuits embedded in mul- tiple dielectrics is extremely important for the design and verification of nowadays systems on package and systems on-chip for communication systems. Circuit performances such as SI, EMC, delay, radiation, power consumption, reliability are strongly influenced by the electrical charac- teristics of interconnects. Among the other effects, timing verification requires accurate interconnect modelling of parasitic parameters especially as regard as the parasitic

Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills

In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.

Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy

Integrated-circuit interconnect characterization is growing in importance as devices become faster and smaller. Along with this trend, interconnect geometry is becoming more complex, consisting of an increasing number of wiring levels. Accurate numerical extraction of three-dimensional (3-D) interconnect capacitance is essential for achieving design targets in the multigigahertz digital regime. Interconnect-capacitance extraction is complicated by the presence of inhomogeneous layers with differing dielectric constant. Dielectric anisotropy as well is common in many low-/spl kappa/ polymeric dielectrics used in high-performance ICs. A CAD procedure using the novel floating random-walk extractor QuickCAP is presented. Our procedure is efficient enough to extract a substantial amount of a chip's 3-D wiring. We include as well dielectric anisotropy and inhomogeneity. The procedure is not based on effective conductor geometry or on a finite-sized conductor library but rather on the entire 3-D layout, accounting for actual local variations in conductor separations and shapes. We then apply our procedure to an experimental circuit vehicle implemented in AlGaAs-GaAs heterojunction bipolar transistor current-mode logic. This vehicle is used to validate the accuracy of our CAD procedure in predicting circuit speed. Measured and predicted test-capacitor values and ring-oscillator propagation times agreed generally to within 2-4%. To verify results on a larger digital circuit, we analyzed all interconnects in an adder carry-chain oscillator using our procedure. Predicted propagation delays were generally within 3% of measurement.