Calorimeter Front-end Electronics Research Articles

Low noise 4-channel front end ASIC with on-chip DLL for the upgrade of the LHCb Calorimeter

An integrated circuit for the Upgrade of the LHCb Calorimeter front end electronics is presented. It includes four analog channels, a Delay Locked Loop (DLL) for signal phase synchronization for all channels and an SPI communication protocol based interface. The analog circuit is based on two fully differential interleaved channels with a switched integrator to avoid dead time and it incorporates dedicated solutions to achieve low noise, linearity and spill-over specifications. The included DLL is capable of shifting the phase of the LHC clock (25 ns) in steps of 1 ns. The selected technology is AMS SiGe BiCMOS 0.35 um.

Computing challenges in the certification of ATLAS Tile Calorimeter front-end electronics during maintenance periods

After two years of operation of the LHC, the ATLAS Tile calorimeter is undergoing a consolidation process of its front-end electronics. The certification is performed in the experimental area with a portable test-bench which is capable of controlling and reading out one front-end module through dedicated cables. This test-bench has been redesigned to improve the tests of the electronics functionality quality assessment of the data until the end of Phase I.

Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the present Long Shutdown (LS1) of LHC, improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a PowerPC 440 microprocessor hard core and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities needed to perform the desired tests such as TTCvi emulation, G-Link decoding, ADC control and data reception.

Low Noise Front End ASIC With Current Mode Active Cooled Termination for the Upgrade of the LHCb Calorimeter

The current mode line terminating input stage of an integrated circuit for the upgrade of the LHCb calorimeter front end electronics is presented. The circuit is based on a current mode input stage followed by two fully differential interleaved channels, namely a switched integrator and a track and hold. The input stage employs a novel electronically cooled input termination scheme to achieve stringent noise requirements. Compared to previous designs, its novelty relies in the use of two current feedback loops to decrease and control the input impedance of a common base stage. Two prototypes in Austriamicrosystems SiGe BiCMOS 0.35 μm technology have been designed and tested. Key measurements have been performed. Reflection coefficient is smaller than 0.5% for the full dynamic range, which is 12 bits. Relative linearity error is below 1%. Output noise is about 1 LSB after applying correlated double sampling.

Low noise front end ICECAL ASIC for the upgrade of the LHCb calorimeter

A fully differential ASIC with cooled input termination is presented as a solution for the Upgrade of the Calorimeter front end electronics. The LHCb experiment needs to increase about ten times the integrated luminosity in order to study new physics. The increase in signal has to be compensated reducing the gain of the photomultipliers which implies stringent noise requirements. The proposed solution offers an active termination at the input and avoids the noise originated by the use of a resistor. The circuit is based on a two interleaved channel with a first amplifier stage, a switched integrator, and a Track-and-Hold. Two prototypes have been implemented and tested in SiGe BiCMOS 0.35um technology.

A High Speed Serializer ASIC for ATLAS Liquid Argon Calorimeter Upgrade

We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgrade

We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in a 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post-layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

Radiation hardness on very front-end for SPD

The calorimeter front-end electronics of the LHCb experiment will be located in a region, which is not protected from radiation. Therefore, all the electronics must be qualified to stand some defined radiation levels. The procedure, measurements and results of an irradiation test for every component of the very front-end SPD detector, which is part of the LHCb calorimeter are presented here. All the tested components, except a custom made ASIC, are commercially available.

Test system for the production of the Atlas Tile Calorimeter front-end electronics

The Atlas hadronic Tile Calorimeter front-end electronics is fully included in the so-called “super-drawers”. The 256 super-drawers needed for the entire calorimeter are assembled and extensively tested in Clermont-Ferrand before being sent to CERN to be inserted in the calorimeter modules. A mobile system has been developed to perform a complete test of the super-drawers during their insertion.

Analog floating-point BiCMOS sampling chip and architecture of the BaBar CsI calorimeter front-end electronics system at the SLAC B-factory

The design and implementation of an analog floating-point sampling integrated circuit for the BaBar detector at the SLAC B-Factory is described. The CARE (Custom Auto-Range Encoding) circuit is part of an 18-bit dynamic range sampling system with a 4-MHz waveform digitization rate for the CsI calorimeter. The architecture and methodology of the system are described. The CARE integrated circuit receives dual-range (gain of 1 and 32) 13-bit signals from the 18-bit range preamplifiers mounted directly on the CsI crystals and converts the input at a rate of 4 MHz to an auto-range floating-point format with a 10-bit analog mantissa and 2 digital range bits (for 4 ranges). Additional functions integrated on the chip are averaging and selection circuitry for signals originating from two independent diodes per crystal and range-selection overwrite circuitry. The circuit will be mounted within the detector structure and thus low power dissipation is essential. The circuit has been fabricated in a 1.2-/spl mu/m BiCMOS process with polysilicon-to-polysilicon capacitors and polysilicon resistors. Measurement results are presented. One complete CARE channel dissipates 25 mW.

Hadron calorimeter front-end electronics for the upgraded UA1 detector

A solution to interfacing a scintillator calorimeter with photomultipliers to electronics designed for ionization chambers is presented. We describe in detail the development guidelines and the layout of a combined analogue/digital card that allows us to form a coherent electronics setup with the same readout chain for two entirely different types of calorimeters

The DELPHI Hadron Calorimeter module characteristics in the saturated proportional mode of its detector operation

Abstract A preamplifier allowing an increase in the sensitivity of the already produced DELPHI Hadron Calorimeter front-end electronics up to 0.1 pC is described. The presented preamplifier permits a considerable reduction of the gas gain and transition to the saturated avalanche mode region. The HC barrel module characteristics in the proportional mode of its detector operation are explored. The possibility of selecting muon tracks in the HC and using them for detector triggering has been investigated. It is shown that the transition to the proportional mode does not worsen the main characteristics of the HC and the reliability of its detectors will be considerably increased. The investigation has been performed at the Laboratory of High Energies, JINR.