Bus Interface Unit Research Articles

UVM based verification of iAPX 186 processor modules

UVM is used to enable faster development and reuse of System Verilog based Verification Environment. The use of UVM is to develop reusable test bench. The UVM class library contains configuration database, TLM and component hierarchy. Each and every component in the verification environment has a specific functionality. The UVM has a list of base class which are pre-stored and System Verilog environment can be built by deriving the base classes. Two parameters have been used namely Coverage and Assertions. Coverage is used to measure whether all features of the design specification is tested. Assertions are used for checking the behavior of the design. In this work, we design the individual blocks like Interrupt Controller, Timer module, DMA Controller, Execution Unit and Bus Interface Unit of 80186 processor using Verilog and Verify its functionality behavior using the two parameters using UVM.

Implementation of ARINC 659 Bus Controller for Space-Borne Computers

As one of the key technologies of Honeywell, the aeronautical radio incorporated (ARINC) 659 bus is popular in current space-borne computers. However, Honeywell does not design ARINC 659 bus controller separately, and there are only a few papers about FPGA-based ARINC 659 bus controllers. Accordingly, to promote the extremely high performance needs of space-borne computers, this paper designs an ARINC 659 bus controller chip which integrates two independent bus interface units (BIUs), one 8-bit MCU, and several peripheral interfaces (i.e., UART, SPI, and I2C). Because the two BIUs are identical and mutually checked, the symmetry problem is emphatically dealt with in the design of this bus controller, and effective timing convergence is realized, which makes the bus controller work reliably and stably. In addition, due to the circuit’s large scale, design for testability (DFT) is also considered. Accordingly, on-chip clock (OCC) and scanning compression test technique are used to realize the at-speed test and shorten the test time, respectively.

Portable Toolbox for Monitoring and Evaluating Signal Operations

Traffic signal operators are often faced with the challenge of assessing the performance of signal operation and troubleshooting day-to-day operational issues. In many cases, the problems can be specific to a certain time of day or exclusive traffic patterns; this specificity makes it more difficult to pinpoint the problems without spending hours or even days at the sites. With limited resources and budget constraints, public agencies need to find a more efficient and cost-effective approach to operating and maintaining an ever-increasing number of signals within their jurisdictions. To address this challenge, the authors developed a portable tool that consists of a field-hardened computer that interfaces with the traffic signal cabinet through special enhanced bus interface units. The toolbox consists of a monitoring tool and an analysis tool. The monitoring tool monitors and logs relevant events within the cabinet that provide input for analyzing intersection operations. These inputs include signal status, detector call status (including pedestrian calls), preempt status, and coordination status. The analysis tool then analyzes the log files for each day and produces user-friendly reports in hourly average and cycle-based formats. The measures of effectiveness produced by the tool include signal data (e.g., phase time, phase failures, queue clearance time), pedestrian data (e.g., pedestrian calls per hour and average time to service pedestrian), and preempt data (e.g., type of preempt, time of preempt, and duration of preempt). The analyst can install the tool in the signal cabinet and log the data for subsequent evaluation and troubleshooting in the office. The tool was deployed and field-evaluated at two signalized intersections in Texas. The results generated from the tool were found to be in good agreement with observations at the test sites.

Active fault protection for an AC zonal marine power system

This study presents a method to protect the zonal distribution system proposed for future ships when fault occurs. By utilising a bus interface unit, the energy storage and grid interface within it provide one benefit that an independent fault protection scheme can be achieved. The new protection scheme is based on active impedance estimation. This technique actively imposes small transient disturbances onto the system at a point of measurement to excite the system in real time and estimate the system impedance at that point. The continuous wavelet transform is employed to achieve accurate impedance estimation over a broad frequency range from a small amount and very noisy data. The performance of this proposed technique is investigated both by simulation and experiment. The scheme exploits the increased use of power electronic devices to provide a useful complement to traditional protection strategies, which can also provide the necessary back up protection during extreme protection failure, without the need for communication channels.

A trace-driven simulation methodology

This paper presents a simulation methodology for evaluating the performance of CISC computers. The method is called Message Flow Technique (MFT). MFT has several advantages over Instruction Flow Technique (IFT) we presented in [1]. The proposed methodology is applied to a single and two-level cache CISC system using 80486 SX as a case study. It was found that with a single-level on-chip cache of size 8K, the performance of the system is considerably limited by the service time of BIU(Bus Interface Unit). The average service time of BIU, per instruction, was found to be around 1.0135 microseconds for our Modified Gibson Mix (MGM). With a second-level external cache of sizes 16K, 32K, 64K, and 128K the average performance improvements were found to be 1.4%, 18.6%, 39% and 53% respectively. The methodology presented here is an efficient and easy to use tool that could help performance analysts in evaluating computer systems.

A methodology for evaluating the performance of CISC computer systems under single and two-level cache environments

This paper presents a simulation methodology for evaluating the performance of CISC computers. The method is called Message Flow Technique (MFT). MFT has several advantages over Instruction Flow Technique (IFT) we presented in [1]. The proposed methodology is applied to a single and two-level cache CISC system using 80486 SX as a case study. It was found that with a single-level on-chip cache of size 8KB, the performance of the system is considerably limited by the service time of BIU (Bus Interface Unit). The average service time of BIU, per instruction, was found to be around 1.0135 microseconds for our Modified Gibson Mix (MGM). With a second-level external cache of sizes 16KB, 32KB, 64KB, and 128KB the average performance improvements were found to be 1.4%, 18.6%, 39% and 53% respectively. The methodology presented here is an efficient and easy to use tool that could help performance analysts in evaluating computer systems.

Microprocessor architectures and systems: RISC, CISC and DSP

Part 1 Complex instruction set computers: enter the MC68000 complex instructions, Microcode and Nanocode the MC68000 hardware M68000 asynchronousbus M6800 synchronousbus the user/supervisor concept the MC68010 virtual memory processor MC68010 supervisor resource the MC68008. Part 2 32-bit CISC processors: enter HCMOS technology the MC68020 32-bit performance standard coprocessor interface MC68881 and MC68882 floating point coprocessors the MC68851 paged memory management unit (PMMU) the MC68030, the first commercial 50 MHz. Part 3 The rise challenge: the 80/20 rule the initial RISC research the Berkeley model the Stanford model the catalysts the M88000 family the MC88100 programming model the MC88100 instruction set MC88100 external functions M88200 cache MMU the MBUS protocol M88000 master/checker fault tolerance. Part 4 Digital signal processing: the DSP56000 family move commands. Part 5 Memory, memory management and caches: shadow RAM DRAM v SRAM optimizing the DRAM interface memory management multitasking and user/supervisor conflicts. Part 6 Real time software interrupts and exceptions: interrupting an MC88100 MC88100 interrupt service routines interrupting the DSP56000 triadic instruction sets register windowing the M68300 family. Part 7 Multiprocessing: SISD - single instruction, single data SIMD - single instruction, multiple data MIMD - multiple instruction, multiple data MISD - multiple instruction, single data constructing a MIMD architecture processor bandwidths. Part 8 Application ideas: MC68020 and MC68030 design techniques for high-reliability applications transparent update techniques for digital filters using the DSP56000 motor and servo control. Part 9 Semiconductor technology: semiconductor technology silicon technology CMOS and bipolar technology. Part 10 The changing design cycle: the changing design cycle the shortening design cycle simulation v emulation. Part 11 Generation: enter the MC68040 the instruction execution unit the bus interface unit the M68300 family DSP96000 combining integration and performance once a new approach to emulation integration and higher performance. Part 12 Selecting a microprocessor architecture: meeting performance needs development support considering all the options. Appendices: benchmarking binary compatibility standards.

Reliability analysis techniques for complex multiple fault tolerant computer architectures

Several issues on reliability analysis of complex multiple-fault-tolerant computer systems are addressed, and techniques are developed to reduce the complexity of the reliability model. Two-fault-tolerant architectural concepts (the matrix-voter-based architecture, MVA, and the channel-voter-based architecture, CVA) developed for a computer node in a distributed embedded environment are used as examples. These two architectures are analyzed including the dynamics of transient and intermittent faults. The relationship between the number of retries and its effect upon system reliability has been analyzed for various average transient lifetimes. The MVA, although structurally regular, is more challenging for reliability analysis than the CVA. The system unreliability decreases as the reliability of the MVA is rather insensitive to the bus-interface unit failures. For the same parameter values, the MVA has an unreliability 1/10 that of the CVA. >

Systems aids in determining Local Area Network performance characteristics

At Bethesda, Maryland, the National Library of Medicine has a large array of heterogenous data processing equipment dispersed over ten floors in the Lister Hill Center and four floors in the Library Building. The National Library of Medicine decided to implement a more flexible, expansible access medium (Local Area Network (LAN) to handle the rapid growth in the number of local and remote users and the changing requirements. This is a dual coaxial cable communications system designed using cable television (CATV) technology. One cable, the outbound cable, transfers information between the headend and the user locations. The other cable, the inbound cable, transfers information from the user locations to the headend. This system will permit the distribution of visual and digital information on a single medium. On-line devices, computers, and a technical control system network control center are attached to the LAN through BUS Interface Units (BIUs). The technical control system will collect statistical and status information concerning the traffic, BIUs, and system components. The BIUs will, at fixed intervals, transmit status information to the technical control. The Network Control Centers (NCC) will provide network directory information for users of the system, descriptions of the services available, etc. A X.25 gateway BIU will interface the LAN to the public networks (Telenet and Tymnet) and to X.25 host computer systems.

Bidirectional token flow system

Over the last few years there has been an avalanche of technical literature on techniques for allowing nodes to access and share one of the most valuable resources of a computer communication network, i.e., the bandwidth of the communication media. 1 This report describes the design of a new type of Local Area Computer Network called BID that uses a bidirectional token flow as a form of token passing. 2 The design of BID not only allows it to process messages having various properties but also makes it possible to operate simultaneously in a packet and circuit-switching mode. This latter mode, using minipackets, enables BID to be used for those applications having real-time response requirements. In describing BID this report defines the basic concepts of the implicit token, token carrier, token generator, and token wait time. It also describes a new preemption technique which reduces the walk time normally associated with token and polling systems. A GPSS computer simulation was made of the BID system to determine the average delay times experienced by the various priority classes of messages. An analytical model using a single priority class of messages is presented, and the results of the computer simulation are compared with this. The simulation results also indicate the uniformity of the average delays experienced by the Bus Interface Units across the bus resulting from the use of bidirectional flow of tokens.

The Honeywell Modular Microprogram Machine

M 3 is intended for research into unconventional special purpose stored program elements of computer systems (for example, a distributed computer Bus Interface Unit). The principal requirements for such a machine are flexibility and modularity. M 3 consists of an application independent Kernel Machine to which application-dependent Functional Modules are attached. The Kernel Machine is vertically microprogrammed; it includes highly capable microinstruction sequencing logic which facilitates structured microprogramming. The Functional Modules contain the operand registers and the operators (e.g., adders, shifters, etc.) needed by the specific application. The operators may be invoked not only by the Kernel Machine but also by one another; control may be passed among operators in a sequential or hierarchical fashion; operators may execute concurrently with each other and with the Kernel Machine; operators may be re-entrant or recursive; operators may activate themselves, or cause microcode interrupt routines to be executed in the Kernel Machine.