Busbar Inductance Research Articles

Impact of Dimensions, Apertures and Terminals on Stray Inductance of the Laminated Busbar

This paper presents a systematic investigation of the impact of physical parameters such as dimensions, apertures and terminals, on the busbar inductance. A planar laminated busbar with copper conductors and a polyamide insulator is studied using a 3D FEM (Finite Element Modelling) based simulation software. The impact of dimensions such as conductor length, width and thickness, depth of insulator, the effects of aperture number, size, position and connection terminals on the busbar inductance are examined. The magnetic flux density, current density involved and its dependence on the self and mutual inductance of the laminated busbar is analyzed. Laminated busbars provided lower inductance with decreased conductor length, thickness, aperture diameter and depth of insulator. Also, the increased width of the busbar is of the essence for the design of a low inductance busbar. Low inductance laminated busbars are highly beneficial in power converters, powertrain inverters in electric vehicles, photovoltaic converters.

Influence of physical parameters on the capacitance of laminated busbars for electric vehicles

Laminated busbars are essential for highly efficient, high power density applications, especially in the electric transportation sector, due to their unique electrical and mechanical characteristics. Stray parameters in laminated busbars pose a real challenge to designers in industries and researchers in the field since controlling these are crucial in busbar performance. Laminated busbar inductance has been studied extensively in the literature. However, very few works have focussed exclusively on the capacitance of the laminated busbar. In this paper, the impacts of busbar physical parameters on capacitance are studied in detail using Finite Element Modelling (FEM) software, ANSYS Q3D Extractor. The variation of capacitances on laminated busbars concerning several factors such as the busbar dimensions, terminals and apertures on the busbar structure, conductor and insulator materials are analysed.

EMI Performance of Active Neutral Point Clamped Phase Leg for Dual Active Bridge DC–DC Converter

This article evaluates the electromagnetic interference (EMI) caused by active neutral point clamped (ANPC) phase leg undergoing zero voltage switching (ZVS). ZVS, together with a high fundamental frequency operation is encountered in dual active bridge (DAB) converters. This allows ANPC phase leg to be operated in a different manner than its inverter counterpart. A comprehensive evaluation of four switching schemes for NPC/ANPC-DAB with regard to their EMI performance, voltage overshoot, and losses have been done. Switching state redundancies have been used to reduce the EMI of the ANPC phase leg. To further help in reduction of high frequency EMI and voltage overshoot, a low inductance busbar design has been presented for through-hole discrete devices. Finite element simulation and measurement results show a busbar inductance of 7.7 nH for long commutation loops. Finally, EMI performance (conducted and radiated) together with the busbar design has been experimentally validated for two of the most useful switching schemes. The switching schemes and the busbar design can boost adoption of NPC/ANPC-DAB by ensuring EMI compliance and improved efficiency without affecting the normal DAB operation or using additional hardware.

Circuit implementation of power converter for high-speed switching operations

Recently, high di/dt and dv/dt switching operations of power converter circuits has been discussed for realizing a high-efficiency power converter circuit. In this case, parasitic inductances of the bus bar between a DC capacitor and power devices may cause issues of overshoot voltage and electromagnetic interference(EMI) noise. Therefore, it is necessary to design the bus bar geometry while considering the minimization and optimization of the parasitic inductance of bus bar. This paper discusses a relationship between bus bar geometry and switching characteristics. In addition, the bus bar analysis is based on the PEEC method, and the bus bar geometry is designed by considering the stray inductance with using an inductance-map method. Moreover, this paper also presents a design procedure of acceptable stray inductance based on a standardization method. It should be noted that the stray inductance is designed not for minimization, but optimization, and it is shown not as an absolute value(H), but as a percentage value(%). Finally, the oscillation waveforms under turn-off operation will be discussed depending on the bus bar geometry.

Measurement of Parasitic Inductances in the Bus-Bar Assembly of a High Power Voltage Source Converter

Insulated gate bipolar transistor (IGBT) based voltage source converters use copper plates with insulating sheets in between them (sandwich bus-bar arrangement) for connecting the different device terminals in the power circuit. In such converters, the parasitic inductances in the power circuit are crucial as they cause overvoltage spikes across the device. Also, the parasitics affect the current sharing between IGBTs when they are connected in parallel in high power converters. The conduction path through plates and fasteners in the bus-bar assembly is three-dimensional and quite complex, making analytical evaluation of the stray inductance quite challenging. The first objective here is to present a simple experimental setup and experimental procedure, which are convenient for power electronic engineers, to measure the bus-bar inductance. The next objective is to carry out experimental studies on the inductances offered by different components and sub-assemblies in a bus-bar assembly. This includes evaluation of inductances of the different conduction paths in typical bus-bar plates. The third objective is to experimentally evaluate the parasitic inductances in the bus-bar assembly of a commercial 250 kVA high power converter. Each leg of this converter consists of two 300 A/1200 V IGBTs connected in parallel. The effective inductance seen by the individual device modules are determined experimentally.

Laminated Bus Bar Design for Power Converter Circuit Considering Structural and Electrical Limitations

In order to improve the reliability of a power converter circuit, it is important to analyze the DC-side stray inductance between the DC capacitor and the power devices because this may affect the switching losses, lead to the occurrence of over-voltages in power devices, and increase the short-circuit current. As such, a number of studies have investigated these effects through calculations, experiments, and circuit simulations. However, thus far, no paper has discussed a design of the stray inductance. In this paper, the authors propose a design procedure for the stray inductance of the laminated bus bar for a high-speed switching circuit using SiC power devices. The relationship among the bus bar inductance, the over-voltage, and the short-circuit current is clarified using an analytical MOSFET model. In order to verify the analysis results, an experiment using SiC-MOSFET and SiC-SBD rated at 1,200V is conducted. From these results, the upper and lower limitations of the bus bar inductance for the buck chopper circuit are found, and the design procedure for the wiring structure considering the stray inductance is discussed using the inductance map.

The Impact of Layer Number on Stray Inductance of DC-link Busbar in Power Converters

In high power converter design, low-inductance busbar connecting DC capacitors and power devices is the main concern to improve the quality of the whole power electronics system. This paper analyzes the impact of layernumber on the stray inductance of busbar taking a subway traction converter as example. The method of partial element equivalent circuit and the Q3D software are used to extract the stray inductance. The simulation and experimental results show that the stray inductance of three-layer busbar is lower than two-layer busbar with other same conditions.

Study on the Impact of Layer Number on Stray Inductance of Busbar

In high power converter design, low-inductance busbar connecting DC capacitors and power devices is main concern to improve the quality of the whole power electronics system. This paper analyzes the impact of layer-number on the stray inductance of busbar taking a subway traction converter as example. The method of partial element equivalent circuit and the Q3D software were used to extract the stray inductance. The simulation and experimental results show that the stray inductance of three-layer busbar is lower than two-layer busbar with other same conditions.

High-Speed Analysis of Bus Bar Inductance for a Laminated Structure

High-Speed Analysis of Bus Bar Inductance for a Laminated Structure

Design of Wiring Structure by Considering Bus Bar Inductance

Recently, high-switching-frequency and high-di/dt switching operation of inverters has been studied for the purpose of finding a way to reduce the size and weight of LC filters. In power electronic circuits, the stray inductance of the bus bar between a DC capacitor and power devices may cause an overshoot voltage and electromagnetic interference (EMI) noise for high-di/dt switching operation. Therefore, it is necessary to design the bus bar structure while considering the minimization and optimization of the bus bar inductance value. Generally, the bus bar inductance is analyzed by using 3D finite element method (FEM), but it takes a long time to construct analytical models and to perform the analysis. This paper proposes an improved calculation method for a medium-voltage inverter, based on the partial inductance calculation method. In addition, the wiring structure is designed by considering the stray inductance with using an inductance-mapping method.

A simplified method of calculating busbar inductance and its application for stray resonance analysis in an inverter dc link

A simplified method of calculating busbar inductance and its application for stray resonance analysis in an inverter dc link

A simplified method of calculating busbar inductance and its application for stray resonance analysis in an inverter dc link

Sinusoidal PWM control is widely applied to power electronic converters. The carrier frequency of recent converter products is gradually being raised in order to decrease current harmonics as much as possible. However, in the dc filter circuits of large capacity converters, the capacitance of a unit capacitor is relatively large, and the busbars are relatively long. Therefore, the resonant frequency is lower than those of small capacity converters. Consequently, there is a concern that the carrier frequency will become close to the resonant frequency, which will cause trouble. On the other hand, it is often necessary to decrease the inductance of the loop circuit consisting of a switching device and its by-pass circuit, in order to suppress the switching surge voltage. In both cases described above, it is important to be sure of the exact busbar inductance for reliable design. In this paper, a simplified method of calculating busbar inductance is proposed. This method is based on the partial inductance theory. In particular, the characteristics of a pair of busbars, and the use of the method are described. Finally, an application to stray resonance analysis in the dc filter circuit of a three level inverter is described in comparison with experimental data. From these results, we confirmed that the proposed method is usable to estimate busbar inductance quickly and accurately. © 1999 Scripta Technica, Electr Eng Jpn, 126(3): 49–63, 1999

A Simplified Calculating Method of Busbar Inductance and Its Application for Stray Resonance Analysis in Inverter DC Link

A Simplified Calculating Method of Busbar Inductance and Its Application for Stray Resonance Analysis in Inverter DC Link

Multiple Paralleling of Power Diodes

Analysis of current sharing in multiple parallel power diode assemblies highlights the significance of bus-bar inductance. Some mutual inductances are demonstrated to be advantageous and practical design guidelines for multiple parallel diode rectifiers are given.