Buried Photodiode Research Articles

1T semi-floating gate image sensor with enhanced quantum efficiency and high response speed

The active pixel image sensor based on a semi-floating gate transistor (SFGT-APS) has been proposed and investigated; however, the quantum efficiency (QE) and the sensitivity are too poor to meet low illumination intensity and high-speed application due to the shallow junction of photodiodes. In this work, we demonstrate a new structure, called buried photodiode semi-floating gate transistor active pixel image sensor (BSFGT-APS), which possesses enhanced QE, high sensitivity, and fast response speed. Moreover, BSFGT-APS has the same fill factor with SFGT-APS, which is 55% with a 1 μm2 photodiode in 0.13 μm process. The basic device characteristics were investigated by Sentaurus TCAD simulation, including potential of photodiode, transient response, dark current, conversion gain, and full well capacity.

A Pump-Gate Jot Device With High Conversion Gain for a Quanta Image Sensor

A new photodetector designed for Quanta image sensor application is proposed. The photodetector is a backside-illuminated, buried photodiode with a vertically integrated pump and transfer gate and a distal floating diffusion to reduce parasitic capacitance. The structure features compact layout and high conversion gain. The proposed device is modeled and simulated, and its performance characteristics estimated.

Radiation Effects in Pinned Photodiode CMOS Image Sensors: Pixel Performance Degradation Due to Total Ionizing Dose

Several Pinned Photodiode (PPD) CMOS Image Sensors (CIS) are designed, manufactured, characterized and exposed biased to ionizing radiation up to 10 kGy(SiO2 ). In addition to the usually reported dark current increase and quantum efficiency drop at short wavelengths, several original radiation effects are shown: an increase of the pinning voltage, a decrease of the buried photodiode full well capacity, a large change in charge transfer efficiency, the creation of a large number of Total Ionizing Dose (TID) induced Dark Current Random Telegraph Signal (DC-RTS) centers active in the photodiode (even when the Transfer Gate (TG) is accumulated) and the complete depletion of the Pre-Metal Dielectric (PMD) interface at the highest TID leading to a large dark current and the loss of control of the TG on the dark current. The proposed mechanisms at the origin of these degradations are discussed. It is also demonstrated that biasing (i.e., operating) the PPD CIS during irradiation does not enhance the degradations compared to sensors grounded during irradiation.

CMOS image sensors comprised of floating diffusion driving pixels with buried photodiode

New CMOS image sensors that can realize high quality dark scene images with pixels smaller than conventional pixel types are described. The new technologies used to develop them are floating diffusion (FD) driving pixel with a buried photodiode with three or less transistors, and low-voltage driving technologies with a new photodiode structure and FD-boost method. Through the use of the 0.25-/spl mu/m technology, prototype chips consisting of 3.45-/spl mu/m size pixels were manufactured. Prototype chips consisting of 3.1-/spl mu/m size pixels which share FD between two neighboring pixels (2-pixel-sharing) were also manufactured. The complete transfer operation, that is to say, zero lag and zero pixel kTC noise was achieved at a supply voltage of 2.5 V with manufacturing stability. Realized saturation voltages were 510 and 360 mV for 3.45-/spl mu/m and 3.1-/spl mu/m size pixel chips, respectively. In addition, a combined double-correlated double sampling (CDS) architecture which can flexibly process two sets of signals in combination were employed. Due to its small pixel size, high image quality, and output flexibility, this framework has potential for replacing charge-coupled device (CCD) image sensors with CMOS image sensors in volume markets of digital still cameras and camcorders.

A 3.9-/spl mu/m pixel pitch VGA format 10-b digital output CMOS image sensor with 1.5 transistor/pixel

A 3.9-/spl mu/m pixel pitch VGA format 10-b digital output CMOS image sensor with 1.5 transistor/pixel has been developed for mobile applications. The newly developed CMOS pixel architecture realizes the minimum number of the transistors in one pixel. Small pixel size and sufficient fill factor are achieved by using the shared pixel architecture and floating diffusion driving. High conversion gain, low random noise, and low dark current are achieved by buried photodiode with complete charge transfer capability and correlated double sampling (CDS) circuit. The image sensor is fabricated in a thin planarized 0.35-/spl mu/m single poly-Si double-metal customized CMOS process in order to provide good image performance. The image sensor achieves low noise floor of 330 /spl mu/V and low dark current of 50 pA/cm/sup 2/ at 45/spl deg/C. This image sensor also realized various functions by on-chip digital and analog circuits.

3-D Optical and Electrical Simulation for CMOS Image Sensors

The optical and electrical characteristics of CMOS image sensors, such as readout, saturation, reset, charge-voltage conversion, and crosstalk characteristics, are analyzed by a three-dimensional (3-D) device simulator SPECTRA and a 3-D optical simulator TOCCATA which were developed for the analysis of CCD image sensors. The model of readout operation for a buried photodiode with potential barrier and dip is discussed with consideration of thermal diffusion. The transient simulation is executed for readout and reset operation. A novel calculation method for photodiode saturation condition is proposed. The optical and electronic crosstalk is analyzed individually by ray-tracing and current calculation. It is found that the above methods successfully analyze the optical and electrical characteristics of CMOS image sensors.

Low-leakage-current and low-operating-voltage buried photodiode for a CMOS imager

A low-leakage current and low-operating-voltage buried-photodiode structure of CMOS image sensors has been developed. The new structure adopted a modified fabrication process as well as an additional shallow p+ layer structure that covers the entire surface of the deep n-type photodiode. The required operating voltage for complete charge transfer from the photodiode is 3.3 V. Furthermore, the leakage current level allows high-quality images comparable to those of CCD image sensors.

3-D optical and electrical simulation for CMOS image sensors

The optical and electrical characteristics of CMOS image sensors, such as readout, saturation, reset, charge-voltage conversion, and crosstalk characteristics, are analyzed by a three-dimensional (3-D) device simulator SPECTRA and a 3-D optical simulator TOCCATA which were developed for the analysis of CCD image sensors. The model of readout operation for a buried photodiode with potential barrier and dip is discussed with consideration of thermal diffusion. The transient simulation is executed for readout and reset operation. A novel calculation method for photodiode saturation condition is proposed. The optical and electronic crosstalk is analyzed individually by ray-tracing and current calculation. It is found that the above methods successfully analyze the optical and electrical characteristics of CMOS image sensors.

24-5 埋め込みホトダイオードとバリアを介して駆動するCCDレジスタの結合の検討

24-5 埋め込みホトダイオードとバリアを介して駆動するCCDレジスタの結合の検討

イメージセンシング技術 ＣＭＯＳイメージセンサにおける低電圧駆動埋込みＰＤの解析 埋込みＰＤ構造による低リーク電流の検討

A CMOS image sensor with a very-low-leakage photodiode and a low-voltage buried photodiode has been developed that has sensitivity comparable to that of conventional CCD imagers. Photodiode leakage current caused by stress originates in the surface damage and in the dislocations and defects near the local oxidation of silicon. Use of a dislocation free stress-release process and of a buried photodiode reduced the damage and eliminates the stress. A 1/4-inch 330 K pixel CMOS image sensor using this buried photodiode structure and a sensor-specified process had a low dark current of 0.1 nA/cm2 in 5.6 μm pixels. The buried photodiode can operate in complete charge-transfer mode at voltage as low as 3.3 V, thereby suppressing the image lag and FPN of the photodiode.

固体撮像とその関連技術 １６０万画素増幅型イメージセンサＢＣＡＳＴの開発

This paper introduces a new device architecture suitable for obtaining a large format, high resolution, and high performance image sensor. Each pixel in the sensor comprises a buried photodiode and a junction field effect transistor, for signal charge generation and amplificaion, respectively. A 1.6 M pixel image sensor was constructed with source follower amplifiers and correlated double sampling circuits for signal readout. The image sensor exhibited high-sensitivity, low-noise, and high-protection capabilities for blooming and smear. The fundamental characteristics-sensitivity of 2 V/lx·s, dynamic range of 75 dB, noise equivalent exposure of 9.2×10-5lx·s, and a dark FPN level of -66 dB were achieved.