Bulk Fin Field Effect Transistor Research Articles

Current–Voltage Model of Bulk Fin Field-Effect Transistors with a Half-Circle Corner

The drain current of fully depleted (FD) nanoscale bulk FinFETs with the top-channel of a half-circle shape was modeled, for the first time, systematically in all operational regions and compared with the data obtained from three-dimensional (3D) device simulation. In the current model of these devices, it is very important to have accurate threshold voltages for side-channels and top-channel, and take the field penetration effect induced by the top-gate near the top of a fin body into account the threshold voltage (Vth) models for top-channels and side-channels, respectively. So, we obtained successfully the Vth models [Vth0t (Vth model of top-channel at a low drain bias) and Vth0s (Vth model of side-channels at a low drain bias)] considering the field penetration effect for both channels (top- and side-channels) to model the current behaviors in the doped bulk FinFETs with the top-channel of a half-circle shape. Our compact current model with Vth0t and Vth0s predicted accurately the current behaviors of the devices and shown a good agreement with 3D simulation.

Influence of gate-source/drain misalignment on the performance of bulk FinFETs by a 3D full band Monte Carlo simulation

We investigate the influence of gate-source/drain (G—S/D) misalignment on the performance of bulk fin field effect transistors (FinFETs) through the three-dimensional (3D) full band Monte Carlo simulator. Several scattering mechanisms, such as acoustic and optical phonon scattering, ionized impurity scattering, impact ionization scattering and surface roughness scattering are considered in our simulator. The influence of G—S/D overlap and underlap on the on-states performance and carrier transport of bulk FinFETs are mainly discussed in our work. Our results show that the on-states currents increase with the increment of G—D/S overlap length and the positions of a potential barrier and average electron energy maximum vary with the G—D/S overlap length. The carrier transport phenomena in bulk FinFETs are due to the effect of scattering and the electric field in the overlap/underlap regime.

Three-dimensional Monte Carlo simulation of bulk fin field effect transistor

In this paper, we investigate the performance of the bulk fin field effect transistor (FinFET) through a three-dimensional (3D) full band Monte Carlo simulator with quantum correction. Several scattering mechanisms, such as the acoustic and optical phonon scattering, the ionized impurity scattering, the impact ionization scattering and the surface roughness scattering are considered in our simulator. The effects of the substrate bias and the surface roughness scattering near the Si/SiO2 interface on the performance of bulk FinFET are mainly discussed in our work. Our results show that the on-current of bulk FinFET is sensitive to the surface roughness and that we can reduce the substrate leakage current by modulating the substrate bias voltage.

Low-Frequency-Noise Investigation of n-Channel Bulk FinFETs Developed for One-Transistor Memory Cells

The low frequency (LF) noise has been studied in n-channel triple-gate bulk fin Field-Effect Transistors (FinFETs), which are developed for one-transistor (1T) memory applications. Significant variation in the noise spectral density has been observed, which is related to the random occurrence of excess Lorentzian components, associated with generation-recombination (GR) noise. Both gate-voltage-dependent and gate-voltage-independent GR noise peaks have been found, which are assigned to gate oxide traps or traps in the silicon fins, respectively. In addition, excess 1/f noise in weak inversion has sometimes been observed and is ascribed to surface-roughness fluctuations. Overall, the gate oxide quality seems to be the major contributor to the LF noise and not the channel and source-drain engineering investigated here.

Advantage of Plasma Doping for Source/Drain Extension in Bulk Fin Field Effect Transistor

The impact of plasma doping (PD) on the formation of source/drain extension (SDE) is demonstrated for a p-type bulk fin field effect transistor (FinFET). The impurity distribution in a narrow fin (15 nm) was analyzed with atom probe tomography (APT) and secondary ion mass spectroscopy (SIMS). The lateral distribution of boron in the Si fin by the PD is similar to the case with conventional beam-line ion implantation (BL). However, the vertical distribution of boron by the PD is much steeper than that by the conventional BL. TCAD simulations show that the driving current of the FinFET fabricated by the PD is 34% higher than that of the FinFET fabricated by the BL under the same off-leakage current. Therefore, the PD is a key technology for fabricating the SDE of narrow bulk-FinFETs in the future.

Advantage of Plasma Doping for Source/Drain Extension in Bulk Fin Field Effect Transistor

Advantage of Plasma Doping for Source/Drain Extension in Bulk Fin Field Effect Transistor

Device Design of p+/n+ and n+/p+/n+ Gate Bulk Fin Field Effect Transistors with Source/Drain to Gate Underlap for Sub-40 nm Dynamic Random Access Memory Cell Transistors

For given gate lengths (Lg≤40 nm) and fin body widths (Wfin≤30 nm), p+/n+ and n+/p+/n+ gate bulk fin field effect transistors (FinFETs) with a source/drain to gate underlap were designed to overcome the challenges in a sub-40 nm technology node. Their characteristics were compared with those of p+ gate bulk FinFETs through three-dimensional device simulation. We concentrated on device characteristics, such as on state current (Ion), off state current (Ioff), subthreshold swing (SS), and drain-induced barrier lowering (DIBL), by controlling the overlap length of the source/drain-to-gate electrode and fin body width (Wfin). We also investigated the characteristics of p+/n+ and n+/p+/n+ gate bulk FinFETs with various n+ gate lengths (Ls's).

Comparative Study of p+/n+ Gate Modified Saddle Metal Oxide Semiconductor Field Effect Transistors and p+/n+ Gate Bulk Fin Field Effect Transistors for Sub-40 nm Dynamic Random Access Memory Cell Transistors

We present a comparative study of p+/n+ gate modified saddle metal oxide semiconductor field effect transistors (MOSFETs) and p+/n+ gate bulk fin field effect transistors (FinFETs) that have been proposed for sub-40 nm dynamic random access memory (DRAM) applications. The p+/n+ gate structure consists of polycrystalline silicon (poly-Si) with two different work functions, so that the gate-induced-drain-leakage (GIDL) current of both devices can markedly be reduced. Device characteristics were carefully investigated in terms of on/off current ratio (Ion/Ioff) and subthreshold swing (SS) by changing fin body width (Wb), and we analyzed drain current–gate voltage (I–V) characteristics and electric field profiles of a 40 nm device by controlling n+ gate length (Ls). Finally, electrical characteristics with respect to gate length (Lg) are also compared.

Threshold-Voltage Modeling of Bulk Fin Field Transistors by Considering Surface Potential Lowering

Threshold voltage (Vth) modeling of the double/triple-gate bulk fin field-effect transistors (FinFETs) was performed by considering the potential lowering at the surface of fin body at VGS=Vth condition. With decreasing gate length and/or fin width, the surface band-bending (2ψB) at VGS=Vth in fully depleted bulk FinFETs decreases since actual surface potential decreases at the Vth condition. Based on the 2ψB correction, charge-sharing length (xh) and corner factor (αc) were newly extracted. The Vth behaviors of bulk FinFETs were modeled based on the surface potential lowering, three-dimensional (3-D) charge-sharing, narrow-width effect, and corner factor. The Vth model predicted well the Vth behavior with fin body width, body doping concentration, gate length, gate height, and corner shape of the fin body. Our compact models predicted accurately Vth of the devices with the gate length up to 20 nm and the fin body width up to 5 nm.

Recessed Channel Fin Field-Effect Transistor Cell Technology for Future-Generation Dynamic Random Access Memories

A new bulk fin field-effect transistor (bulk FinFET) with a recessed channel structure is proposed as a future dynamic random access memory (DRAM) cell transistor following the recess-channel-array transistor (RCAT). An enlarged effective channel length improves the relationship between off-state channel leakage (Ioff) and gate-induced drain leakage (GIDL) current, which correspond to the static and dynamic retention characteristics of a DRAM chip. The high current drivability of FinFET is maintained even with a recessed channel. A recessed-channel FinFET (RC-FinFET) shows excellent DC characteristics (subthreshold swing, drain-induced barrier lowering and body-bias effect) and longer retention time than a conventional local-damascene FinFET (LD-FinFET).

Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions

The impact ionization behavior of bulk fin field effect transistors (FinFETs) was investigated with respect to fin body width (Wfin) and bias conditions. As fin width decreases to less than about 50 nm, the effect of parasitic source/drain series resistance becomes significant, resulting in a decrease in the impact ionization rate due to the increasing voltage drop across the resistance. We analyzed the ISUB/ID trend depending on the bias conditions (VGS=VDS and VGS=VDS/2) for devices with a Wfin thicker than 50 nm. Through two-dimensional device simulation, we showed the voltage drop and the peak electron temperature for various Wfin. It was also shown that the contact resistivity between the source/drain and the metal electrode is very important in the bulk FinFET with a very thin fin width.

Negative Bias Temperature Instability of Bulk Fin Field Effect Transistor

We investigated the negative bias temperature instability (NBTI) of bulk fin field effect transistor (FinFET) for the first time. Because bulk FinFET has a body terminal, it is more flexible in studying NBTI characteristics than a silicon on insulator (SOI) FinFET (no body terminal). The dependence of NBTI on back bias is smaller in 100 nm bulk FinFET with a fin width of 30 nm than in conventional planar channel devices. The bulk FinFET with the side surface orientation of (100) showed better NBTI than the device with the orientation of (110). The fin width variation has little impact on the NBTI of bulk FinFET. Moreover, the device with longer channel showed less degradation.