MOSFET Breakdown Research Articles

A Stochastic Framework for the Time Kinetics of Interface and Bulk Oxide Traps for BTI, SILC, and TDDB in MOSFETs

A stochastic reaction–diffusion drift model is used to simulate the time kinetics of interface and bulk oxide traps responsible for bias temperature instability (BTI), stress-induced leakage current (SILC), and time-dependent dielectric breakdown (TDDB) in MOSFETs. Trap generation and passivation are calculated using dissociation and repassivation of trap precursors and simultaneous diffusion and/or drift of atomic, molecular, and/or ionic species. The average of multiple stochastic simulations is used to qualitatively explain the measured BTI and SILC data. The difference in BTI and SILC time kinetics, variation in SILC time kinetics across reports, and oxide thickness dependence of TDDB Weibull slope variation are also qualitatively explained.

Understanding the role of threading dislocations on 4H-SiC MOSFET breakdown under high temperature reverse bias stress

The origin of dielectric breakdown was studied on 4H-SiC MOSFETs that failed after three months of high temperature reverse bias stress. A local inspection of the failed devices demonstrated the presence of a threading dislocation (TD) at the breakdown location. The nanoscale origin of the dielectric breakdown was highlighted with advanced high-spatial-resolution scanning probe microscopy (SPM) techniques. In particular, SPM revealed the conductive nature of the TD and a local increase of the minority carrier concentration close to the defect. Numerical simulations estimated a hole concentration 13 orders of magnitude larger than in the ideal 4H-SiC crystal. The hole injection in specific regions of the device explained the failure of the gate oxide under stress. In this way, the key role of the TD in the dielectric breakdown of 4H-SiC MOSFET was unambiguously demonstrated.

A Multilevel Gate Driver of SiC mosfets for Mitigating Coupling Noise in Bridge-Leg Converter

Silicon carbide (SiC) devices can significantly increase power efficiency, temperature reliability, power capacity, and power density because of their outstanding characteristics. Nevertheless, in the bridge-leg configuration of a power converter, the high-speed switching capability of SiC mosfet s is often restricted by the coupling noise between high-side mosfet and low-side mosfet . The coupling noise caused by high ${dv/dt}$ and ${di/dt}$ in switching transient will increase the switching loss and the risk of mosfet breakdown. In order to completely take advantage of the superior feature of SiC mosfet s, a novel multilevel gate driver is proposed in this article to mitigate the coupling noise effectively. Compared to the conventional gate drivers, the proposed gate driver adds a capacitor, an auxiliary mosfet , a Zener diode, and two resistors to regulate the turn- off voltage bias felicitously. In this article, the operation principle of the proposed gate driver is first introduced, to the best of our knowledge. Moreover, to obtain the circuit parameters accurately, a series of formulas have also been derived by equivalent circuit models. A 230-V/4.6-A synchronous buck converter based on SiC mosfet s is successfully experimented to verify this proposed gate driver.

Experimental Results of on-State Resistance Reduction by STI Fingers in LDMOSFET

This letter demonstrates a successful method for on-state resistance reduction up to 20% by shallow trench isolation (STI) fingers and with extra NLDD implant in the fingered region simultaneously for medium power devices. This fingered region provides a multidimensional electric field that avoids MOSFET breakdown voltage decrease, and it also shortens the drain-current conduction path. Therefore, low on-state resistance and high drain driving current is obtained in our proposed device. Careful design for structural parameters of this STI finger is needed to achieve the optimum R ON performance without hurting breakdown voltage.

System in Package (SiP) With Reduced Parasitic Inductance for Future Voltage Regulator

A system in package (SiP) that integrates high-side and low-side MOSFETs and their driver IC has been developed for voltage regulators. Compared with the conventional discrete package, the SiP offers 25% lower power loss because it has low parasitic inductances. The peak drain voltage of the low-side MOSFET during turn- on of the high-side MOSFET is 45% lower than that of the discrete package, and this improves switching noise characteristics and lowers MOSFET conduction losses because it decreases the MOSFET breakdown voltage. A mixed-mode simulation was performed that indicated the common-source parasitic inductance should be reduced in order to attain low switching loss. To reduce this common-source parasitic inductance, the source pad of the high-side MOSFET is bonded directly to the driver IC with a wire.

Study of Dopant Redistribution at the Substrate-Source/Drain p-n Junction of Nanoscale MOSFET During Progressive Breakdown

During the evolution of dielectric breakdown (BD) in MOSFETs, the substantial localized temperatures (which could exceed the silicon melting point) in the vicinity of the BD spot may cause dopants at the source/drain (S/D) to be redistributed (IEDM Tech. Dig., p. 717, 2004; IEEE Proc. IPFA, p. 131, 2005). The preliminary study of dopant redistribution based on the diode current-voltage (I-V) characteristics at the substrate-S/D p-n junction of a BD MOSFET was presented by Lim (IEEE Proc. IPFA, p. 131, 2005). The post-BD MOSFET diode current measured in the reverse bias as well as the low-voltage region of the forward bias was found to increase significantly as progressive BD evolves. The simulation results associated with the dopant redistribution are in good agreement with the experimental measurements. This confirms that the dopant redistribution is one of the dominant mechanisms responsible for the change in the post-BD MOSFET diode I-V characteristics. In addition, the dopant redistribution in a large-area long-channel BD MOSFET is found to be a function of BD location. However, the BD location dependence of the dopant redistribution will vanish in a narrow short-channel BD MOSFET

Large-signal modeling of SOI MESFETs

It has been demonstrated that sub-micron metal–semiconductor field-effect transistors (MESFETs) can be fabricated using a commercial 3.5 V silicon-on-insulator (SOI) CMOS foundry with no changes to the CMOS process flow. The SOI MESFETs demonstrate excellent RF capabilities and can operate at voltages that are at least 3X higher than the MOSFET breakdown voltage. If the high voltage capability is to be exploited in radio frequency integrated circuits it is important to develop an accurate empirical model of the device. This paper presents the SPICE model development of the SOI MESFET. A measurement-based approach is used to customize a commercially available, large-signal TOM3 MESFET model. Using the TOM3 model, an SOI MESFET Colpitts oscillator operating at 1.5 GHz has been simulated with an output swing of 7 V to illustrate the high voltage RF applications of the device.

Percolation resistance evolution during progressive breakdown in narrow MOSFETs

A method has been developed to determine the effective resistance of a conductive breakdown (BD) path formed in ultrathin gate dielectric. Based on this method, the evolution of the percolation resistance (R/sub perc/) during progressive BD (PBD) is studied in details. It is found that R/sub perc/ rapidly degrades in the initial stage of PBD with the rate of 0.1-0.2 dec/s. As PBD continues to evolve, the R/sub perc/ degradation drastically slows down, and the parasitic resistance becomes increasingly significant. In the later stage of PBD, R/sub perc/ degrades with a very slow rate, leading to the saturation of R/sub perc/. Additionally, the temperature and the voltage dependence of R/sub perc/ suggest that the mechanism responsible in governing the PBD growth under normal operations could be different from that during accelerated stressing.

Comprehensive Study of Drain Breakdown in MOSFETs

MOSFET breakdown voltage is strongly affected by the measurement conditions and the device layout. C/sub DB/,C/sub GD/,R/sub sub/, and R/sub gate/ must be extracted in order to predict the device trigger voltage under subthreshold, non-dc conditions. Substrate resistance is modeled with a simple, semi-empirical equation.

Plasma-induced micro breakdown in small-area MOSFETs

We investigated the impact of latent plasma-induced damage (PID) on the reliability of nMOSFETs with small gate area and gate-oxide thickness of 3.2 nm. To this purpose, we stressed 1500 devices with different antenna areas by using a staircase-like stress voltage and by monitoring the gate leakage at the gate voltage V/sub G/=+2 V. The stress was always stopped because of an abrupt jump in the gate current. The statistics obtained for the breakdown current are characterized by two different oxide-breakdown modes. The first is the well-known hard breakdown (HB), while the second one, which we called micro breakdown (MB), can be modeled as a double trap-assisted tunneling (D-TAT) mechanism and is characterized by a very small leakage current (around 100 pA at the gate voltage V/sub G/=2 V). In devices with large antenna, i.e., more prone to be damaged by plasma processing, the number of microbroken oxides is larger and breakdown occurs at lower voltages than in reference devices (non plasma damaged). Conversely, the hard breakdown statistics shows only a weak dependence on the gate antenna ratio of plasma damaged devices. This has been explained by considering the intrinsic nature of latent plasma-induced oxide defects, linked to the different generation mechanisms involved in micro breakdown and hard breakdown phenomena.

Breakdown and stress-induced oxide degradation mechanisms in MOSFETs

The evolution and model of breakdown mechanisms of constant-voltage stress (CVS) and constant-current stress (CCS) are investigated and compared. The results show that for both stressing methods, the transient evolution of stress current determines the breakdown. For CVS, because the stress current decreases with time, the trapped charge and interface state density increases with stress time with a T s 1/2 βλ dependence. For CCS, due to the constant trapped charge generation rate, the trapped charge and interface state increases linearly with stress time. A passing current model for CVS has been developed to explain the breakdown mechanism and its dependence on trapped charge distribution and trapped charge density.

Temperature-dependence of steady-state characteristics of SCR-type ESD protection circuits

Experimental analysis of the temperature-dependent I– V characteristics of various SCR (Silicon-Controlled Rectifier) electrostatic discharges (ESD) protection circuits have been carried out. These circuits include diode-chain-triggering SCR (DCTSCR), low-voltage zener diode trigger SCR (ZDSCR), low-voltage trigger SCR (LVTSCR) and gate-coupled low-voltage trigger SCR (GCSCR) circuits. The ZDSCR uses the zener breakdown mechanism of a reverse-biased p +–n + diode as a trigger mechanism, the DCTSCR uses the current flowing through forward-biased diode chain as a trigger mechanism, the LVTSCR uses the grounded-gate MOSFET breakdown current as the trigger mechanism and the steady-state I– V characteristics of GCSCR also uses the avalanche breakdown as a triggering mechanism. The trigger voltage can decrease or increase with increasing temperature depending upon the triggering mechanism used in the circuit, however the holding voltages of these SCRs decrease with increasing temperature.

Drain breakdown in submicron MOSFETs: a review

This paper reviews the physics and models of drain breakdown in short-channel MOSFET. Four mechanisms, namely, (1) avalanche breakdown (MI mode), (2) finite multiplication with positive feedback of the substrate current, and (3) parasitic transistor induced breakdown and (4) punchthrough, are discussed. Since the breakdown mechanisms have different dependencies on its device parameters operation conditions, the device parameters should be optimized to have better reliability margins in the down-scaled structures.

An analytical MOSFET breakdown model including self-heating effect

This paper presents an analytical breakdown model including self-heating effect (SHE) for NMOSFET devices. Model evaluation is taken for a wide ambient temperature range, from room temperature to 200°C. It is found that the device self-heating effect is suppressed when ambient temperature is increased. In addition, our results suggest that the conventional MOSFET breakdown model without considering the self-heating effect can overestimate the breakdown characteristics for the short-channel devices.

Modeling of the parasitic transistor-induced drain breakdown in MOSFETs

Parasitic bipolar transistor (PET) induced breakdown characteristics in MOSFETs are investigated and modeled with the aid of MINIMOS simulation. Formula for approximating the breakdown voltage is also developed. The proposed model agrees well with the MINIMOS simulation results, especially in the bias, temperature, and substrate resistance dependencies. According to the simulation and theoretical results, the breakdown voltage for the PET-induced breakdown can be increased by raising the temperature, increasing the channel length, and reducing the substrate resistance.

Deep-depletion-layer impact-ionization-induced gate-oxide breakdown in thin-oxide n-MOSFETs

This work extensively examines gate-oxide breakdown behaviours of n-MOSFETs by means of enhancement-type and depletion-type devices with various channel dimensions under different operation conditions. The results indicate that positive-charge accumulation in gate oxide is only one of the processes occurring during high-field stress but is not the main cause for gate-oxide breakdown. The accelerated gate-oxide breakdown in MOSFETs is initiated by interface states at the Si-SiO 2 interface, which are generated from the following process: holes created by impact ionization in the deep-depletion layer of the drain are injected into the gate oxide and trapped near the Si-SiO 2 interface; then they recombine with hot electrons crossing the interface. In addition, gate-oxide breakdown at the gate-and-drain overlap may lead to that between gate and source.

Empirical model of MOSFET breakdown voltages

An additive model of drain-to-source current of a MOS transistor in the breakdown region is presented for the circuit-simulation SPICE program. An additional drain-to-source current is described by mixed quadratic and exponential formulas. Continuity of current and its first derivatives is assured. This guarantees a convergence of the Newton-Raphson algorithm used in SPICE. Variation of the drain-to-source breakdown voltage at V/sub gs/=0 and of the injection-induced breakdown voltage at V/sub gs/>V/sub th/ with the gate-to-source voltage and the effective channel length is taken into account. Most of the model parameters have physical meanings and they are easily measurable. >

New physical model of multiplication-induced breakdown in MOSFETs : Tomasz Skotnicki, Gerard Merckel and Bderrahman Merrachi. Solid-St. Electron.34(11), 1297 (1991)

New physical model of multiplication-induced breakdown in MOSFETs : Tomasz Skotnicki, Gerard Merckel and Bderrahman Merrachi. Solid-St. Electron.34(11), 1297 (1991)

Channel width effect on MOSFET breakdown

Wide-channel MOSFETs have typically 10 to 30% lower breakdown voltages than narrow-width (W approximately=L) transistors and are less likely to exhibit clear snapback characteristics. These observations can be explained using a simplified model to determine the width dependence of the MOSFET substrate resistance. The normalized substrate current I/sub sub//W required for source turn-on predicted by this model is found to decrease by an order of magnitude for wide-channel-width transistors in agreement with measured data. This results in the observed decrease in breakdown voltage for wide-channel MOSFETs. >

New physical model of multiplication-induced breakdown in MOSFETs

The thesis of this paper is that the mechanism of multiplication-induced breakdown is essentially different from what has previously been thought. Two consecutive phases of the breakdown: enhanced body effect (EBE) and parasitic bipolar action have to be distinguished. It is shown that the difference between the EBE and the ordinary body effect results from the fact that the body effect does not involve any electrical field, whereas EBE has to account for a nonzero field in the bulk, necessary to drive the substrate current. Similarly the bipolar action may be treated in terms of a parasitic bipolar transistor, but only on condition that the variable geometry and unconventional mode of biasing of the base are taken into account. It has been found that the size of the base increases considerably with V DS. In addition, the base bias V be is not equal to V sub − V sub = R sub I sub becomes entirely constant) but rather to V sub + δΨ − V SB, where δΨ has been explicitly related to the substrate current I sub. The new physical model of multiplication-induced breakdown has been verified and confirmed according to numerical simulation results. Furthermore, the analytical predictions based on it agree very closely with measured drain and substrate current characteristics.