Bitonic Sort Research Articles

Connected Cubic Network Graph

Hypercube is a popular interconnection network. Due to the popularity of hypercube, more researchers pay a great effort to develop the different variants of hypercube. In this paper, we have proposed a variant of hypercube which is called as “Connected Cubic Network Graphs”, and have investigated the Hamilton-like properties of Connected Cubic Network Graphs (CCNG). Firstly, we defined CCNG and showed the characteristic analyses of CCNG. Then, we showed that the CCNG has the properties of Hamilton graph, and can be labeled using a Gray coding based recursive algorithm. Finally, we gave the comparison results, a routing algorithm and a bitonic sort algorithm for CCNG. In case of sparsity and cost, CCNG is better than Hypercube.

Evaluating Power and Energy Efficiency of Bitonic Mergesort on Graphics Processing Unit

Excessive power consumption is expected to be the major obstacle to achieve exascale performance within a reasonable power budget in the upcoming years. In addition, graphics processing units (GPUs) are expected to become a significant ingredient in the pursuit of exascale computing due to their fine-grained, highly parallel architecture and advancements in performance and power efficiency. To address the power obstacle of exascale systems, we suggest evaluating power and energy consumption of the fundamental software building blocks. We experimentally investigate power consumption, energy consumption, and kernel runtime of Bitonic Mergesort (a promising sort for parallel architectures) under various workloads on NVIDIA K40 GPU. The results show some insights in terms of power and energy consumption advantage of Bitonic Mergesort compared with NVIDIA’s Advanced Quicksort (a highly optimized parallel quicksort).

C2CU: a CUDA C program generator for bulk execution of a sequential algorithm

SummarySeveral important tasks, including matrix computation, signal processing, sorting, dynamic programming, encryption, and decryption, can be performed by oblivious sequential algorithms. A sequential algorithm is oblivious if an address accessed at each time does not depend on the input data. A bulk execution of a sequential algorithm is to execute it for many independent inputs in turn or in parallel. A number of works have been devoted to design and implement parallel algorithms for a single input. However, none of these works evaluated the bulk execution performance of these algorithms. The first contribution of this paper is to present a time‐optimal implementation for bulk execution of an oblivious sequential algorithm. Our second contribution is to develop a tool, named C2CU, which automatically generates a CUDA C program for a bulk execution of an oblivious sequential algorithm. The C2CU has been used to generate CUDA C programs for the bulk execution of the bitonic sorting, Floyd‐Warshall, and Montgomery modulo multiplication algorithms. Compared to a sequential implementation on a single CPU, the generated CUDA C programs for the above algorithms run, respectively, 199, 54, and 78 times faster.

Streaming Sorting Networks

Sorting is a fundamental problem in computer science and has been studied extensively. Thus, a large variety of sorting methods exist for both software and hardware implementations. For the latter, there is a trade-off between the throughput achieved and the cost (i.e., the logic and storage invested to sort n elements). Two popular solutions are bitonic sorting networks with O ( n log 2 n ) logic and storage, which sort n elements per cycle, and linear sorters with O ( n ) logic and storage, which sort n elements per n cycles. In this article, we present new hardware structures that we call streaming sorting networks , which we derive through a mathematical formalism that we introduce, and an accompanying domain-specific hardware generator that translates our formal mathematical description into synthesizable RTL Verilog. With the new networks, we achieve novel and improved cost-performance trade-offs. For example, assuming that n is a two-power and w is any divisor of n , one class of these networks can sort in n /; w cycles with O ( w log 2 n ) logic and O ( n log 2 n ) storage; the other class that we present sorts in n log 2 n /; w cycles with O ( w ) logic and O ( n ) storage. We carefully analyze the performance of these networks and their cost at three levels of abstraction: (1) asymptotically, (2) exactly in terms of the number of basic elements needed, and (3) in terms of the resources required by the actual circuit when mapped to a field-programmable gate array. The accompanying hardware generator allows us to explore the entire design space, identify the Pareto-optimal solutions, and show superior cost-performance trade-offs compared to prior work.

A Transfer-Aware Runtime System for Heterogeneous Asynchronous Parallel Execution

This paper presents a novel resource management approach for efficiently managing the computation and the data movements between the host and its accelerators in a heterogeneous platform. Our approach is based on OmpSs, with support for multi-core CPUs, GPGPUs and Maxeler Data Flow Engines based on FPGA technology; it exploits data locality, data transfer costs and data dependencies. The proposed approach is supported by an offline learning process coupled with online monitoring, allowing performance to be estimated while learning from past observations during execution. Its performance is compared against the current OmpSs scheduler using five benchmarks: matrix multiplication, bitonic sort, N-body simulation, Cholesky decomposition and AdPredictor. The results show the proposed approach can achieve up to 4.25 times speed-up for Cholesky decomposition. Moreover, an evaluation with AdPredictor indicates that the FPGA version is up to 46 times faster than the CPU version for large task sizes.

Optimized Merge Sort on Modern Commodity Multi-core CPUs

Sorting is a kind of widely used basic algorithms. As the high performance computing devices are increasingly common, more and more modern commodity machines have the capability of parallel concurrent computing. A new implementation of sorting algorithms is proposed to harness the power of newer SIMD operations and multi-core computing provided by modern CPUs. The algorithm is hybrid by optimized bitonic sorting network and multi-way merge. New SIMD instructions provided by modern CPUs are used in the bitonic network implementation, which adopted a different method to arrange data so that the number of SIMD operations is reduced. Balanced binary trees are used in multi-way merge, which is also different with former implementations. Efforts are also paid on minimizing data moving in memory since merge sort is a kind of memory-bound application. The performance evaluation shows that the proposed algorithm is twice as fast as the sort function in C++ standard library when only single thread is used. It also outperforms radix sort implemented in Boost library.

Optimizing Sorting Algorithms Using Ubiquitous Multi-core Massively Parallel GPGPU Processors

While developing naive code is uncomplicated, optimizing extremely parallel algorithms requires deep understanding of the core architecture. Recent years have witnessed a phenomenal growth in the computational capabilities and applications of GPUs. High performance of modern Graphics Processing Units may be used not only for graphics related application but also for general computing. Out of the vast applications which require parallel computing, some broadly classified are real-world applications like scientific computing, numerical simulations, healthcare, energy, data-analysis, etc. All of these applications involve wide data-intensive tasks, often subject to time constraints and space complexity. One of the fundamental issues in computer science is ordering a list of items. Bitonic sort is one of the most basic computing problems which also play a very important role in plenty of algorithms commonly used in graphics applications, such as visibility ordering or collision detection. This paper makes use of the parallel property of GPU and accelerates the function of bitonic sort which in itself is designed explicitly for parallel networks.

Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design

In many digital signal processing (DSP) applications, static random access memory (SRAM) based embedded memory and flip-flop based shift registers consume a significant portion of area and power. These DSP units are dominated by sequential memory access where SRAM-based memory or flip-flop based shift registers are inefficient in terms of area and power. We propose spintronic domain wall memory (DWM) based embedded memories for DSP building blocks such as survivor-path memories and last-in first-out (LIFO) in Viterbi decoder, first-in-first-out (FIFO) register files in FFT processor and bitonic sorter, and input register of distributed arithmetic (DA) based FIR filter that exploit the unique serial access mechanism, non-volatility and small footprint of the memory for area and power saving. Simulations using 65 nm technology show that the DWM based design achieves significant area and power savings over the conventional SRAM and spin-transfer-torque RAM (STTRAM) based design approach. For 8 k-point FFT processor and Viterbi decoder, the DWM-based design shows 60.6% (8.4%) and 66.4% ( $-$ 1.7%) area and 60.3% (44.3%) and 60.0% (37.8%) power savings over the conventional SRAM (STTRAM) based design, respectively. For DA-based FIR filter, it achieves 15.7% area and 15.5% power savings over shift register based design.

BPLG–BMCS: GPU-sorting algorithm using a tuning skeleton library

In this work, we present an efficient and portable sorting operator for GPUs. Specifically, we propose an algorithmic variant of the bitonic merge sort which reduces the number of processing stages and internal steps, increasing the workload per thread and focusing on a multi-batch execution for multiple problems of a small size. This proposal is well matched to current GPU architectures and we apply different CUDA optimizations to improve performance. For portability, we use a library based on tuning building blocks. Thanks to this parametrization, the library can easily be tuned for different CUDA GPU architectures. Our proposals obtain competitive performance on two recent NVIDIA GPU architectures, providing an improvement of up to 11,794$$\times $$? over CUDPP and up to 6467$$\times $$? over ModernGPU.

An Analysis of Hypermesh NoCs in FPGAs

Accurate analytic models for the area, delay and power of the Hypermesh NoC topology, realized with the Altera family of FPGAs, are presented. Hypermeshes are based on the concept of hypergraphs, which consist of a set of nodes and a set of hyperedges, where the hyperedges represent low-latency switches which interconnect multiple nodes with deterministic latencies. Three different switch designs for the hyperedges are proposed and evaluated. Two parallel algorithms are considered; (a) the Bitonic sorting algorithm, and (b) the FFT parallel algorithm. The analytic models are shown to be very accurate, typically within 6 percent. The 2D Hypermesh is compared to the 2D layouts of the binary hypercubes (BHC) and generalized hypercubes (GHC) in terms of area, energy per algorithm, and the Energy-Area product . The Energy-Area product is proposed as an useful design metric to evaluate NoCs, which combines both the cost and the performance metrics of an NoC into one. Our analysis indicates that the 2D Hypermeshes generally have considerably lower area, energy, and Energy-Area product compared to the 2D layouts of the Hypercubes.

Estimation of Execution Time and Speedup for Bitonic Sorting in Sequential and Parallel Enviroment

The Batcher`s bitonic sorting algorithm is one of the best parallel sorting algorithms, for sorting random numbers in modern parallel machines. Load balancing property of bitonic sorting algorithm makes it unique among other parallel sorting algorithms. Contribution of bitonic sorting algorithm can be seen in various scientific and engineering applications. Research on a bitonic sorting algorithm has been reported by various researchers in order to improve up the performance of initial batcher`s bitonic sorting algorithm. In this paper, time estimation of bitonic sort algorithm is done in both sequential as well as in parallel domain.

An optimized bitonic sorting strategy with midpoint-based dynamic communication

This paper proposes an optimized Bitonic sorting (OBS) strategy with midpoint-based dynamic communication. Our OBS strategy uses the midpoint-weight list ranking to improve complexity and reduce time of sorting on parallel and distributed systems. Applying a better key in the PE-list ranking can find the right place of (Pi, Pj) and improve communication time significantly (i.e., fewer iterations, better synchronization in each iteration, faster convergence to the result), while most of coarse-grain parallel sorting (P<N) approaches improve only a large amount of data exchange (N/P) in each of static(s(s+1)/2) iterations. Theoretically, the OBS method can reduce fixed (s(s+1)/2) iterations to 1,2,3,…, or s=log2P iterations, which are improved over those (≤s(s+1)/2 iterations) of the dynamic DCES method. In performance evaluation, sorting was accomplished on multicore machines. Experimental results showed that our optimized OBS outperforms those of the dynamic DCES about 35%–40% and those of the static LBM about 51%–54% (for N=10 to 100 million elements on an 8-multicore computer).

Reduced-Complexity k-best Decoder for LTE Standard

This paper presents a VLSI implementation of reduced -complexity and reconfigurable MIMO(Multiple-Input Multiple-Output) signal detector targeting 3GPP-LTE standard. In recent wireless communication system, MIMO technology is considered as the key technique in LTE to meet the target. Maximum Likelihood (ML) detection is the optimal detection algorithm for MIMO systems. FPGA implementation of ML detector becomes infeasible as its complexity grows exponentially with the increase in number of antennas. Therefore, we propose a modified K-best detector algorithm which employs parallel and distributed sorting strategy combined with bitonic sorter that has near-ML detection solution. The design was implemented targeting Xilinx Spartan 6 device and the resource utilization results are presented and the performance comparison with the literature was also done. The total on-chip power estimated is 213mW.

Bitonic Sorting Algorithm: A Review

Batchers bitonic sorting algorithm is a parallel sorting algorithm, which is used for sorting the numbers in modern parallel machines. There are various parallel sorting algorithms such as radix sort, bitonic sort, etc. It is one of the efficient parallel sorting algorithm because of load balancing property. It is widely used in various scientific and engineering applications. However, Various researches have worked on a bitonic sorting algorithm in order to improve up the performance of original batchers bitonic sorting algorithm. In this paper, tried to review the contribution made by these researchers.

Implementation of a High-Throughput Modified Merge Sort in MIMO Detection Systems

Wireless communication technology continues to advance at a rapid pace, and researchers have made tremendous progress in extending single-input single-output (SISO) systems to multiple-input multiple-output (MIMO) systems such as IEEE 802.11n, WiMAX, and LTE. However, a MIMO system requires a detector circuit to separate received data. To reduce the number of comparators required, the method of modified merge sort is proposed, and the results are compared with those of five sorting algorithms. This modified merge sort requires approximately 56% fewer comparators than a bitonic merge sort and approximately 46% fewer comparators than an odd-even merge sort. When implemented in a TSMC 0.18-μm process, the proposed chip demonstrates a throughput of up to 1200 Mbps at an operating frequency of 150 MHz.

A GPU-based parallel method for evolutionary tree construction

Evolutionary trees are widely applied in various applications to show the inferred evolutionary relationships among species or entities. Neighbor-Joining is one solution for data-intensive and time-consuming evolutionary tree construction, with polynomial time complexity. However, its performance becomes poorer with the growth of massive datasets. Graphics Processing Units (GPUs) have brought about new opportunities for these time-consuming applications. Based on its high efficiency, a GPU-based parallel Neighbor-Joining method is proposed, and two efficient parallel mechanisms, data segmentation with asynchronous processing and the minimal chain model with bitonic sort, are put forward to speed up the processing. The experimental results show that an average speedup of 25.1 is achieved and even approximately 30 can be obtained with a sequence dataset ranging from 16,000 to 25,000. Moreover, the proposed parallel mechanisms can be effectively exploited in some other high performance applications.

Интеграция алгоритма параллельной сортировки Бэтчера и активной системы хранения данных

This paper describes a modified parallel Batcher sort algorithm for big data processing. The main novelty of implemented sort algorithm is to integrate effective parallel batcher sort and Active Storage concept. We use Active Storage based on Lustre File System and TSim C++ template library for parallelization. This paper presents experimental testing results for scientific processing real seismic data. Presented results indicate that described algorithm can reach linear acceleration on sorting big data sets (More then 100 Gb).

Bitonic sort on a chained-cubic tree interconnection network

Bitonic sort is one of the fastest oblivious parallel sorting algorithms known so far. Due to its high modularity, bitonic sort can be mapped to different interconnection networks. In this paper, the bitonic sort algorithm is mapped to the chained-cubic tree (CCT) interconnection network. It is shown that the computation time of the bitonic sort on a CCT (BSCCT) algorithm is O((n/p)×log(np)) and that the communication cost is O(plog2p), assuming that n keys are evenly distributed among p processors that comprise a given CCT network. Simulation is implemented and used to assess the performance of the BSCCT algorithm in terms of computation time, communication cost, message delay, and key comparisons. Simulation results showed that the BSCCT algorithm achieves a speedup that is almost 12-fold relative to a bitonic sort on a single processor, when 1024 processors were used to sort 32M keys.

Parallel bucket sorting on graphics processing units based on convex optimization

We found an interesting relation between convex optimization and sorting problem. We present a parallel algorithm to compute multiple order statistics of the data by minimizing a number of related convex functions. The computed order statistics serve as splitters that group the data into buckets suitable for parallel bitonic sorting. This led us to a parallel bucket sort algorithm, which we implemented for many-core architecture of graphics processing units (GPUs). The proposed sorting method is competitive to the state-of-the-art GPU sorting algorithms and is superior to most of them for long sorting keys.

Efficient sorting design on a novel embedded parallel computing architecture with unique memory access

Embedded Parallel computing architecture with Unique Memory Access (ePUMA) is a domain-specific embedded heterogeneous 9-core chip multiprocessor, which has a unique design with low power and high silicon efficiency for high-throughput DSP in emerging telecommunication and multimedia applications. Sorting is one of the most widely studied algorithms, more embedded applications also need efficient sorting. This paper proposes an efficient bitonic sorting algorithm eSORT for the novel ePUMA DSP. eSORT algorithm consists of two parts: an in-core sorting algorithm and an intra-core sorting algorithm. Both algorithms are adapted to the novel architecture and take advantage of the ePUMA platform. This paper implemented and evaluated the eSORT for variable datasets on ePUMA multi-core DSP and compared its performance with the Cell BE processors with the same SIMD parallelization structure. Results show that bitonic sort on ePUMA multi-core DSP has much better performance and scalability. Compared with optimized bitonic sort on Cell BE, the in-core sort is 11 times faster and intra-core sort is 15 times faster in average.