Bitonic Sort Research Articles

Utilization of Two Cross Two Switch for Bitonic Sorting Circuit

Utilization of Two Cross Two Switch for Bitonic Sorting Circuit

Single-Instruction-Multiple-Data Instruction-Set-Based Heat Ranking Optimization for Massive Network Flow

In order to cope with the massive scale of traffic and reduce the memory overhead of traffic statistics, the traffic statistics method based on the Sketch algorithm has become a research hotspot for traffic statistics. This paper studies the problem of the top-k flow statistics based on the Sketch algorithm and proposes a method to estimate the flow heat from massive network traffic using the Sketch algorithm and identify the kth flow with the highest heat by using a bitonic sort algorithm. In view of the performance difficulties of applying multiple hash functions in the implementation of the Sketch algorithm, the Single-Instruction-Multiple-Data (SIMD) instruction set is adopted to improve the performance of the Sketch algorithm so that SIMD instructions can process multiple fragments of data in a single step, implement multiple hash operations at the same time, compare and sort multiple flow tables at the same time. Thus, the throughput of the execution task is improved. Firstly, the elements of data flow are described and stored in the form of vectors, while the construction, analysis, and operation of data vectors are realized by SIMD instructions. Secondly, the multi-hash operation is simplified into a single vector operation, which reduces the CPU computing resource consumption of the Sketch algorithm. At the same time, the SIMD instruction set is used to optimize the parallel comparison operation of the flow table in a bitonic sort algorithm. Finally, the SIMD instruction set is used to optimize the functions in the Sketch algorithm and top-k sorting algorithm program, and the optimized code is tested and analyzed. The experimental results show that the time consumed by the advanced vector extensions (AVX)-instructions-optimized version has a significant reduction compared to the original version. When the length of KEY is 96 bytes, the instructions consumed by multiple hash functions account for less in the entire Sketch algorithm, and the time consumed by the optimized version of AVX is about 67.2% of that in the original version. As the length of KEY gradually increases to 256 bytes, the time consumed by the optimized version of AVX decreases to 53.8% of the original version. The simulation results show that the AVX optimization algorithm is effective in improving the measurement efficiency of network flow.

Investigating the effect of varying block size on power and energy consumption of GPU kernels

Power consumption is likely to remain a significant concern for exascale performance in the foreseeable future. In addition, graphics processing units (GPUs) have become an accepted architectural feature for exascale computing due to their scalable performance and power efficiency. In a recent study, we found that we can achieve a reasonable amount of power and energy savings based on the selection of algorithms. In this research, we suggest that we can save more power and energy by varying the block size in the kernel configuration. We show that we may attain more savings by selecting the optimum block size while executing the workload. We investigated two kernels on NVIDIA Tesla K40 GPU, a Bitonic Mergesort and Vector Addition kernels, to study the effect of varying block sizes on GPU power and energy consumption. The study should offer insights for upcoming exascale systems in terms of power and energy efficiency.

Design of High-Speed Multiway Merge Sorting Networks Using Fast Single-Stage N-Sorters and N-Filters

In hardware such as FPGAs, Kenneth Batcher&#x2019;s Odd-Even Merge Sort and Bitonic Merge Sort are the state-of-the-art methodologies used to quickly sort a list of more than 16 input values. Both sorting networks feature merges of 2 sorted input lists into a single sorted output list. For both, a full sort of 64 and 512 input values requires 21 and 45 serial stages, respectively. Multiway merge sorting networks described here require significantly fewer serial stages. For example, 8-way merge networks fully sort 64 and 512 input values in 9 and 20 serial stages, less than half the number of the respective 2-way networks. When the multiway merge sorting networks utilize the single-stage <i>N</i>-sorters recently defined by the authors, they are considerably faster than Batcher&#x2019;s networks. In the AMD-Xilinx Ultrascale+ xcvu9p FPGA, the two 8-way merge networks have speedups of 1.85 and 1.74 versus the comparable 2-way networks. A fully pipelined 3-way merge network in this FPGA is capable of fully sorting 500 million lists of 729 unsorted 32-bit values in one second. In software, multiway merge methods are used to find the median of certain pixel rectangles in images, since the median can be determined in fewer stages than are required to fully sort the rectangle. However, the software still requires a series of many 2-sorter operations to find a median. These multiway merge median methods are dramatically sped up in hardware, where the authors&#x2019; new single-stage <i>N</i>-sorters and <i>N</i>-filters operate in parallel in each stage of the merge process.

A fast vectorized sorting implementation based on the ARM scalable vector extension (SVE).

The way developers implement their algorithms and how these implementations behave on modern CPUs are governed by the design and organization of these. The vectorization units (SIMD) are among the few CPUs’ parts that can and must be explicitly controlled. In the HPC community, the x86 CPUs and their vectorization instruction sets were de-facto the standard for decades. Each new release of an instruction set was usually a doubling of the vector length coupled with new operations. Each generation was pushing for adapting and improving previous implementations. The release of the ARM scalable vector extension (SVE) changed things radically for several reasons. First, we expect ARM processors to equip many supercomputers in the next years. Second, SVE’s interface is different in several aspects from the x86 extensions as it provides different instructions, uses a predicate to control most operations, and has a vector size that is only known at execution time. Therefore, using SVE opens new challenges on how to adapt algorithms including the ones that are already well-optimized on x86. In this paper, we port a hybrid sort based on the well-known Quicksort and Bitonic-sort algorithms. We use a Bitonic sort to process small partitions/arrays and a vectorized partitioning implementation to divide the partitions. We explain how we use the predicates and how we manage the non-static vector size. We also explain how we efficiently implement the sorting kernels. Our approach only needs an array of O(log N) for the recursive calls in the partitioning phase, both in the sequential and in the parallel case. We test the performance of our approach on a modern ARMv8.2 (A64FX) CPU and assess the different layers of our implementation by sorting/partitioning integers, double floating-point numbers, and key/value pairs of integers. Our results show that our approach is faster than the GNU C++ sort algorithm by a speedup factor of 4 on average.

NOP-DH – Evaluation Over Bitonic Sort Algorithm

The growing use of Field Programmable Gate Array (FPGA) to increase application performance requires tools that simplify the digital circuit development process. Traditional approaches of Hardware Description Languages (HDLs) are complex and require specialized knowledge at a low-level abstraction. In turn, different approaches called High-Level Synthesis (HLS) aim at facilitating the development of FPGA applications, making this development process closer to those of software using programming languages such as C or C++. However, these alternatives do not properly exploit the parallelism capability of FPGAs as they are based on usual sequential approaches and, moreover, continue to depend on developer technical knowledge about the target hardware. The Notification Oriented Paradigm (NOP) emerges as an alternative to develop and execute applications. The NOP brings a new inference concept based on precise notifying collaborative entities. This type of inference allows presenting an innovative way of implicitly achieving decoupled and decentralized solutions, thereby enabling parallelism and distribution in a level of granularity as fine as possible in the envisaged computational platform. In this context, researches on NOP have proposed the design of digital circuits based on the NOP model, called NOP Digital Hardware (DH). In this paper, it is proposed to evaluate the use of the NOP-DH to develop the well-known Bitonic Sort, which is a sort algorithm useful as benchmark. This algorithm has particular properties that are advantageous for parallel execution, especially in FPGAs. Experiments were performed to compare the performance, amount of logic elements, and maximum frequency of NOP-DH against the traditional VHDL approach. These experiments demonstrated that even with a higher abstraction level of development, NOP-DH circuits achieve similar results when compared to the traditional development in VHDL.

Analog circuit implementation based on median filter for salt and pepper noise reduction in image

In this study, an analog circuit design instead of using a software is utilized to remove Salt and Pepper (S&P) noise in image. For this purpose, a digital image filtering method which is called median filter is carried out. In median filter method, a current-mode nine-input one-output circuit architecture is preferred since 3 × 3 filtering mask is employed. Median filter circuit is based on a modified bitonic sort network and consists of 26 max/min selector circuits. A current-mode two-input two-output circuit is designed as a max/min selector and there is no biasing current source in the max/min selector structure. In analysis part, two 150 × 150 images with different amount of S&P noise are used and the noise in image is successfully reduced with the help of the proposed circuit design. The performance of the suggested median filter is also verified through the quality measurement parameters such as Structural Similarity Index Metric, Mean Squared Error, Mean Absolute Error and Peak Signal to Noise Ratio. TSMC CMOS 0.18 µm process model is utilized to simulate the introduced median filter circuit.

Federated Data Cleaning: Collaborative and Privacy-Preserving Data Cleaning for Edge Intelligence

As an important driving factor of emerging Internet-of-Things (IoT) applications, machine learning algorithms are currently facing the challenge of how to “clean” data noise, that is introduced during the training process (e.g., asynchronous execution and lossy data compression and quantization). In an attempt to guarantee data quality, various data cleaning approaches have been proposed to filter out abnormal data entries based on the global data distribution. However, most existing data cleaning approaches are based on a centralized paradigm and thus cannot be applied to future edge-based IoT applications, where each edge node (EN) has only a limited view of the global data distribution. Moreover, the increasing demand for privacy preservation largely prevents ENs from combining their data for centralized cleaning. In this study, we propose a federated data cleaning protocol, coined as FedClean, for edge intelligence (EI) scenarios that is designed to achieve data cleaning without compromising data privacy. More specifically, different ENs first generate Boolean shares of their data and distribute them to two noncolluding servers. These two servers then run the FedClean protocol to privately and efficiently compute the attribute value frequency (AVF) scores of the collected data entries, which are then sorted in ascending order via a bitonic sorting network without revealing their values. As a result, data entries with lower AVF scores are considered as abnormal and filtered out. The security, efficiency, and effectiveness of the proposed approach are then demonstrated via concrete security analysis and comprehensive experiments.

An O(1) time complexity sorting network for small number of inputs with hardware implementation

The sorting algorithms have found applications in various research fields including image and video processing. High speed sorting is important in real-time applications, such as real-time image processing. Two properties are criterion for sorting networks: the number of steps (speed) and the number of comparators (efficiency). In this paper, we have proposed a method to decrease the number of steps. We introduce a new method for sorting an unordered sequence, which is based on the graph theory concept,and contrary to the conventional sorting networks, it consists of graph edge calculators rather than compare-and-swaps. An outstanding feature of the proposed method is that for small number of inputs, its number of steps is independent of the number of inputs that denotes it orders N inputs in O(1) steps. Moreover, the proposed method surpasses the previous ones in term of speed; it just needs two steps to sort a sequence. In the first step, all the inputs are compared with each other, and in the second step, the results of comparisons direct the inputs to the right outputs. To justify the functionality, the proposed method is simulated with the Modelsim-Altera and implemented on a Cyclone IV FPGA platform. Simulation results indicate that in comparison with the Bather's Bitonic mergesort, which is known to be the fastest algorithm, the proposed method while requires 80% more LEs, consumes 52% less memory and achieves 73% more throughput. Furthermore, the Bitonic mergesort can only accept a power of 2 number of inputs, while the proposed method does not hold such a limitation.

Implementing bitonic sorting on optical network-on-chip with bus topology

Optical network-on-chip (ONoC) is a new designing of multi-processor system-on-chip. On the one hand, global bus is a simple and common logical topology for ONoC. On the other hand, the parallel formulation of bitonic sorting has lower time complexity than the sequential implementation of bitonic sorting. Thus, it is meaningful to study the parallel implementation for bitonic sorting on bus ONoC. Different wavelengths are used to achieve the parallel processing for bitonic sorting on bus ONoC. The wavelength assignment scheme for n elements bitonic sorting is proposed such that the number of wavelengths required is just n/2.

VLSI Architecture for Enhanced Approximate Message Passing Algorithm

Compressed sensing (CS) enables the reconstruction of sparse signals from a small number of linear measurements. However, sparse signal recovery algorithms require significant computational effort, even for problems of moderate size, and make their hardware realization a highly challenging task. In this paper, we present a novel architecture for the reconstruction of the sparse signal using the recently proposed Enhanced Approximate Message Passing (EAMP) algorithm. The EAMP algorithm shows better performance in terms of convergence rate and sparsity measurement trade-off as compared to AMP, IST and IHT techniques. The execution time of the proposed design has been reduced by maximizing parallelism with an appropriate level of unfolding. It receives CS measurements (y) and the number of non-zero elements (K) in the input vector from the encoder. Depending on the value of K, one sensing matrix (Φ j ) is selected from the code book Φ. The reconstruction algorithm (EAMP) recovers the input vector (s) by using y and Φ. Bitonic sorting has been used to identify the thresholding value in the EAMP algorithm. The proposed architecture for EAMP algorithm has been synthesized using Synopsys design compiler with 65 nm technology CMOS standard cell libraries. It occupies 719.15 KGE and consumes 315.5 mW power at a frequency of 400 MHz. It is suitable for any arbitrary sparsity-based signal restoration and CS problems.

A Hybrid Pipelined Architecture for High Performance Top-K Sorting on FPGA

We present a hybrid pipelined sorting architecture capable of finding and producing as its output the K largest elements from an input sequence. The architecture consists of a bitonic sorter and L cascaded sorting units. The sorting unit is designed to output P elements during every cycle with the aim of increasing the throughput and lowering the latency. The function of the bitonic sorter is to generate a segmented ordered sequence. The sorting unit processes this sequence to identify and output the P largest elements. Hence, the K=PL largest elements are obtained after the segmented ordered sequence proceeds through L cascaded sorting units. Variable-length and continuous sequences are supported by the proposed sorting architecture. The results of the implementation show that the sorting architecture can achieve a throughput of 22.88 GB/s with P=16 on a state-of-the-art Field Programmable Gate Array (FPGA).

RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using a Multidimensional Sorting Algorithm

This paper proposes a novel hardware-based multidimensional sorting algorithm and its respective architecture, called real-time hardware sorter (RTHS), for emerging data intensive processing applications where performance and resource conservation are serious concerns. The basic idea behind RTHS is to reduce the hardware complexity of parallel hardware sorting architectures (PHSAs) through a high-performance scalable matrix-based sorting method. The proposed method can also be used for implementing Min/Max queues or finding the largest/smallest records exclusively in the big data application. Implementing the RTHS design on a Virtex-7 field-programmable gate array (FPGA) reveals that the number of lookup tables (LUTs) of the proposed method has decreased by 66.3% and 87.3% compared to the conventional Bitonic sorting network (CBSN) and the state-of-the-art PHSA, respectively. In addition, the number of required registers for the proposed method has decreased by 94.8% compared to the state-of-the-art PHSA.

Design of a Novel Query System for Social Network

User intention and nature of network plays a vital role towards the quality of response received as the result of any user query. Therefore, the need of system understanding the user's intent and network dynamism as well is highly apparent. The proposed query processing and analysing system (QPAS) for social networks is based on extracting user's intent from various social networks using existing NLP techniques. It fetches the information and further employs hybrid ensemble k-means hierarchical agglomerative clustering (HEKHAC) and modified Bitonic sort to improve the responses. The proposed approach offers an edge over other mechanisms as it not only retrieves more user-centric results as compared to traditional way of keyword-based searching but also in timely manner as well. It is an innovative approach to investigate the new aspects of social network. The proposed model offers a noteworthy revolution scoring up to precision and recall respectively.

A Study of Integer Sorting on Multicores

Integer sorting on multicores and GPUs can be realized by a variety of approaches that include variants of distribution-based methods such as radix-sort, comparison-oriented algorithms such as deterministic regular sampling and random sampling parallel sorting, and network-based algorithms such as Batcher’s bitonic sorting algorithm. In this work we present an experimental study of integer sorting on multicore processors. We have implemented serial and parallel radix-sort for various radixes, deterministic regular oversampling, and random oversampling parallel sorting, including new variants of ours, and also some previously little explored or unexplored variants of bitonic-sort and odd-even transposition sort. The study uses multithreading and multiprocessing parallel programming libraries with the same C language code working under Open MPI, MulticoreBSP, and BSPlib. We first provide some general high-level observations on the performance of these implementations. If we can conclude anything is that accurate prediction of performance by taking into consideration architecture dependent features such as the structure and characteristics of multiple memory hierarchies is difficult and more often than not untenable. To some degree this is affected by the overhead imposed by the high-level library used in the programming effort. Another objective is to model the performance of these algorithms and their implementations under the MBSP (Multi-memory BSP) model. Despite the limitations mentioned above, we can still draw some reliable conclusions and reason about the performance of these implementations using the MBSP model, thus making MBSP useful and usable.

Design space exploration of multi-core RTL via high level synthesis from OpenCL models

As more and more powerful integrated circuits are appearing on the market, more and more applications, with very different requirements and workloads, are making use of available computing power. Designing optimized accelerators that can meet particular requirements has always presented a tremendous challenge to hardware engineers. To do so, designers have to trade off performance for power consumption in a manner such that the final RTL consumes minimum energy to meet the required performance (e.g. FLOPS) target. Moreover, the growing trend towards heterogeneous platforms is crucial to meet time and power consumption constraints of high-performance computing (HPC) applications. The OpenCL parallel programming language and framework enables programming CPU, GPU and recently FPGAs using the high-level synthesis (HLS) methodology. This work presents a design space exploration flow based on execution time, resource utilization and power consumption of OpenCL kernels mapped on FPGAs using the Xilinx high-level synthesis tool chain. Our experiments suggest that the quality of generated solutions, in terms of performance-per-watt, can be determined using analytical formulas prior to implementation, thus enabling fast and accurate DSE by considering on-chip and off-chip sources of parallelism. Moreover, the automated flow suggests design hints to meet a given time constraint within available resources. The proposed technique is demonstrated by optimizing the well known bitonic sorting network from NVIDIA’s OpenCL benchmark. Our results report that FPGAs have at least 20% higher performance-per-watt with respect to two high-end GPUs manufactured in the same technology (28 nm). Additionally, FPGAs with more available resources and using a more modern process (20 nm) can outperform the tested GPUs while consuming at least 55% less power at the cost of more expensive devices.

The Half Cleaner Lemma: Constructing Efficient Interconnection Networks from Sorting Networks

In general, efficient non-blocking interconnection networks can be derived from sorting networks, and to this end, one may either follow the merge-based or the radix-based sorting paradigm. Both paradigms require special modifications to handle partial permutations. In this article, we present a general lemma about half cleaner modules that were introduced as building blocks in Batcher’s bitonic sorting network. This lemma is the key to prove the correctness of many known optimizations of interconnection networks. In particular, we first show how to use any ternary sorter and a half cleaner for implementing an efficient split module as required for radix-based sorting networks for partial permutations. Second, our lemma formally proves the correctness of another known optimization of the Batcher-Banyan network.

Analyzing Power and Energy Efficiency of Bitonic Mergesort Based on Performance Evaluation

In graphics processing unit ( GPU ) computing community, bitonic mergesort (BM) is recognized as one of the most investigated sorting algorithms. It is specially designed for parallel architectures, requires minor inter-process communication, can be implemented in-place, and is logically appropriate for single instructions multiple data platforms. In addition, GPUs have shown tremendous improvements in power and performance efficiency and thus have become essential ingredients in pursuit of the prospective exascale systems whose major obstacle is the excessive power consumption. In a recent research work, we found that fundamental software building blocks can offer a reasonable amount of power and energy saving that can offer new ways to tackle the power obstacle of the prospective exascale systems. We evaluated average peak power , average energy , and average kernel runtime of BM under various workloads and compared it with advanced quicksort (AQ) . The results showed that BM outperformed AQ based on all the three metrics in most cases. In this paper, we further investigate BM to identify the factors that result in its underlying power and energy efficiency advantage over AQ. We analyze the power and energy efficiency of BM and AQ based on their performance evaluation on NVIDIA K40 GPU. The performance of both the algorithms is investigated using various experiments offered by NVIDIA Nsight Visual Studio .

Efficient Sorting Architecture for List-Fast-SSC Decoding of Polar Codes

Polar codes have been proven to achieve the symmetric capacity of memoryless channel. Compared with a successive cancellation list decoder, list-Fast simplified-successive cancellation generates more candidate paths, which leads to more resource costs and higher decoding latency. To remedy this drawback, we present a simplified sorting architecture. An $M*L$ ordered candidate path matrix is constructed by preliminary sorter, where $M$ and $L$ denote the number of candidate path expanded by one constituent code and the list size of the decoder, respectively. Then, we eliminate the candidate paths that are definitely not in the $L$ best paths by the proposed lossless pruning algorithm. Finally, a compatible sorting network combining the advantages of bitonic sorter and odd–even sorter is proposed. Numerical results show that for $L=32$ and $M=8$ , the proposed architecture can reduce 66.7% of candidate paths and save 52.3% of compare and swap units (CASUs) and 25% of CASU stages compared with the odd–even sorter.

Computer Generation of High Throughput and Memory Efficient Sorting Designs on FPGA

Accelerating sorting using dedicated hardware to fully utilize the memory bandwidth for Big Data applications has gained much interest in the research community. Recently, parallel sorting networks have been widely employed in hardware implementations due to their high data parallelism and low control overhead. In this paper, we propose a systematic methodology for mapping large-scale bitonic sorting networks onto FPGA. To realize data permutations in the sorting network, we develop a novel RAM-based design by vertically “folding” the classic Clos network. By utilizing the proposed design for data permutation, we develop a hardware generator to automatically build bitonic sorting architectures on FPGAs. For given input size, data width and data parallelism, the hardware generator specializes both the datapath and the control unit for sorting and generates a design in high level hardware description language. We demonstrate trade-offs among throughput, latency and area using two illustrative sorting designs including a high throughput design and a resource efficient design. With a data parallelism of p (2 ≤ p ≤ N/2), the high throughput design sorts an N-key sequence with latency 6N=p + o(N), throughputp results per cycle and uses 6N + o(N) memory. This achieves optimal memory efficiency (defined as the ratio of throughput to the amount of on-chip memory used by the design) and outperforms the state-of-the-art. Experimental results show that the designs obtained by our proposed hardware generator achieve 49 to 112 percent improvement in energy efficiency and 56 to 430 percent higher memory efficiency compared with the state-of-the-art.