Bit-serial Multiplier Research Articles

GF(2m) multiplication over triangular basis for design of Reed-Solomon codes

Bit-serial and bit-parallel multiplication architectures for GF(2m) are presented, using a triangular basis representation of field elements. The paper is a development of the work originally presented by Hasan and Bhargava. It is shown that, by forcing these multipliers to operate entirely over the triangular basis, lower latency delays and hardware savings can be made. Also, a more flexible definition of the triangular basis is presented, which allows a number of triangular bases to any given basis to be defined. It is shown that when the defining irreducible polynomial is a trinomial, the triangular basis is a simple permutation of the polynomial basis elements. Furthermore, if the defining irreducible polynomial is a pentanomial of a certain form the triangular basis to polynomial basis conversion requires minimal hardware and a reordering of basis coefficients.

On-Line Error Detection for Bit-Serial Multipliers in GF(2m)

In this paper error detection is applied to four finite field bit-serial multipliers. It is shown that by using parity prediction, on-line error detection can be incorporated into these multipliers with very low hardware overheads. These hardware overheads are generally independent of m and comprise only a handful of gates, so for large values of m these overheads are particularly low. The fault coverage of the presented structures has been investigated by simulation experiment and shown to range between 90% and 94.3%.

A real-time systolic integer multiplier

We describe the construction of two practical real-time systolic bit-serial multipliers: a pipelined multiplier and a nonpipelined multiplier. Our non-pipelined multiplier requires roughly half the...

A real-time systolic integer multiplier

We describe the construction of two practical real-time systolic bit-serial multipliers: a pipelined multiplier and a nonpipelined multiplier. Our non-pipelined multiplier requires roughly half the hardware (number of full-adders) as compared to Atrubin's multiplier, which is the best real-time systolic multiplier known to-date. Our starting point is a serial/parallel multiplier which is not systolic, has a large number of primary inputs and does not support pipelining. We modify this design step by step using systematic methodologies until our design is obtained. The methodologies used in the design are: broadcast elimination, replacing parallel inputs with a broadcast mechanism and adding a simplified version of the circuit in order to enable pipelining. Applying these methodologies yields an improved circuit the correctness of which is easily understood.

Bit-serial multiplication in GF(2m) using irreducible all-one polynomials

Two architectures for carrying out bit-serial multiplication in GF(2m) are presented where the defining irreducible polynomial for the field is an all-one polynomial. The multipliers presented have low hardware requirements, regular structures and are therefore suitable for VLSI implementation.

Systolic digital filters with reduced latency—serial implementation

Schemes that implement finite impulse response (FIR) and infinite impulse response (IIR) digital filters when bit-serial or digit-serial arithmetic is used are proposed in this paper. The main objective is to obtain reduced latency (minimal latency at the word level) of the filter outputs while maintaining the word rate. Existing schemes (systolic or not) for filters are transferred down to the digit level and regular structures systolic at the bit or digit level are proposed. First a modified representation of a digital filter signal flow-graph appropriate for bit-serial or digit-serial arithmetic is presented. Next we show how the resulting flow-graph can be transformed to lead directly to a systolic implementation at the bit or word level. We aim towards minimizing the latency of the filter response. For this reason we work with bidirectional signal flow-graphs that lead to systolic arrays where data and partial results move in opposite directions, otherwise called two-way pipeline systolic arrays. The multipliers that are used in the implementation of the filters must have low latency themselves. For this reason they have the same two-way pipeline structure. In order to maintain the data word rate, the full-bit output of a multiplier must be rounded by a number of bits equal to the length of the data words. We propose a composite bit-serial multiplier that performs this rounding while preserving low latency and incorporate it in schemes for direct implementation of low-latency high-throughput systolic arrays for FIR and IIR digital filters. These schemes for bit-serial multipliers and filters are also extended to digit-serial arithmetic.

Bit-serial Berlekamp-like multipliers for GF (2 m )

A bit-serial multiplier for GF(2m) is presented. This multiplier operates in a similar way to the traditional Berlekamp multiplier and has the same hardware requirements. However the format of the inputs to the proposed multiplier is different, and in some circumstances constant multipliers based on this approach can be clocked faster than those based on the traditional Berlekamp multiplier.

A class of systolic serial-parallel multipliers

A scheme for a fully-systolic bit-serial multiplier is presented, based on merging two adjacent cells of an existing semi-systolic multiplier in a single new cell. The multiplier has immediate response and high bit-throughput, limited by the propagation delay of one gated full adder and a latch. A way to increase the word-throughput, while retaining systolicity, is also presented.

Bit-serial multipliers and squarers

Traditional bit-serial multipliers present one or more clock cycles of data-latency. In some situations, it is desirable to obtain the output after only a combinational delay, as in serial adders and subtracters. A serial multiplier and a squarer with no latency cycles are presented here. Both accept unsigned or sign-extended two's complement numbers and produce an arbitrarily long output. They are fully modular and thus good candidates for introduction in VLSI libraries. >

VLSI structures for bit-serial modular multiplication using basis conversion

This paper proposes design techniques for the efficient VLSI implementation of bit-serial multiplication over a modulus. These techniques reduce multiplication into simple cyclic shifts, where the number representation of the data is chosen appropriately. This representation will, in general, be highly redundant, implying a relatively poor throughput for the multiplier. It is then shown how, by splitting the multiplier into two pipelined multipliers, the throughput of the unit can be increased, whilst still retaining a cyclic-shift implementation. The split multiplier requires a mid-computation basis conversion, and the two number representations, used within the unit, are only moderately redundant. Thus, high-throughput, bit-serial multipliers are achieved, with most of the complexity contained within systolic basis converter modules. The multipliers are applicable to the VLSI implementation of high-throughput, signal processing operations performed over finite fields, in particular, transform and filter operations.

Bit-serial multiplier based on Josephson latching logic

The authors have designed, fabricated, and tested a Josephson bit serial multiplier based on voltage latching logic. The bit serial implementation takes advantage of high-speed characteristics of Josephson circuits to achieve higher circuit functionality per gate by reducing gate complexity. To facilitate the multiplier design, logic simulation was performed using transistor-transistor-logic (TTL) equivalent gate models of voltage latching modified-variable-threshold-logic (MVTL) gates. A 4-b serial-parallel multiplier based on MVTL gates has been designed and fabricated in niobium. The basic timed-XOR and full adder circuits used in the multiplier were successfully tested. Preliminary testing of the multiplier indicated inadequate operating margin for a full functional test.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Division and bit-serial multiplication over GF(qm)

Division and bit-serial multiplication in finite fields are considered. Using co-ordinates of the supporting elements it is shown that, when field elements are represented by polynomials, division over GF(qm) can be performed by solving a system of m linear equations over GF(q). For a canonical basis representation, a relationship between the division and the discrete-time Wiener-Hopf equation of degree m over GF(q) is derived. This relationship leads to a bit-serial multiplication scheme that can be easily realised for all irreducible polynomials.

High-performance bit-serial adders and multipliers

A design methodology is presented which uses clocked logic modules to synthesise flexible high performance multipliers. By using two-stage pipelined bit-serial adders, a bit-serial multiplier can be designed which is capable of producing both single- and double-precision products for continuous two&apos;s complement data streams. High processing speeds are possible owing to the systolic structure which is pipelined at the gate level.

Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors

The use of bitand digit-serial arrays in digital designs is attractive, because of the large savings in chip area that are possible with such designs as well as the comparative ease with which such designs can be conceived and fabricated. These arrays are used extensively in digital signal processing applications and are part of circuits generated by silicon compilers. A number of bitand digit-serial architectures have been proposed by Jasica et al. [l], Scanlon and Fuchs [2], Kanopoulos [3], Lyon [4], Denyer and Renshaw [5], and Hartley and Corbett [6]. Test generation for such arrays is a difficult problem due to the presence of internal system states that are neither directly controllable nor observable. The erroneous system states can mask errors activated by a test sequence unless the test sequence is carefully designed for the bitand digit-serial array to be tested. Breuer [7] studied the problem of fault detection in linear cascades of identical machines. He derived strong necessary and sufficient conditions for such cascades to be testable by two or three uniform (preset) experiments. Test sequences for two bit-serial multipliers are presented by Davis et al. [8]. An ad hoc procedure based on exhaustive simulation of all faulty truth tables of a full adder

On bit-serial multiplication and dual bases in GF(2/sup m/)

The existence of certain types of dual bases in finite fields GF(2/sup m/) is discussed. These special types of dual bases are needed for efficient implementation of (generalized) bit-serial multiplication in GF(2/sup m/). In particular, the question of choosing a polynomial basis of GF(2/sup m/), for example (1, alpha , alpha /sup 2/, alpha /sup 3/, . . ., alpha /sup m-1/), such that the change of basis matrix from the dual basis to a scalar multiple of the original basis has as few '1' entries as possible, is studied. It was previously shown by M. Wang and I. F. Blake (1990) that the optimal situation occurs when the minimal polynomial of alpha is an irreducible trinomial of degree m; then, an appropriate scalar multiple, beta , yields a change of basis matrix that is a permutation matrix. A construction is presented that often yields bases where the change of basis matrix has low weight, in the case where no irreducible trinomial of degree m exists. A simple formula can be used to compute beta and the weight of the change of basis matrix, given the minimal polynomial of alpha .< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Multiplier/shifter design tradeoffs in a 32-bit microprocessor

The authors concentrate on design tradeoffs between the bit-serial multiplier and the full barrel shifter combined with a large register file. They analyze and compare three alternatives for a given set of technology related parameters and a given set of higher level language (HLL) benchmarks. Although their basic concern is the design of a 32-bit GaAs microprocessor on a single chip, the implications of the results are more general.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Efficient bit-serial multiplication and the discrete-time Wiener-Hopf equation over finite fields

Discrete-time Wiener-Hopf equations (DTWHEs) over finite fields are considered. It is shown that solving the DTWHE is equivalent to performing division over finite fields. The proof provides a new interpretation of the relationship between bit-serial multiplication and DTWHEs. The interpretation enables bit-serial multiplication over GF(2/sup m/) to be understood more easily. As an example, bit-serial multiplication methods for multiplying any two elements that can be done without performing any transformation, or with only a simple transformation of the bases, are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Bit-serial modular multiplier

A bit-serial modular multiplier is presented which uses a table look-up method to perform modular reduction. Since the dock frequency is independent of word length, this design is most useful when dealing with large integers, and is required by many modern cryptographic systems.

Reconfigurable testable bit-serial multiplier for DSP applications

A new testable and reconfigurable bit-serial multiplier is proposed. Fault tolerance is established through built-in self-testing and dynamic reconfiguration. During the reconfiguration phase, the faulty modules of the multiplier are automatically isolated and the system reconfigures itself for the required function with no need for external interference. Quadruple-double modular redundancy (QDMR) techniques are employed to allow the isolation of the bad modules and the use of only good ones. The faulty cells are located and the diagnostic information is scanned out for evaluation. The followed design method supports a two-level testing strategy, in which the multiplier is tested by a small built-in test circuit and the test circuit itself is tested externally by a scan-path technique, providing high fault coverage. This design method adopts the functional building block concept and is especially suitable for linear arrays. The multiplier is based on the bit-serial approach, which has been proven to be an efficient implementation for several digital-signal-processing (DSP) structures; it accepts 2 s complement data and coefficients in a serial form. A prototype of an 8-bit multiplier has been implemented in single-layer metal 2 μm CMOS technology; it has an area of 2.64 mm×1.91 mm (without I/O pads) and contains approximately 2500 devices.

Design alternatives for adaptive digital lattice filters and a new bit-serial architecture

The problem of the efficient realization of an adaptive digital linear prediction filter is investigated, and three implementation approaches are examined: a single-chip general-purpose digital signal processor realization, a multi-chip, multiplexed architecture, and a multichip systolic array approach. In addition, the complete architecture and organization of a systolic-type realization is also presented. A single-chip lattice stage of the systolic architecture contains both the filtering section and the adaptation logic which is based on the stochastic gradient adaptation algorithm. The filter-stage architecture uses bit-serial arithmetic by employing five bit-serial multipliers and four single-bit adders integrated on a single chip. Chips can be cascaded to obtain multiple-stage filters. The filter architecture is designed to operate with 17-bit, two's complement, fixed-point data with 16-bit precision. At an estimated 8.5-MHz clock rate, the chip could accommodate applications with data sampling rates of 500 KHz.