Bitline Delay Research Articles

Pre-Emphasis Pulse Design for Reducing Bit-Line Access Time in NAND Flash Memory

This paper describes pre-emphasis (PE) pulses to reduce bit-line (BL) access time in NAND flash memory. Optimum PE pulse widths and resultant minimum BL delay times are investigated, where the BL delay is determined by the sense current at the input terminal of a sensing circuit in contrast with the word-line (WL) delay that is determined by the WL voltage at the gate of a selected memory cell. Two BL models are used, namely, a single-line model (SLM) for the shielded BL read operation and a three-line model (TLM) for the all-BL read operation. Under the condition that the sense current delay is defined by the time when the sense current becomes stable between 110% and 90% of the cell current and the BL voltage delay is defined by the time when the BL voltage at the selected cell reaches a window between 110% and 90%, SPICE simulation results show that the sensed current delay and the BL voltage delay are reduced by 43% and 36% in the case of SLM and by 16% and 28% in the case of TLM, respectively. Thus, the key results are the following: (1) PE pulses are effective to reduce the sense current delay time for BL access, as well as the BL voltage delay time for both SLM and TLM; (2) the sensitivity of the PE pulse on the delay time is much larger for the sensed current delay than the BL voltage delay due to the absence of filtering with the RC delay element in BL delay; and (3) address-dependent PE pulse control can reduce the sense current delay significantly, especially for access to cells closely located to the sensing circuit.

MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing

Magnetic tunnel junction is first integrated into Loop Replica Bit-Line for robust MRAM sensing. The replica bit-line with the replica bit-cells is used to generate sensing enable signal for bit-line delay tracking. As a realization of MTJ device and MRAM circuit interaction, a tunable MTJ-based loop structure with a group of replica cells is applied to control the timing of STT-MRAM, using optimal MTJ resistance at either parallel or anti-parallel state. The logic delay among the discharging groups is compensated for removing its impact on the target timing. The proposed MTJ-LRB structure was implemented with 28-nm CMOS process and 40nm $\times 40$ nm spin-transfer-torque MTJ device, and evaluated in a $512\times 512$ MRAM array. Simulation results show that the sensing latency variation can be reduced by 87.8% and 76.2% compared with the traditional inverter chains and a previous replica BL technique. The proposed MTJ-LRB achieves enhanced timing scheme and process-voltage-temperature tracking ability, which could be applied to future non-volatile memory design.

A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process

With advances in semiconductor technology, the threshold voltage variation has worsened, which has a great impact on the speed and stability of static random access memory (SRAM). This paper proposes a pipeline replica bitline (RBL) delay technique designed to reduce the timing variation of SRAM sense amplifiers. This design takes full advantage of all cells in the RBL as replica cells (RCs). A tunable pipeline structure is applied to control the discharge of groups of RCs. The structure is designed based on theoretical analysis and fabricated using an SMIC 28-nm CMOS process. The measurement results show that the delay variation can be reduced by approximately 43% and 32% compared with the conventional RBL and multistage RBL, respectively. Furthermore, with slight tuning of the normal 28-nm foundry process, four wafers were obtained under extreme conditions to comprehensively test the proposed technique. The results show that the proposed technique is more stable than other techniques in any extreme condition.

Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier

A multi-stage dual replica bit-line delay (MDRBD) technique is proposed for reducing access time by suppressing the sense-amplifier enable (SAE) timing variation of low voltage static random-access memory (SRAM) applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-line (RBL) capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology (Taiwan Semiconductor Manufacturing Company, Taiwan).

High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost

A gate array has a great advantage in that the extra cost required for customizing VLSI masks is low and the lead time needed to obtain an ASIC is short. Hence, it is widely and generally used in the ASIC industry as a major semicustomized VLSI design methodology. This paper presents high-density RAM/ROM macros using memory-oriented CMOS gate-array base cells. The metatile methodology along with a hierarchical verification technique is used for macro design; all the interconnection wires needed to generate a RAM/ROM macro are installed in each physical leaf cell by way of preparation. The macro size is configurable regarding both word count and bit width. Moreover, back annotations after generating a macro are not necessary because there are no unknown factors such as parasitic resistance and/or capacitance. To reduce the power consumption of RAM/ROM macros, six narrow-channel MOSFETs (two pMOSs and four nMOSs) are prepared in the base cell, resulting in a new 10-transistor-type base cell. Using one single base cell, we can implement an SRAM cell (up to two ports), a 4-bit ROM cell, or a 2-input logic gate. When designing the ROM cell, we adopt a double-rail bitline scheme to shorten the bitline delay. Another high-speed technique is to use a new current-mirror sense amplifier. Owing to the high sensitivity (47 mV) of this amplifier, we have successfully reduced the required read bitline signal from 300 to 100 mVpp. With regards to layout techniques, we propose a new high-density address decoder using a subdecoder and complex logic gates. In addition, some verification techniques using phantom base cells are devised. These techniques are confirmed with a gate-array RAM/ROM macro test chip fabricated with a 0.6- $\mu \text{m}$ low cost, CMOS process. With a two-port SRAM with 256 cells/bitline, the address access time under typical conditions of 3.3 V and 25 °C is 7.125 ns and the power-supply current at a 40-MHz operation is 3.8 mA for an I/O-data width of 1 bit.

ASYNCHRONOUS INSTRUCTION CACHE MEMORY FOR AVERAGE-CASE PERFORMANCE

This paper presents an asynchronous instruction cache memory for average-case performance, rather than worst-case performance. Even though the proposed instruction cache design is based on a fixed delay model, it can achieve high throughput by employing a new memory segmentation technique that divides cache memory cell arrays into multiple memory segments. The conventional bit-line memory segmentation divides a whole memory system into multiple segments so that all memory segments have the same size. On the contrary, we propose a new bit-line segmentation technique for the cache memory which consists of multiple segments but all the memory segments have the same delay bound for themselves. We use the resister-capacitor (R-C) modeling of bit-line delay for content addressable memory–random access memory (CAM–RAM) structure in a cache in order to estimate the total bit-line delay. Then, we decide the number of segments to trade-off between the throughput and complexity of a cache system. We synthesized a 128 KB cache memory consisting of various segments from 1 to 16 using Hynix 0.35-μm CMOS process. From the simulation results, our implementation with dividing factor 4 and 16 can reduce the average cache access time to 28% and 35% when compared to the non-segmented counterpart system. It also shows that our implementation can reduce the average cache access time by 11% and 17% when compared to the bit-line segmented cache that consists of the same number of segments that have the same size.

An auto-calibrated, dual-mode SRAM macro using a hybrid offset-cancelled sense amplifier

A dual-mode power and performance optimized SRAM is presented. Given the fact that the power and speed associated with the cell access time are directly related to the sense amplifier offset a new optimization platform based on the hybrid offset-cancelled current sense amplifier (OCCSA) [1] is presented. It is shown that the speed and power overhead of the offset cancellation can be optimized in a multi-variable auto-calibration loop to achieve the lowest power or the highest performance mode. The flexibility of having two degrees of freedom in OCCSA offers a significant bitline delay reduction with minimum power sacrifice in the high performance mode. The proposed scheme is verified using a macro cell implemented in a 0.18μm CMOS technology. In the Power Optimized mode, a wide range of offset is applied to a single column test structure and 25% energy consumption reduction is measured compared to the conventional case. For a 32kb SRAM array, compared to a conventional sense amplification, a 2X reduction in energy consumption is achieved in the Energy Optimized mode. Thanks to the offset cancelling nature of the proposed scheme, a 2X improvement in cell access time is achieved in the Speed Optimized mode.

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

A digitized replica bitline delay technique has been proposed for random-variation-tolerant timing generation of static random access memory (SRAM) sense amplifiers (SA). The timing variation of SA attributable to the random variation of transistor threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) is reduced by a sufficient count of replica cells, and replica bitline delay is digitized and multiplied to adjust it to the target timing for SA. The variation of the generated timing was 41% smaller than that with a conventional technique and cycle time was reduced 20% at the supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) of 0.6 V in 40 nm CMOS technology with this scheme.

A New Differential-Amplifier-Based Offset-Cancellation Sense Amplifier for Speed-Improvement of High-Density Static Random Access Memories in Scaled-Down Complementary Metal–Oxide–Semiconductor Technology

A new differential-amplifier-based offset-cancellation sense amplifier (DOCSA) is proposed in order to improve operation speed of high-density, six-transistor-cell static random access memories (SRAMs) in scaled-down complementary metal–oxide–semiconductor (CMOS) technology. 40-nm node CMOS test chips were fabricated and measured to demonstrate the successful operation and performance of DOCSA. Simulated offset voltage of DOCSA was 60% compared to that of a conventional latch-type sense amplifier with the same input capacitance, and the bit-line delay in an SRAM is expected to be 60% by using DOCSA. The standard deviation of measured offset voltage in DOCSA agreed well with that of the simulated one. Combination of CMOS scaling and deviation-relief circuit technology becomes important in advanced LSI technology.

Design Technology of stacked NAND type 1-transistor FeRAM

Design technology of stacked NAND type 1-transistor FeRAM has been described. With 39nm design rule feasibility study of 1Tbit memory focused on cell array structure and core circuit has been investigated. 64 layer 8k×8k stacked SGT memory cell array structure and the double ended row and column decoder with SGT have been newly introduced.From the estimation of wordline and bitline delay time this structure enables to reduce the delay time of core circuit to 5ns. Stacked NAND type 1-transistor FeRAM is a promising candidate for realizing fast access time of 50ns.

Low-Power Logic Circuit and SRAM Cell Applications With Silicon on Depletion Layer CMOS (SODEL CMOS) Technology

In this paper, the switching performance of Silicon on Depletion Layer CMOS (SODEL CMOS) is investigated with a view to realizing high-speed and low-power CMOS applications. Thanks to smaller parasitic capacitance, the propagation delay time (/spl tau//sub pd/) in SODEL CMOS has been improved by up to 25% compared to that of conventional bulk CMOS in five stacked nFET inverters at the same V/sub dd/. It is also confirmed that about 30% better power-delay product can be realized at the same /spl tau//sub pd/ with reduced V/sub dd/ in SODEL CMOS. In SRAM cell applications, SODEL CMOS shows high Static Noise Margin (SNM) of /spl sim/95 mV at V/sub dd/=0.6 V. Smaller bitline delay is expected and confirmed in SODEL CMOS SRAM by SPICE simulations. Latch-up immunity for /spl alpha/-particle irradiation in SODEL CMOS was also found to be comparable to that of conventional bulk CMOS. Therefore, SODEL CMOS device and circuit technology is expected to provide a better solution for low-power system-on-a-chip (SoC).

A 6-GHz 16-kB L1 cache in a 100-nm dual-v t technology using a bitline leakage reduction (blr) technique

This work describes an aggressive SRAM cell configuration using dual-V/sub T/ and minimum channel length to achieve high performance. A bitline leakage reduction technique is incorporated into an L1 cache design using the new cell in a 100-nm dual-V/sub T/ technology to eliminate impacts of bitline leakage on performance and noise margin with minimal area overhead. Bitline delay is 23% better than the best conventional design, thus enabling 6-GHz operation at with 15% higher energy.

1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs

Multithreshold-voltage CMOS (MTCMOS) has a great advantage of lowering physical threshold voltages without increasing the power dissipation due to large subthreshold leakage currents. This paper presents the embedded SRAM techniques for high-speed low-power MTCMOS/SIMOX application-specified integrated circuits (ASICs) that are operated with a single battery cell of around 1 V. In order to increase SRAM operating frequency, a pseudo-two stage pipeline architecture is proposed. The address decoder using a pass-transistor-type NAND gate and a segmented power switch presents a short clocked wordline selection time. The large bitline delay in read operations is greatly shortened with a new memory cell using extra low-V/sub th/ nMOSs. The small readout signal from memory cells is detected with a high-speed MTCMOS sense amplifier, in which a pMOS bitline selector is merged. The wasted power dissipation in writing data is reduced to zero with a self-timed writing action. A 8 K-words/spl times/16-bits SRAM test chip, fabricated with a 0.35-/spl mu/m MTCMOS/SIMOX process (shortened effective channel length of 0.17 /spl mu/m is available), has demonstrated a 100-MHz operation under the worst power-supply condition of 1 V. At a typical 1.2 V, the power dissipation during the standby time is 0.2-/spl mu/W and that of a 100-MHz operation with a checkerboard test pattern is 14 mW for single fan-in loads.

A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM's

Fast and low-power circuit techniques for battery-operated low-voltage SRAM's are described. To shorten the read access time with low power dissipation, the step-down boosted-wordline scheme, which is combined with current-sense amplifiers, is proposed. Boosting a selected-wordline voltage shortens the bitline delay before the stored data are sensed. The power dissipation while selecting a wordline is suppressed by stepping down the selected-wordline potential. Moreover, to reduce the standby power, a switched-capacitor-type boosted-pulse generator, which is controlled by an address transition detection (ATD) signal, is used. A 61 kword/spl times/16-bit organization SRAM test chip was fabricated using the 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) process. The power dissipation in the memory array is reduced to 57% (1 mW) at 10 kHz operation in comparison with the conventional boosted-wordline scheme.

25-ns 256K×1/64K×4 CMOS SRAM's

Through a metal option, a 256K word/spl times/1-bit and a 64K word/spl times/4-bit CMOS SRAM organization has been obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address-transition-detector circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-/spl mu/m double-polysilicon and single-metal process technology with a polycide gate offers a memory cell size of 90 /spl mu/m/SUP Z/ and a chip size of 47.4 mm/SUP 2/.