Bit-level Systolic Array Research Articles

High-speed easily testable Galois-field inverter

Galois field (GF) computation is important in applications such as error-control coding, switching theory, and cryptography. In GF, division and inversion operations are much harder to implement in digital logic as compared with multiplication and addition operations so far as performance and hardware complexity is concerned. Although several VLSI structures for division or inversion have been proposed in the past, most of them have complex routing, nonmodular architectures, and low testability. Testability especially is an increasing concern in VLSI design. In this paper, C-testable bit-level systolic arrays for GF(2/sup m/) inversion are presented. We propose a counter-free extended Euclidean algorithm for GF inversion. Based on the algorithm, we obtain efficient systolic GF inverters, which are extendible to GF dividers. Both the bit-parallel and bit-serial inverters proposed are shown to be easily testable. For example, the bit-serial inverter requires only four test patterns regardless of the field size (or number of cells). High testability is a key advantage for the proposed GF inverters, especially in core-based VLSI system chips.

An efficient VLSI architecture for real-time additive synthesis of musical signals

This paper presents a new architecture for the hardware implementation of additive synthesis for high-quality musical sound generation. A marginally stable second-order infinite-impulse-response filter is used to generate each sinusoid, the frequency, amplitude, and phase of which can independently be specified. A chip has been designed with a bit-level systolic array approach. It is capable of performing 1200 sinusoid real-time synthesis. Furthermore, it is possible to connect up to 11 chips, to achieve an outstanding 13 200 sinusoid synthesis. Two completely independent output channels are available as 20-b streams. The system is clocked at 60 MHz when working with a 44.1-kHz sampling rate. The integrated circuit is designed in a 0.5-/spl mu/m CMOS technology and has a core area of approximately 19 mm/sup 2/.

Data dependence analysis and bit-level systolic arrays of the median filter

The data dependence of the delete-and-insert sort algorithm for median filtering is analyzed in this paper. It is shown that because of data dependence, the fastest throughput rate and the most efficient pipeline scheme cannot be used concurrently. A modified delete-and insert sort algorithm avoiding the above dilemma and its bit-level systolic array implementation are proposed in this paper. The throughput rate of the proposed architecture is equal to one-half (output/clocks) the maximum throughput allowed by the delete-and-insert sort algorithm, and the clock cycle time is equal to the propagation delay of a simple combinational circuit. Its speed is about 1.5 times faster than the existing bit-level systolic array designed by using the same delete-and-insert sort algorithm. The proposed architecture can be designed to operate at different word lengths and different window sizes. It is modular, regular, and of local interconnections and therefore amenable for VLSI implementation.

A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays

In this paper, we discuss the controllability and observability issues in bilateral bit-level systolic arrays. We have introduced a new concept—‘Sj-controllability in M steps’, which is somewhat analogous to the concept of C-testability and refers to the fact that all the cells in the array can be set to the state Sj in at most M steps after initialization. Systolic arrays where the value of M is independent of the length, of the array are characterized. Our testing procedure is based on partitioning the array into several identical subarrays which allows us to apply a repetitive pattern of tests and propagate test outcome to the observable extremities so that every cell in the array is tested by a minimum sequence of tests. Based on this concept,we have developed a set of sufficient conditions for an arbitrary bilateral bit-level systolic array to be testable for single faults.

Bit-level systolic arrays for finite-field multiplications

Galois-field multiplication algorithms and their systolic realizations are proposed. Parallel and serial architectures as well as their VLSI implementations are presented. They are based on the standard-basis representation of the Galois-field elements. Our algorithms allow the two operands to enter the systolic arrays in the same order. Only one control signal for the serial systolic array is required as compared to two in the previous design. Our multipliers are more regular and modular, requiring simple control signal, and compact in terms of silicon area; they are well suited to VLSI implementation. Expansion to higher order Galois fields are easier to realize than other multipliers. High throughput rates are achieved due to their systolic array architectures.

A bit-level systolic implementation of the median filter

A novel median filter has been implemented by using a bit-level systolic array. The filter saves more than 23% of transistors when compared with conventional designs. The median filter may be clocked to a maximum 100 MHz for real-time applications. The bit-level systolic array is designed for unlimited word length and extension to larger window sizes.

LILA: layout generation for iterative logic arrays

A CAD tool, LILA, that generates layouts of both one-dimensional and two-dimensional iterative logic arrays, described in VHDL or schematic structures, is presented. Such a tool is very important because in current industry, the generation of high density iterative logic arrays (such as data paths in microprocessors) is still mainly performed manually, and is a major bottleneck of the design. In LILA, interconnections between modules (i.e., cells) of the array do not need to be between adjacent modules and functions of modules of the array do not need to be identical. Regularity in module functions and interconnections between modules are automatically extracted by the tool. Based on interconnection wire length between modules, layouts of modules and interconnections are optimized in a single step. The signals in each array module are generated in such a way that signals in adjacent modules are perfectly aligned and connected by module abutments. As no global routing or channel routing between modules are necessary, the total layout area and propagation delay between modules are minimal. The proposed system is especially useful for data path modules, bit-level systolic arrays, storage devices, and many other regular structures, and has been actually implemented in a design environment. Extensive experiments have shown that the system has a very good performance and produces layouts of very high density. The tool takes about 1.6 CPU seconds to generate an eight-by-eight array divider on a SUN SPARCstation II. >

Bit-level systolic array for fast exponentiation in GF(2/sup m/)

This paper presents a new parallel-in-parallel-out bit-level systolic array with unidirectional data flow for computing exponentiation in GF(2/sup m/). The array is highly regular, modular, and thus well suited to very-large-scale-integration implementation. In addition, it can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. As compared with a previously known systolic GF(2/sup m/) exponentiator with the same throughput performance, the proposed system requires much less chip area, has small latency, and is easier to incorporate fault-tolerant design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Dynamic computational blocks for bit-level systolic arrays

Integrated dynamic logic trees with latches provide cost effective circuit techniques for building massively pipelined, systolic, computational blocks operating at the bit level. Recent results have demonstrated that dynamic pipelines are capable of very high switching speeds with appropriate circuit design techniques. In this paper we trade some of this speed for much higher functionality of each logic block. The resulting throughput rate remains sufficiently high for useful applications, but results in substantial area and power savings. Design techniques for the individual logic trees (switching trees) are based on simple graph theoretic rules. Examples are shown to support the technique.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Bit-serial VLSI implementation of delayed LMS adaptive FIR filters

The delayed least-mean-square (DLMS) algorithm is useful for adaptive finite impulse response (FIR) filtering applications where high throughput rates are required. In the paper, a bit-serial bit-level systolic array based on new schemes for multiplication and inner-product computation is presented to implement DLMS adaptive N-tap FIR filters. The architecture is highly regular, modular, and thus well-suited to VLSI implementation. It has an efficiency of 100% and a throughput rate of one filter output per 2B cycles, where B is the word length of input data. In addition, the proposed array uses a small delay of [(4B+N/2+4)/2B] in the filter coefficient adaptation, where [x] is the smallest integer greater than or equal to x. This ensures that the DLMS algorithm can have good performance under proper selection of the step size. Based on a conservative design technique of static complementary metal oxide semiconductor (CMOS) logic, it is shown that the proposed system can be realized in a single chip for most practical applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

70-MHz 2- mu m CMOS bit-level systolic array median filter

An algorithm for VLSI median filtering of one-dimensional signals of complexity linearly dependent on the filter window length is described. The algorithm is implemented as a bit-level systolic array (BLSA), in order to achieve high performance. A single-chip median filter characterized by a window length of 25 8-b samples, and by operation on three interleaved independent sequences for a total of 75 samples, is presented as a demonstration of the concept. The throughput relevant to one sequence is 1/3 for this chip, whereas the theoretical maximum allowed by the algorithm is 1/2. Prototypes designed with a 2- mu m CMOS technology have been successfully tested at a clock frequency over 70 MHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

BIT-LEVEL SYSTOLIC ARRAYS FOR DIGITAL CONTOUR SMOOTHING BY ABEL-POISSON KERNEL

Two different bit-level systolic arrays for digital contour smoothing by Abel-Poisson kernel which minimize the execution time and the number of functional elements required are suggested. The arrays are fully pipelined on the bit-level achieving very high clock frequency. They are implementable in VLSI and are dedicated for real-time applications.

An efficient systolic array implementation of the sign-LMS algorithm

A bit-level systolic array of the implementation of the LMS algorithm is presented. The array is divided into a 2D convolver array and a linear updater array. The structure is 100% data flow efficient, requiring N/2 rows to implement N coefficients. The updater is made up of N/2 simple cells. The sign-LMS algorithm is used for updating the coefficients. All coefficients are updated every 2R clocks where R is the number of bits per coefficient and the clock is the bit-level clock (array clock). >

A bit-level systolic array for median filter

A bit-level systolic array for median filters based on the majority of the bit strings of input samples is presented. The majority function can be implemented by a 1-b odd/even transposition network, which is regular and can be designed easily. If each input sample is represented by r bits, the systolic array contains r processor elements and requires time complexity O(N+n+r-1) for a stream of N samples with window size n in a one-dimensional median filter. >

Bit-level pipelined 2-D digital filters for real-time image processing

Bit-level systolic arrays for real-time 2-D FIR and IIR (finite and infinite impulse response) filters are presented. Two-dimensional iteration and retiming techniques are depicted to illustrate block pipeline 2-D IIR filters, which guarantee high-throughput operation for real-time applications. The block (parallel) systolic architectures are refined down to the bit level. This increases the filter's throughput rate and decreases the filter's development and manufacturing costs. The AP figure is improved from O(N/sup 2/W/sup 3/) for the previous design to O(N/sup 2/W/sup 2/), i.e. by a factor of O(W), where W is the word length. Pipelining at the bit rate level is the major reason for this improvement. Another advantage of the proposed design is that it has simpler wire routing and control circuitry. In summary, these systolic-array realizations are more cost effective; more regular structurally; composed of bit-level cells and latches; and fully pipelined at the bit level.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A low-overhead scheme for testing a bit-level finite ring systolic array

Testing large VLSI circuits is a difficult and challenging problem for designers. Large unstructured circuits are often impossible to test. The number of test vectors also tend to be large and difficult to generate using automated tools for testing. In this paper, we have investigated the testing of systolic arrays built from a finite ring cell that has been proposed recently for digital signal processing functions. The cell has been shown to allow encoding, decoding and general inner product type computations for residue number system applications, with considerable advantages over equivalent binary implementation. As a further feature, we show, in this paper, that an array of such cells is remarkably easy to test for stuck-at faults. Generating test vectors for these arrays is also straightforward.

A bit-level systolic architecture for implementing a VQ tree search

A bit-level systolic array system for performing a binary tree Vector Quantization codebook search is described. This consists of a linear chain of regular VLSI building blocks and exhibits data rates suitable for a wide range of real-time applications. A technique is described which reduces the computation required at each node in the binary tree to that of a single inner product operation. This method applies to all the common distortion measures (including the Euclidean distance, the Weighted Euclidean distance and the Itakura-Saito distortion measure) and significantly reduces the hardware required to implement the tree search system.

The design of wave digital filters using fully pipelined bit-level systolic arrays

Wave digital filters (WDF) based on analogue lattice and unit element cascade networks possess important properties that make them suitable for VLSI integration. These include low round-off noise even with short coefficient wordlength and a building block (two-port adaptor) with a very simple structure. Exploiting these properties leads to area efficient designs. Systolic architectures for these WDF networks give the additional advantage of very high sampling rates with potential application in sonar and video signal processing. The bit-level systolic array design of two WDFs is considered in detail, beginning at the filter specification and ending at the VLSI hardware architecture, with discussion of the expected values of the integrated circuit parameters.

The use of data dependence graphs in the design of bit-level systolic arrays

The use of bit-level systolic array circuits as building blocks in the construction of larger word-level systolic systems is investigated. It is shown that the overall structure and detailed timing of such systems may be derived quite simply using the dependence graph and cut-set procedure developed by S.Y. Kung (1988). This provides an attractive and intuitive approach to the bit-level design of many VLSI signal processing components. The technique can be applied to ripple-through and partly pipelined circuits as well as fully systolic designs. It therefore provides a means of examining the relative tradeoff between levels of pipelining, chip area, power consumption, and throughput rate within a given VLSI design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Comparison of two-phase latch configurations for pipelined processors in MOS VLSI: case study: a CMOS systolic multiplier

It is shown that for bit-level pipelined processors whose elements require no precharge phase, pipelining with master-slave latches gives a theoretical maximum throughput of nearly twice that of the Mead-Conway alternating phase arrangement. A comparison is made between area and power requirements as a function of clock rate, both in general terms and with reference to a design example; a pipelined multiplier implemented as a bit-level systolic array.